the following patch was just integrated into master:
commit ab16b336642a5a08ac41b5f0148e48b47ded30ec
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Jul 24 13:13:46 2015 -0500
skylake: use native gpio configuration for uart
Instead of open coding the UART2 gpio configuration use
the support library.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289801
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11176
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11176 for details.
-gerrit
the following patch was just integrated into master:
commit 9506aea3511d626da936df0cee431b6dcabb8734
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Jul 24 13:06:12 2015 -0500
glados: move to native gpio configuration
Instead of relying on FSP to do gpio configuration in one
place use the native support in coreboot. This also removes
the open coded configuration of the memory configuration
ids.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289800
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11175
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11175 for details.
-gerrit
the following patch was just integrated into master:
commit ffdf901c765db8bb01006fa81839fb5703eea4e1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Jul 24 13:00:36 2015 -0500
skylake: provide native gpio functionality
It's important to be able to configure the gpio pads at
various stages instead of a single place using FSP. Without
this support there is a lot of duplicated open-coded pad
configuration taking place both within the SoC code and
mainboards.
Current limitation is that all GPIOs are in ACPI mode. i.e.
The HostSW ownership register sets the pad configuration to
only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The
GPI_STS update is masked within the GPIO community registers.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289789
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11174
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11174 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11227
-gerrit
commit b410af0c68613507637ba97787000baf4230c271
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Thu Aug 13 21:55:30 2015 +0200
seabios integration: deal with ccache woes some more
seabios integration interprets the CC variable with a special case when
ccache is prepended to the compiler.
Since the integration also tries to extract compiler flags (which I'm
not sure we still add to CC _ever_), that also needs to look at only
the part of the string that contains compiler and (maybe) flags, so
skip the first word if it was determined to be the path to the ccache
binary.
Change-Id: I717863f456bf4fd6f08427d86633079ecda039df
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
payloads/external/Makefile.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
index ad1a3ef..6cdb412 100644
--- a/payloads/external/Makefile.inc
+++ b/payloads/external/Makefile.inc
@@ -36,7 +36,7 @@ SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1)
seabios:
$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
HOSTCC="$(HOSTCC)" \
- CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) CFLAGS="$(patsubst $(word $(SEABIOS_CC_OFFSET),$(CC_x86_32))%,,$(CC_x86_32))" \
+ CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) CFLAGS="$(patsubst $(word $(SEABIOS_CC_OFFSET),$(CC_x86_32))%,,$(wordlist $(SEABIOS_CC_OFFSET),9999,$(CC_x86_32)))" \
LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \
OBJDUMP="$(OBJDUMP_x86_32)" \
OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \
the following patch was just integrated into master:
commit 27baa32fbefa19afe2bc96b60f534ca20cb49065
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Wed Aug 12 11:19:10 2015 -0500
cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled
In the wake of the recent Intel "Memoy Sinkhole" exploit a code review
of the AMD SMM code was undertaken. While native Family 10h support
does not appear to be affected by the same SMM flaw, it also does not
require SMM to function. Therefore, the SMM memory range initialization
should only be executed if SMM will be used on the target platform.
Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11211
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/11211 for details.
-gerrit