coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: skylake: add gpe.h for ASL generation
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11233 -gerrit commit 4e7c50da02126332216f9b0e2121cddad9c6e3e4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 13 03:00:54 2015 -0500 skylake: add gpe.h for ASL generation One thing that is brittle is lining up GPE0 bits in ASL and with a board's design proper. This results in open calculated magic numbers. To help alleviate this provide just #defines that C preprocessor can use before handing the source off to the ASL compiler. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Everything's intact. Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293410 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/gpe.h | 137 ++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h new file mode 100644 index 0000000..d8cc1a1 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpe.h @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#endif /* _SOC_GPE_H_ */

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New patch to review for coreboot: Kunimitsu: Enable root ports and clkreqs
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11232 -gerrit commit 9d22701e05b32df88e7d9c99473f4a5237ec3e2d Author: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Date: Wed Jul 22 17:27:56 2015 +0530 Kunimitsu: Enable root ports and clkreqs This patch enables the root ports and configures the clock req numbers as per the design On kunimitsu FAB3 board with D0 MCP Root port 1 --> Wifi card --> clkreq 1 Root port 4 --> Kepler VP8/VP9--> clkreq 2 BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for Kunimitsu and Boot Kunimitsu board with D0 MCP Original-Change-Id: I4e110d2d07efbfa7a306852301cd1cd89027b2ba Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290051 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Change-Id: I6d66c78496ac3f43e07d96feefed35cf50da6aa1 Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 6f03bbf..e414928 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -28,8 +28,15 @@ chip soc/intel/skylake register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" + # Pcie RootPort + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkReqNumber[4]" = "2" + # GPE configuration register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" register "gpe0_en_3" = "0x00000000"

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New patch to review for coreboot: Kunimitsu: Update Mainboard ASL for Kunimitsu FAB3 with D0 MCP
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11231 -gerrit commit 2119d47dbb6b5ca5ea25d78a5dfb3dbf8430b493 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Tue Jul 28 23:30:45 2015 +0530 Kunimitsu: Update Mainboard ASL for Kunimitsu FAB3 with D0 MCP This patch updates the mainboard.asl file to support Kunimitsu FAB3 board which is based on SKL D0 MCP. BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for kunimitsu; booted on kunimitsu FAB3 with D0 MCP Original-Change-Id: I31a315740d49125591591b20c296babe49004166 Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290050 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I81c22e407d1b3d420744eaf1d3f7ff4e8e749bcb Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> --- src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 156 +++++++++++++++-------- 1 file changed, 105 insertions(+), 51 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index a5e7bcf..aa752f9 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -18,18 +18,14 @@ * Foundation, Inc. */ -#define KUNIMITSU_TRACKPAD_IRQ 0x33 -#define KUNIMITSU_TOUCH_IRQ 0x1f +#define BOARD_TRACKPAD_IRQ 0x33 +#define BOARD_TOUCHSCREEN_IRQ 0x1f -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ KUNIMITSU_TRACKPAD_IRQ -#define BOARD_TRACKPAD_I2C_BUS 1 -#define BOARD_TRACKPAD_I2C_ADDR 0x15 - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ KUNIMITSU_TOUCH_IRQ -#define BOARD_TOUCHSCREEN_I2C_BUS 0 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b +#define BOARD_TRACKPAD_I2C_ADDR 0x15 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 +#define BOARD_LEFT_SSM4567_I2C_ADDR 0x34 +#define BOARD_RIGHT_SSM4567_I2C_ADDR 0x35 +#define BOARD_AUDIO_CODEC_I2C_ADDR 0x1A Scope (\_SB) { @@ -54,49 +50,25 @@ Scope (\_SB.PCI0.LPCB) { #include <drivers/pc80/tpm/acpi/tpm.asl> } + Scope (\_SB.PCI0.I2C0) { - Device (ATSB) - { - Name (_HID, "ATML0001") - Name (_DDN, "Atmel Touchscreen Bootloader") - Name (_UID, 4) - Name (_S0W, 4) - Name (ISTP, 0) /* TouchScreen */ - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x27, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } - }) - Method (_STA) - { - Return (0xF) - } - } - Device (ATSA) + Device (ETSA) { - Name (_HID, "ATML0001") - Name (_DDN, "Atmel Touchscreen") + Name (_HID, "ELAN0001") + Name (_DDN, "ELAN Touchscreen") Name (_UID, 5) - Name (_S0W, 4) Name (ISTP, 0) /* TouchScreen */ Name (_CRS, ResourceTemplate() { I2cSerialBus ( - BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C0", // ResourceSource + BOARD_TOUCHSCREEN_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C0", ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { + Interrupt (ResourceConsumer, Edge, ActiveLow) { BOARD_TOUCHSCREEN_IRQ } }) @@ -106,6 +78,7 @@ Scope (\_SB.PCI0.I2C0) } } } + Scope (\_SB.PCI0.I2C1) { Device (ELAN) @@ -113,20 +86,21 @@ Scope (\_SB.PCI0.I2C1) Name (_HID, "ELAN0000") Name (_DDN, "Elan Touchpad") Name (_UID, 3) + /* Allow device to power off in S0 */ Name (_S0W, 4) Name (ISTP, 1) /* TouchPad */ Name (_CRS, ResourceTemplate() { I2cSerialBus ( - BOARD_TRACKPAD_I2C_ADDR, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C1", /* ResourceSource */ + BOARD_TRACKPAD_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C1", ) Interrupt (ResourceConsumer, Edge, ActiveLow) { - KUNIMITSU_TRACKPAD_IRQ + BOARD_TRACKPAD_IRQ } }) Method (_STA) @@ -135,3 +109,83 @@ Scope (\_SB.PCI0.I2C1) } } } + +Scope (\_SB.PCI0.I2C4) +{ + // LEFT SSM4567 I2c ADDR 0x34 + Device (LSPK) + { + Name (_HID, "INT343B") + Name (_CID, "INT343B") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_LEFT_SSM4567_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", + ) + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) // I2S Codec ADI LEFT SSM4567 Enabled + } + } // Device (LSPK) + + // RIGHT SSM4567 I2C ADDR 0x35 + Device (RSPK) + { + Name (_HID, "INT343B") + Name (_CID, "INT343B") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") + Name (_UID, 2) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_RIGHT_SSM4567_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", + ) + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) // I2S Codec ADI RIGHT SSM4567 Enabled + } + } // Device (RSPK) + + // Nuvoton NAU88L25 (I2SC = 2) + Device (HDAC) + { + Name (_HID, "10508825") + Name (_CID, "10508825") + Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_AUDIO_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", + ) + }) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) // I2S Codec Enabled + } + } // Device (HDAC) +} + +

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New patch to review for coreboot: Kunimitsu: Update Gpio table for kunimitsu FAB3 variant
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11230 -gerrit commit 663e40515bc9308afe90d799126d254ce9d44ff5 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Wed Jun 24 21:56:57 2015 +0530 Kunimitsu: Update Gpio table for kunimitsu FAB3 variant This patch updates the GPIO table to support Kunimitsu FAB3 variant, based on SKL D0 MCP. BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for kunimitsu; booted on kunimitsu with D0 MCP. Original-Change-Id: I2343187a919f6d29161069135d97484191198056 Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/289939 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I47302062788a90550fd38cb113e418b21d3f756c Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> --- src/mainboard/intel/kunimitsu/gpio.h | 672 ++++++++++++++++++++++--------- src/mainboard/intel/kunimitsu/ramstage.c | 2 +- 2 files changed, 476 insertions(+), 198 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index e81ad51..6a9cec1 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -18,205 +18,483 @@ * Foundation, Inc. */ -#ifndef _GPIO_H_ -#define _GPIO_H_ +#ifndef _MAINBOARD_GPIO_H_ +#define _MAINBOARD_GPIO_H_ #include <soc/gpio.h> -const GPIO_INIT_CONFIG GpioTableKunimitsu[] = { -{GPIO_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioTermNone}}, -{GPIO_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, (GpioIntApic|GpioIntLevel), GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow,GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh,GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow,GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh,GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, -{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow,GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow,GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, (GpioIntApic|GpioIntLevel), GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh,GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, - GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutLow,GpioIntDis, GpioResetDeep, GpioTermNone}}, -{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, +const GPIO_INIT_CONFIG mainboard_gpio_table[] = { +//Primary Well Group A +/* EC_PCH_RCIN */ +{ GPIO_LP_GPP_A0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* LPC_LAD_0 */ +{ GPIO_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* LPC_LAD_1 */ +{ GPIO_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioTermNone} }, +/* LPC_LAD_2 */ +{ GPIO_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* LPC_LAD_3 */ +{ GPIO_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* LPC_FRAME */ +{ GPIO_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* LPC_SERIRQ */ +{ GPIO_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* XDP_PREQ */ +{ GPIO_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* LPC_CLKRUN */ +{ GPIO_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EC_LPC_CLK */ +{ GPIO_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_LPC_CLK */ +{ GPIO_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EC_HID_INT */ +{ GPIO_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ISH_KB_PROX_INT */ +{ GPIO_LP_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_SUSPWRACB */ +{ GPIO_LP_GPP_A13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PM_SUS_STAT */ +{ GPIO_LP_GPP_A14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_SUSACK */ +{ GPIO_LP_GPP_A15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_1P8_SEL */ +{ GPIO_LP_GPP_A16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_PWR_EN */ +{ GPIO_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* GYRO INTERRUPT */ +{ GPIO_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ALS INTERRUPT / SNSR_HUB_INT */ +{ GPIO_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ISH_GYRO_DRDY/ACCEL INTERRUPT */ +{ GPIO_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SNSR_HUB_STANDBY_WAKE */ +{ GPIO_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +//Primary Well Group B + +{ GPIO_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* HSJ_MIC_DET */ +{ GPIO_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* TRACKPAD_INT */ +{ GPIO_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, + GpioTermNone} }, +/* BT_RF_KILL */ +{ GPIO_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* WIFI_CLK_REQ */ +{ GPIO_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* KEPLR_CLK_REQ/VIDEO_CLK_REQ */ +{ GPIO_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* SSD_CLK_REQ/CLK_REQ_SSD */ +{ GPIO_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* MPHY_EXT_PWR_GATE */ +{ GPIO_LP_GPP_B11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* PM_SLP_S0 */ +{ GPIO_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_PLT_RST */ +{ GPIO_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* WWAN_DISABLE */ +{ GPIO_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* WLAN_PCIE_WAKE */ +{ GPIO_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* SSD_PCIE_WAKE */ +{ GPIO_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* CCODEC_SPI_CS */ +{ GPIO_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* CODEC_SPI_CLK */ +{ GPIO_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* CODEC_SPI_MISO */ +{ GPIO_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* CODEC_SPI_MOSI */ +{ GPIO_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +//Primary Well Group C +/* SMB_CLK */ +{ GPIO_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SMB_DATA */ +{ GPIO_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* M2_WWAN_PWREN */ +{ GPIO_LP_GPP_C3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EC_IN_RW */ +{ GPIO_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* USB_CTL */ +{ GPIO_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_C8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_C9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* NFC_RST* */ +{ GPIO_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EN_PP3300_KEPLER */ +{ GPIO_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K} }, +/* PCH_MEM_CFG0 */ +{ GPIO_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_MEM_CFG1 */ +{ GPIO_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_MEM_CFG2 */ +{ GPIO_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_MEM_CFG3 */ +{ GPIO_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2C0_SDA */ +{ GPIO_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpu5K} }, +/* I2C0_SCL */ +{ GPIO_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpu5K} }, +/* I2C1_SDA */ +{ GPIO_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2C1_SCL */ +{ GPIO_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* GD_UART2_RXD */ +{ GPIO_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* GD_UART2_TXD */ +{ GPIO_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* TCH_PNL_PWREN */ +{ GPIO_LP_GPP_C22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SCREW_SPI_WP_STATUS */ +{ GPIO_LP_GPP_C23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K} }, + +// Primary Well Group D +/* ITCH_SPI_CS */ +{ GPIO_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ITCH_SPI_CLK */ +{ GPIO_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ITCH_SPI_MISO */ +{ GPIO_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* CAM_FLASH_STROBE */ +{ GPIO_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EN_PP3300_DX_EMMC */ +{ GPIO_LP_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EN_PP1800_DX_EMMC */ +{ GPIO_LP_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SH_I2C1_SDA */ +{ GPIO_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SH_I2C1_SCL */ +{ GPIO_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* USB_A0_ILIM_SEL */ +{ GPIO_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* USB_A1_ILIM_SEL */ +{ GPIO_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EN_PP3300_DX_CAM */ +{ GPIO_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EN_PP1800_DX_AUDIO */ +{ GPIO_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* WWAN_WAKE* */ +{ GPIO_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_D15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_D16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* DMIC_CLK_1 */ +{ GPIO_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* DMIC_DATA_1 */ +{ GPIO_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* DMIC_CLK_0 */ +{ GPIO_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* DMIC_DATA_0 */ +{ GPIO_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ITCH_SPI_D2 */ +{ GPIO_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* ITCH_SPI_D3 */ +{ GPIO_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2S_MCLK */ +{ GPIO_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +//Primary Well Group E +/* SPI_TPM_IRQ */ +{ GPIO_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SSD_PEDET */ +{ GPIO_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SSD_SATA_DEVSLP */ +{ GPIO_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* TCH_PNL_INTR* */ +{ GPIO_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, (GpioIntApic | GpioIntLevel), + GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* USB2_OC_0 */ +{ GPIO_LP_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* USB2_OC_1 */ +{ GPIO_LP_GPP_E10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* USB2_OC_2 */ +{ GPIO_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* USB2_OC_3 */ +{ GPIO_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* DDI1_HPD */ +{ GPIO_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* DDI2_HPD */ +{ GPIO_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* EC_SMI */ +{ GPIO_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* EC_SCI */ +{ GPIO_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* EDP_HPD */ +{ GPIO_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* TCH_PNL_RST */ +{ GPIO_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, + GpioIntDis, GpioResetDeep, GpioTermNone} }, +//Primary Well Group F +/* I2S2_SCLK */ +{ GPIO_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2S2_SFRM */ +{ GPIO_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2S2_TXD */ +{ GPIO_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2S2_RXD */ +{ GPIO_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ GPIO_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2C4_SDA */ +{ GPIO_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* I2C4_SDA */ +{ GPIO_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* AUDIO_IRQ */ +{ GPIO_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* AUDIO_SW_INT* */ +{ GPIO_LP_GPP_F11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, + GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* EMMC_CMD */ +{ GPIO_LP_GPP_F12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_0 */ +{ GPIO_LP_GPP_F13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_1 */ +{ GPIO_LP_GPP_F14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_2 */ +{ GPIO_LP_GPP_F15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_3 */ +{ GPIO_LP_GPP_F16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_4 */ +{ GPIO_LP_GPP_F17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_5 */ +{ GPIO_LP_GPP_F18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_6 */ +{ GPIO_LP_GPP_F19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_D_7 */ +{ GPIO_LP_GPP_F20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_RCLK */ +{ GPIO_LP_GPP_F21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EMMC_CLK */ +{ GPIO_LP_GPP_F22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* USIM_DET */ +{ GPIO_LP_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +//Primary Well Group G +/* SD_CMD */ +{ GPIO_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_D_0 */ +{ GPIO_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_D_1 */ +{ GPIO_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_D_2 */ +{ GPIO_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_D_3 */ +{ GPIO_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_CD */ +{ GPIO_LP_GPP_G5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* SD_CLK */ +{ GPIO_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* SD_WP */ +{ GPIO_LP_GPP_G7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, + +//Deep Sleep Well Group +/* PCH_BATLOW */ +{ GPIO_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* EC_PCH_ACPRESENT */ +{ GPIO_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* EC_PCH_WAKE */ +{ GPIO_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, +/* EC_PCH_PWRBTN */ +{ GPIO_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, +/* PM_SLP_S3 */ +{ GPIO_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PM_SLP_S4 */ +{ GPIO_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_SLP_SA */ +{ GPIO_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* USB_WAKEOUT_INTRUDET */ +{ GPIO_LP_GPD7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PM_SUSCLK */ +{ GPIO_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutLow, + GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_SLP_WLAN */ +{ GPIO_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PCH_SLP_S5 */ +{ GPIO_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +/* PM_LANPHY_ENABLE */ +{ GPIO_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, + GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, +{ END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, + GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone} }, }; #endif diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index f9b2764..34fac28 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -19,5 +19,5 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { /*update gpio table*/ - params->GpioTablePtr = (UINT32 *)GpioTableKunimitsu; + params->GpioTablePtr = (UINT32 *)mainboard_gpio_table; }

1 0

New patch to review for coreboot: ifdtool: handle region masks correctly
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11229 -gerrit commit 5bac4fa7428bf43a69fd72a5eb5c752335606d16 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 12 11:44:02 2015 -0500 ifdtool: handle region masks correctly The get_region() function was using fixed masks for the base and limit. However, newer descriptors (on skylake, e.g.) use a 15-bit mask -- not a 12-bit one. Choose the right mask based on ifd_version. BUG=chrome-os-partner:43461 BRANCH=None TEST=Built glados bootimage. Original-Change-Id: Ibcbfd649a561d36b17ea2cc8fbeb30ffdbbb2c96 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293250 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I7f2ef9fb8e5b6c7114225fecc2798668d6507ac3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/ifdtool/ifdtool.c | 41 ++++++++++++++++++++++------------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 6856400..214998c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -101,52 +101,55 @@ static void check_ifd_version(char *image, int size) static region_t get_region(frba_t *frba, int region_type) { + int base_mask; + int limit_mask; + uint32_t *flreg; region_t region; - region.base = 0, region.limit = 0, region.size = 0; + + if (ifd_version >= IFD_VERSION_2) + base_mask = 0x7fff; + else + base_mask = 0xfff; + + limit_mask = base_mask << 16; switch (region_type) { case 0: - region.base = (frba->flreg0 & 0x00000fff) << 12; - region.limit = ((frba->flreg0 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg0; break; case 1: - region.base = (frba->flreg1 & 0x00000fff) << 12; - region.limit = ((frba->flreg1 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg1; break; case 2: - region.base = (frba->flreg2 & 0x00000fff) << 12; - region.limit = ((frba->flreg2 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg2; break; case 3: - region.base = (frba->flreg3 & 0x00000fff) << 12; - region.limit = ((frba->flreg3 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg3; break; case 4: - region.base = (frba->flreg4 & 0x00000fff) << 12; - region.limit = ((frba->flreg4 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg4; break; case 5: - region.base = (frba->flreg5 & 0x00000fff) << 12; - region.limit = ((frba->flreg5 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg5; break; case 6: - region.base = (frba->flreg6 & 0x00000fff) << 12; - region.limit = ((frba->flreg6 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg6; break; case 7: - region.base = (frba->flreg7 & 0x00000fff) << 12; - region.limit = ((frba->flreg7 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg7; break; case 8: - region.base = (frba->flreg8 & 0x00000fff) << 12; - region.limit = ((frba->flreg8 & 0x0fff0000) >> 4) | 0xfff; + flreg = &frba->flreg8; break; default: fprintf(stderr, "Invalid region type %d.\n", region_type); exit (EXIT_FAILURE); } + region.base = (*flreg & base_mask) << 12; + region.limit = ((*flreg & limit_mask) >> 4) | 0xfff; region.size = region.limit - region.base + 1; + if (region.size < 0) region.size = 0;

1 0

New patch to review for coreboot: ifdtool: Update to support Skylake+ descriptor format
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11228 -gerrit commit 0bd43f6b289128754ecaae5721e6120bf00909a0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 22 11:14:48 2015 -0700 ifdtool: Update to support Skylake+ descriptor format The descriptor format has changed with Skylake and some fields have moved or been expanded. This includes new SPI frequencies and chip densities, though unfortunately 30MHz in the new format conflicts with 50MHz in the old format... There are also new regions with a few reserved regions inserted before a new embedded controller region. Unfortunately there does not seem to be a documented version field so there does not seem to be an official way to determine if a specific descriptor is new or old. To work around this ifdtool checks the hardcoded "SPI Read Frequency" to see if it set for 20MHz (old descriptor) or 17MHz (new descriptor). BUG=chrome-os-partner:40635 BUG=chrome-os-partner:43461 BRANCH=none TEST=run ifdtool on skylake and broadwell images Original-Change-Id: I0561b3c65fcb3e77c0a24be58b01db9b3a36e5a9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281001 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9a08c26432e13c4000afc50de9d8473e6f911805 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293240 --- util/ifdtool/ifdtool.c | 223 +++++++++++++++++++++++++++++++++++++++---------- util/ifdtool/ifdtool.h | 22 ++++- 2 files changed, 201 insertions(+), 44 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 8d5d059..6856400 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -31,14 +31,18 @@ #define O_BINARY 0 #endif -#define NUM_REGIONS 5 +static int ifd_version; -static const struct region_name region_names[NUM_REGIONS] = { +static const struct region_name region_names[MAX_REGIONS] = { { "Flash Descriptor", "fd" }, { "BIOS", "bios" }, { "Intel ME", "me" }, { "GbE", "gbe" }, - { "Platform Data", "pd" } + { "Platform Data", "pd" }, + { "Reserved", "res1" }, + { "Reserved", "res2" }, + { "Reserved", "res3" }, + { "EC" "ec" }, }; static fdbar_t *find_fd(char *image, int size) @@ -58,11 +62,43 @@ static fdbar_t *find_fd(char *image, int size) return NULL; } - printf("Found Flash Descriptor signature at 0x%08x\n", i); - return (fdbar_t *) (image + i); } +/* + * There is no version field in the descriptor so to determine + * if this is a new descriptor format we check the hardcoded SPI + * read frequency to see if it is fixed at 20MHz or 17MHz. + */ +static void check_ifd_version(char *image, int size) +{ + fdbar_t *fdb = find_fd(image, size); + fcba_t *fcba; + int read_freq; + + if (!fdb) + exit(EXIT_FAILURE); + + fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)); + if (!fcba) + exit(EXIT_FAILURE); + + read_freq = (fcba->flcomp >> 17) & 7; + + switch (read_freq) { + case SPI_FREQUENCY_20MHZ: + ifd_version = IFD_VERSION_1; + break; + case SPI_FREQUENCY_17MHZ: + ifd_version = IFD_VERSION_2; + break; + default: + fprintf(stderr, "Unknown descriptor version: %d\n", + read_freq); + exit(EXIT_FAILURE); + } +} + static region_t get_region(frba_t *frba, int region_type) { region_t region; @@ -89,8 +125,24 @@ static region_t get_region(frba_t *frba, int region_type) region.base = (frba->flreg4 & 0x00000fff) << 12; region.limit = ((frba->flreg4 & 0x0fff0000) >> 4) | 0xfff; break; + case 5: + region.base = (frba->flreg5 & 0x00000fff) << 12; + region.limit = ((frba->flreg5 & 0x0fff0000) >> 4) | 0xfff; + break; + case 6: + region.base = (frba->flreg6 & 0x00000fff) << 12; + region.limit = ((frba->flreg6 & 0x0fff0000) >> 4) | 0xfff; + break; + case 7: + region.base = (frba->flreg7 & 0x00000fff) << 12; + region.limit = ((frba->flreg7 & 0x0fff0000) >> 4) | 0xfff; + break; + case 8: + region.base = (frba->flreg8 & 0x00000fff) << 12; + region.limit = ((frba->flreg8 & 0x0fff0000) >> 4) | 0xfff; + break; default: - fprintf(stderr, "Invalid region type.\n"); + fprintf(stderr, "Invalid region type %d.\n", region_type); exit (EXIT_FAILURE); } @@ -132,7 +184,7 @@ static void set_region(frba_t *frba, int region_type, region_t region) static const char *region_name(int region_type) { - if (region_type < 0 || region_type >= NUM_REGIONS) { + if (region_type < 0 || region_type >= MAX_REGIONS) { fprintf(stderr, "Invalid region type.\n"); exit (EXIT_FAILURE); } @@ -142,7 +194,7 @@ static const char *region_name(int region_type) static const char *region_name_short(int region_type) { - if (region_type < 0 || region_type >= NUM_REGIONS) { + if (region_type < 0 || region_type >= MAX_REGIONS) { fprintf(stderr, "Invalid region type.\n"); exit (EXIT_FAILURE); } @@ -154,7 +206,7 @@ static int region_num(const char *name) { int i; - for (i = 0; i < NUM_REGIONS; i++) { + for (i = 0; i < MAX_REGIONS; i++) { if (strcasecmp(name, region_names[i].pretty) == 0) return i; if (strcasecmp(name, region_names[i].terse) == 0) @@ -166,16 +218,20 @@ static int region_num(const char *name) static const char *region_filename(int region_type) { - static const char *region_filenames[NUM_REGIONS] = { + static const char *region_filenames[MAX_REGIONS] = { "flashregion_0_flashdescriptor.bin", "flashregion_1_bios.bin", "flashregion_2_intel_me.bin", "flashregion_3_gbe.bin", - "flashregion_4_platform_data.bin" + "flashregion_4_platform_data.bin", + "flashregion_5_reserved.bin", + "flashregion_6_reserved.bin", + "flashregion_7_reserved.bin", + "flashregion_8_ec.bin", }; - if (region_type < 0 || region_type >= NUM_REGIONS) { - fprintf(stderr, "Invalid region type.\n"); + if (region_type < 0 || region_type >= MAX_REGIONS) { + fprintf(stderr, "Invalid region type %d.\n", region_type); exit (EXIT_FAILURE); } @@ -210,6 +266,17 @@ static void dump_frba(frba_t * frba) dump_region(3, frba); printf("FLREG4: 0x%08x\n", frba->flreg4); dump_region(4, frba); + + if (ifd_version >= IFD_VERSION_2) { + printf("FLREG5: 0x%08x\n", frba->flreg5); + dump_region(5, frba); + printf("FLREG6: 0x%08x\n", frba->flreg6); + dump_region(6, frba); + printf("FLREG7: 0x%08x\n", frba->flreg7); + dump_region(7, frba); + printf("FLREG8: 0x%08x\n", frba->flreg8); + dump_region(8, frba); + } } static void dump_frba_layout(frba_t * frba, char *layout_fname) @@ -225,7 +292,7 @@ static void dump_frba_layout(frba_t * frba, char *layout_fname) exit(EXIT_FAILURE); } - for (i = 0; i < NUM_REGIONS; i++) { + for (i = 0; i < MAX_REGIONS; i++) { dump_region_layout(buf, bufsize, i, frba); if (write(layout_fd, buf, strlen(buf)) < 0) { perror("Could not write to file"); @@ -245,8 +312,21 @@ static void decode_spi_frequency(unsigned int freq) case SPI_FREQUENCY_33MHZ: printf("33MHz"); break; - case SPI_FREQUENCY_50MHZ: - printf("50MHz"); + case SPI_FREQUENCY_48MHZ: + printf("48MHz"); + break; + case SPI_FREQUENCY_50MHZ_30MHZ: + switch (ifd_version) { + case IFD_VERSION_1: + printf("50MHz"); + break; + case IFD_VERSION_2: + printf("30MHz"); + break; + } + break; + case SPI_FREQUENCY_17MHZ: + printf("17MHz"); break; default: printf("unknown<%x>MHz", freq); @@ -274,6 +354,15 @@ static void decode_component_density(unsigned int density) case COMPONENT_DENSITY_16MB: printf("16MB"); break; + case COMPONENT_DENSITY_32MB: + printf("32MB"); + break; + case COMPONENT_DENSITY_64MB: + printf("64MB"); + break; + case COMPONENT_DENSITY_UNUSED: + printf("UNUSED"); + break; default: printf("unknown<%x>MB", density); } @@ -295,10 +384,22 @@ static void dump_fcba(fcba_t * fcba) (fcba->flcomp & (1 << 20))?"":"not "); printf("\n Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 17) & 7); - printf("\n Component 2 Density: "); - decode_component_density((fcba->flcomp >> 3) & 7); - printf("\n Component 1 Density: "); - decode_component_density(fcba->flcomp & 7); + + switch (ifd_version) { + case IFD_VERSION_1: + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 3) & 7); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 7); + break; + case IFD_VERSION_2: + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 4) & 0xf); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 0xf); + break; + } + printf("\n"); printf("FLILL 0x%08x\n", fcba->flill); printf(" Invalid Instruction 3: 0x%02x\n", @@ -339,6 +440,9 @@ static void dump_fpsba(fpsba_t * fpsba) static void decode_flmstr(uint32_t flmstr) { + if (ifd_version >= IFD_VERSION_2) + printf(" EC Region Write Access: %s\n", + (flmstr & (1 << 29)) ? "enabled" : "disabled"); printf(" Platform Data Region Write Access: %s\n", (flmstr & (1 << 28)) ? "enabled" : "disabled"); printf(" GbE Region Write Access: %s\n", @@ -350,6 +454,9 @@ static void decode_flmstr(uint32_t flmstr) printf(" Flash Descriptor Write Access: %s\n", (flmstr & (1 << 24)) ? "enabled" : "disabled"); + if (ifd_version >= IFD_VERSION_2) + printf(" EC Region Read Access: %s\n", + (flmstr & (1 << 21)) ? "enabled" : "disabled"); printf(" Platform Data Region Read Access: %s\n", (flmstr & (1 << 20)) ? "enabled" : "disabled"); printf(" GbE Region Read Access: %s\n", @@ -374,6 +481,10 @@ static void dump_fmba(fmba_t * fmba) decode_flmstr(fmba->flmstr2); printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); decode_flmstr(fmba->flmstr3); + if (ifd_version >= IFD_VERSION_2) { + printf("FLMSTR5: 0x%08x (EC)\n", fmba->flmstr5); + decode_flmstr(fmba->flmstr5); + } } static void dump_fmsba(fmsba_t * fmsba) @@ -528,6 +639,7 @@ static void dump_layout(char *image, int size, char *layout_fname) static void write_regions(char *image, int size) { int i; + int max_regions = MAX_REGIONS; fdbar_t *fdb = find_fd(image, size); if (!fdb) @@ -536,7 +648,11 @@ static void write_regions(char *image, int size) frba_t *frba = (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4)); - for (i = 0; i < NUM_REGIONS; i++) { + /* Older descriptor images have fewer regions */ + if (ifd_version < IFD_VERSION_2) + max_regions = MAX_REGIONS_OLD; + + for (i = 0; i < max_regions; i++) { region_t region = get_region(frba, i); dump_region(i, frba); if (region.size > 0) { @@ -601,9 +717,19 @@ static void set_em100_mode(char *filename, char *image, int size) { fdbar_t *fdb = find_fd(image, size); fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)); + int freq; + + switch (ifd_version) { + case IFD_VERSION_1: + freq = SPI_FREQUENCY_20MHZ; + break; + case IFD_VERSION_2: + freq = SPI_FREQUENCY_17MHZ; + break; + } fcba->flcomp &= ~(1 << 30); - set_spi_frequency(filename, image, size, SPI_FREQUENCY_20MHZ); + set_spi_frequency(filename, image, size, freq); } static void lock_descriptor(char *filename, char *image, int size) @@ -736,8 +862,8 @@ void new_layout(char *filename, char *image, int size, char *layout_fname) char layout_region_name[256]; int i, j; int region_number; - region_t current_regions[NUM_REGIONS]; - region_t new_regions[NUM_REGIONS]; + region_t current_regions[MAX_REGIONS]; + region_t new_regions[MAX_REGIONS]; int new_extent = 0; char *new_image; @@ -749,7 +875,7 @@ void new_layout(char *filename, char *image, int size, char *layout_fname) frba_t *frba = (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4)); - for (i = 0; i < NUM_REGIONS; i++) { + for (i = 0; i < MAX_REGIONS; i++) { current_regions[i] = get_region(frba, i); new_regions[i] = get_region(frba, i); } @@ -793,7 +919,7 @@ void new_layout(char *filename, char *image, int size, char *layout_fname) fclose(romlayout); /* check new layout */ - for (i = 0; i < NUM_REGIONS; i++) { + for (i = 0; i < MAX_REGIONS; i++) { if (new_regions[i].size == 0) continue; @@ -804,7 +930,7 @@ void new_layout(char *filename, char *image, int size, char *layout_fname) printf(" This may result in an unusable image.\n"); } - for (j = i + 1; j < NUM_REGIONS; j++) { + for (j = i + 1; j < MAX_REGIONS; j++) { if (regions_collide(new_regions[i], new_regions[j])) { fprintf(stderr, "Regions would overlap.\n"); exit(EXIT_FAILURE); @@ -826,7 +952,7 @@ void new_layout(char *filename, char *image, int size, char *layout_fname) /* copy regions to a new image */ new_image = malloc(new_extent); memset(new_image, 0xff, new_extent); - for (i = 0; i < NUM_REGIONS; i++) { + for (i = 0; i < MAX_REGIONS; i++) { int copy_size = new_regions[i].size; int offset_current = 0, offset_new = 0; region_t current = current_regions[i]; @@ -864,7 +990,7 @@ void new_layout(char *filename, char *image, int size, char *layout_fname) exit(EXIT_FAILURE); frba = (frba_t *) (new_image + (((fdb->flmap0 >> 16) & 0xff) << 4)); - for (i = 1; i < NUM_REGIONS; i++) { + for (i = 1; i < MAX_REGIONS; i++) { set_region(frba, i, new_regions[i]); } @@ -892,18 +1018,18 @@ static void print_usage(const char *name) { printf("usage: %s [-vhdix?] <filename>\n", name); printf("\n" - " -d | --dump: dump intel firmware descriptor\n" - " -f | --layout <filename> dump regions into a flashrom layout file\n" - " -x | --extract: extract intel fd modules\n" - " -i | --inject <region>:<module> inject file <module> into region <region>\n" - " -n | --newlayout <filename> update regions using a flashrom layout file\n" - " -s | --spifreq <20|33|50> set the SPI frequency\n" - " -e | --em100 set SPI frequency to 20MHz and disable\n" - " Dual Output Fast Read Support\n" - " -l | --lock Lock firmware descriptor and ME region\n" - " -u | --unlock Unlock firmware descriptor and ME region\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" + " -d | --dump: dump intel firmware descriptor\n" + " -f | --layout <filename> dump regions into a flashrom layout file\n" + " -x | --extract: extract intel fd modules\n" + " -i | --inject <region>:<module> inject file <module> into region <region>\n" + " -n | --newlayout <filename> update regions using a flashrom layout file\n" + " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" + " -l | --lock Lock firmware descriptor and ME region\n" + " -u | --unlock Unlock firmware descriptor and ME region\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" "\n"); } @@ -973,6 +1099,8 @@ int main(int argc, char *argv[]) region_type = 3; else if (!strcasecmp("Platform", region_type_string)) region_type = 4; + else if (!strcasecmp("EC", region_type_string)) + region_type = 8; if (region_type == -1) { fprintf(stderr, "No such region type: '%s'\n\n", region_type_string); @@ -994,14 +1122,23 @@ int main(int argc, char *argv[]) // Parse the requested SPI frequency inputfreq = strtol(optarg, NULL, 0); switch (inputfreq) { + case 17: + spifreq = SPI_FREQUENCY_17MHZ; + break; case 20: spifreq = SPI_FREQUENCY_20MHZ; break; + case 30: + spifreq = SPI_FREQUENCY_50MHZ_30MHZ; + break; case 33: spifreq = SPI_FREQUENCY_33MHZ; break; + case 48: + spifreq = SPI_FREQUENCY_48MHZ; + break; case 50: - spifreq = SPI_FREQUENCY_50MHZ; + spifreq = SPI_FREQUENCY_50MHZ_30MHZ; break; default: fprintf(stderr, "Invalid SPI Frequency: %d\n", @@ -1091,6 +1228,8 @@ int main(int argc, char *argv[]) close(bios_fd); + check_ifd_version(image, size); + if (mode_dump) dump_fd(image, size); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index b91c02d..8b13283 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -18,14 +18,21 @@ */ #include <stdint.h> -#define IFDTOOL_VERSION "1.1" +#define IFDTOOL_VERSION "1.2" + +enum ifd_version { + IFD_VERSION_1, + IFD_VERSION_2, +}; #define LAYOUT_LINELEN 80 enum spi_frequency { SPI_FREQUENCY_20MHZ = 0, SPI_FREQUENCY_33MHZ = 1, - SPI_FREQUENCY_50MHZ = 4, + SPI_FREQUENCY_48MHZ = 2, + SPI_FREQUENCY_50MHZ_30MHZ = 4, + SPI_FREQUENCY_17MHZ = 6, }; enum component_density { @@ -35,6 +42,9 @@ enum component_density { COMPONENT_DENSITY_4MB = 3, COMPONENT_DENSITY_8MB = 4, COMPONENT_DENSITY_16MB = 5, + COMPONENT_DENSITY_32MB = 6, + COMPONENT_DENSITY_64MB = 7, + COMPONENT_DENSITY_UNUSED = 0xf }; // flash descriptor @@ -48,12 +58,18 @@ typedef struct { } __attribute__((packed)) fdbar_t; // regions +#define MAX_REGIONS 9 +#define MAX_REGIONS_OLD 5 typedef struct { uint32_t flreg0; uint32_t flreg1; uint32_t flreg2; uint32_t flreg3; uint32_t flreg4; + uint32_t flreg5; + uint32_t flreg6; + uint32_t flreg7; + uint32_t flreg8; } __attribute__((packed)) frba_t; // component section @@ -90,6 +106,8 @@ typedef struct { uint32_t flmstr1; uint32_t flmstr2; uint32_t flmstr3; + uint32_t flmstr4; + uint32_t flmstr5; } __attribute__((packed)) fmba_t; // processor strap

1 0

Patch merged into coreboot/master: glados: make EC_SCI_L work
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 3d7020e0c48dcf5a61e68c284759c108907addaf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 9 14:45:02 2015 -0500 glados: make EC_SCI_L work In order for the EC_SCI_L to work the GPE0 route needs to be set along w/ the GPE event for the EC. As the GPE0 route is dynamic the EC_SCI_GPI needs to be set along with the route so everything lines up. In this case, the GPE0 route is set to the defaults such that GPP_C, GPP_D, and GPP_E are routed to GPE0 block 0, 1, and 2, respectively. This works out for glados because the EC_SCI_L is connected to GPP_E16. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts is incrementing as well as /sys/firmware/acpi/interrupts/gpe50. Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292011 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11210 Tested-by: build bot (Jenkins) See http://review.coreboot.org/11210 for details. -gerrit

1 0

Patch set updated for coreboot: glados: make EC_SCI_L work
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11210 -gerrit commit a94359ced76201886d570384d3a202cf2221f190 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 9 14:45:02 2015 -0500 glados: make EC_SCI_L work In order for the EC_SCI_L to work the GPE0 route needs to be set along w/ the GPE event for the EC. As the GPE0 route is dynamic the EC_SCI_GPI needs to be set along with the route so everything lines up. In this case, the GPE0 route is set to the defaults such that GPP_C, GPP_D, and GPP_E are routed to GPE0 block 0, 1, and 2, respectively. This works out for glados because the EC_SCI_L is connected to GPP_E16. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts is incrementing as well as /sys/firmware/acpi/interrupts/gpe50. Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292011 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/devicetree.cb | 8 ++++++++ src/mainboard/google/glados/ec.h | 6 ++++-- src/mainboard/google/glados/gpio.h | 2 +- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2e1cae7..9bb065d 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -49,6 +49,14 @@ chip soc/intel/skylake register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + # Embedded Controller host command window register "gen1_dec" = "0x00fc0801" diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h index f42e4c7..d43b57c 100644 --- a/src/mainboard/google/glados/ec.h +++ b/src/mainboard/google/glados/ec.h @@ -24,8 +24,10 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/gpio.h> -/* GPP_E16 is EC_SCI_L */ -#define EC_SCI_GPI 16 /* TODO: Update this */ +/* GPP_E16 is EC_SCI_L, however the EC_SCI_GPI needs to be a bit + * number relative to the GPE0 block. GPP_E is routed as the dword 2 + * in the GPE0 block. Therefore, 16 + 2 * 32 = 80. */ +#define EC_SCI_GPI 80 #define EC_SMI_GPI GPP_E15 #define MAINBOARD_EC_SCI_EVENTS \ diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index ebbee20..c7cd5ae 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), +/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ /* DDPB_CTRLDATA */ /* GPP_E19 */

1 0

Patch merged into coreboot/master: glados: make EC_SMI_L functional
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 50ed38feba58ff59248015285bfdbe1c37cc4136 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Aug 8 01:25:21 2015 -0500 glados: make EC_SMI_L functional Set the EC_SMI_GPI define to be GPP_E15 and route that GPIO for SMI generation. Also, the mainboard_smi_gpi_handler() was introduced on skylake in order to process any GPI that could generate an SMI. Switch to this handler so one can process the appropriate events. BUG=chrome-os-partner:43778 BRANCH=None TEST=Used 'lidclose' on EC command line during depthcharge to confirm EC_SMI_L generates SMI and shutdown happens. Original-Change-Id: Ia365b86161670a809e3fa99dde38fccc612d5e77 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291934 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ic16ea8e8d6ff564977ed2081d2353c82af71adea Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11209 for details. -gerrit

1 0

Patch merged into coreboot/master: skylake: provide clarification for FADT gpe0_blk_len
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 71e0ac858e84fc3882fd1f836b95e56df9c933f4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 7 23:00:22 2015 -0500 skylake: provide clarification for FADT gpe0_blk_len Instead of using a hard-coded value leverage the existing definitions to perform GPE0 block length calculations. There are 4 pairs of 32-bit status/enable registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291932 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11205 for details. -gerrit

1 0

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coreboot-gerrit August 2015