coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel raminit: fix random raminit failures
by Patrick Rudolph 18 Aug '15

18 Aug '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11248 -gerrit commit 2d2d47228926dfcbbcd6e8b0f3ed178f7102d968 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Aug 17 19:24:12 2015 +0200 intel raminit: fix random raminit failures Issue observed: Intel raminit works in about 50% of all test-cases on lenovo x220. Problem solution: Prefer a smaller valid value over the measured one for initial timB timings. Final testing result: Tests on x220 shows that the issue was resolved. The test system booted successfully ten times in a row. Tests on Gigabyte GA-B75M-D3H revealed no regressions. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ" Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 286493b..90c34cf 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2266,7 +2266,17 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) } FOR_ALL_LANES { struct run rn = get_longest_zero_run(statistics[lane], 128); - ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + if (rn.start < rn.middle) { + ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + } else { + /* In this case statistics[lane][7f] and statistics[lane][0] are + * both zero. + * Prefer a smaller value over rn.start to prevent failures in + * the following write tests. + */ + ctrl->timings[channel][slotrank].lanes[lane].timB = 0; + } + if (rn.all) die("timB discovery failed"); printram("Bval: %d, %d, %d, %x\n", channel, slotrank,

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Patch set updated for coreboot: intel raminit: add sanity check
by Patrick Rudolph 18 Aug '15

18 Aug '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11247 -gerrit commit 2eeb12116803714b67cf777278b7e64dc852fa94 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Aug 16 17:06:30 2015 +0200 intel raminit: add sanity check Make sure edge write test results are sane. Check rn.all to make sure rn.start and rn.end are valid. Most likely the following test is going to fail on the same rank anyway. Change-Id: Ifa601406e6c74ceb8d70063be5ce1bf6bc512c18 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9df102a..286493b 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -3129,6 +3129,8 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, max(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = min(rn.end - ctrl->edge_offset[i], upper[lane]); + if (rn.all || lower[lane] > upper[lane]) + die("edge write discovery failed"); edges[lane] = (lower[lane] + upper[lane]) / 2; }

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New patch to review for coreboot: intel raminit: fix random raminit failures
by Patrick Rudolph 18 Aug '15

18 Aug '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11248 -gerrit commit bdbf1fe4cbd4ce4f9ea1e9addb649365edcde970 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Aug 17 19:24:12 2015 +0200 intel raminit: fix random raminit failures Issue observed: Intel raminit works in about 50% of all test-cases on lenovo x220. Problem solution: Prefer a smaller valid value over the measured one for initial timB timings. Final testing result: Tests on x220 shows that the issue was resolved. The test system booted successfully ten times in a row. Tests on Gigabyte GA-B75M-D3H revealed no regressions. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ" Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit_native.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 286493b..90c34cf 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -2266,7 +2266,17 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) } FOR_ALL_LANES { struct run rn = get_longest_zero_run(statistics[lane], 128); - ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + if (rn.start < rn.middle) { + ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; + } else { + /* In this case statistics[lane][7f] and statistics[lane][0] are + * both zero. + * Prefer a smaller value over rn.start to prevent failures in + * the following write tests. + */ + ctrl->timings[channel][slotrank].lanes[lane].timB = 0; + } + if (rn.all) die("timB discovery failed"); printram("Bval: %d, %d, %d, %x\n", channel, slotrank,

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New patch to review for coreboot: intel raminit: add sanity check
by Patrick Rudolph 18 Aug '15

18 Aug '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11247 -gerrit commit 2a3cf281bbd868fac3411ee6b143f713d0ffb3c9 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Aug 16 17:06:30 2015 +0200 intel raminit: add sanity check Make sure edge write test results are sane. Most likely the following test is going to fail on the same rank anyway. Change-Id: Ifa601406e6c74ceb8d70063be5ce1bf6bc512c18 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- 3rdparty/blobs | 2 +- src/northbridge/intel/sandybridge/raminit_native.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index b4ade40..34b0926 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit b4ade4096486fd1abcde468de8719e45a721aee7 +Subproject commit 34b09265063c19ea5d61bd5a2f057b47b5aa2232 diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9df102a..286493b 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -3129,6 +3129,8 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, max(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = min(rn.end - ctrl->edge_offset[i], upper[lane]); + if (rn.all || lower[lane] > upper[lane]) + die("edge write discovery failed"); edges[lane] = (lower[lane] + upper[lane]) / 2; }

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Patch merged into coreboot/master: Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUN
by gerrit＠coreboot.org 17 Aug '15

17 Aug '15

the following patch was just integrated into master: commit b95fc308af04d06a384cac2972a23dc5e6dbefaf Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 17 11:29:01 2015 -0600 Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUN Broadwell and Skylake chipsets, along with a few mainboards were selecting ALWAYS_LOAD_OPROM without making sure that the dependency for that symbol was met as well. Looking at the dependencies for VGA_RUN_ROM, we see: PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT Since ARCH_X86 selects PCI, that's always met here. Since Broadwell and Skylake don't have native VGA init yet, that's not needed. - Make sure that VGA_RUN_ROM is selected as well. - Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and VGA_RUN_ROM symbols where they're selected. Fixes Kconfig warning for these boards and chipsets: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects ALWAYS_LOAD_OPROM which has unmet direct dependencies (VGA_ROM_RUN) Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/11246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11246 for details. -gerrit

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New patch to review for coreboot: Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUN
by Martin Roth 17 Aug '15

17 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11246 -gerrit commit cf2245f2843a1eb5fe10ab7af25d595d294cb59f Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 17 11:29:01 2015 -0600 Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUN Broadwell and Skylake chipsets, along with a few mainboards were selecting ALWAYS_LOAD_OPROM without making sure that the dependency for that symbol was met as well. Looking at the dependencies for VGA_RUN_ROM, we see: PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT Since ARCH_X86 selects PCI, that's always met here. Since Broadwell and Skylake don't have native VGA init yet, that's not needed. - Make sure that VGA_RUN_ROM is selected as well. - Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and VGA_RUN_ROM symbols where they're selected. Fixes Kconfig warning for these boards and chipsets: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects ALWAYS_LOAD_OPROM which has unmet direct dependencies (VGA_ROM_RUN) Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/cyan/Kconfig | 3 ++- src/mainboard/google/rambi/Kconfig | 3 ++- src/mainboard/intel/strago/Kconfig | 3 ++- src/soc/intel/broadwell/Kconfig | 3 ++- src/soc/intel/skylake/Kconfig | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 988002c..91f7587 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -2,7 +2,8 @@ if BOARD_GOOGLE_CYAN config BOARD_SPECIFIC_OPTIONS def_bool y - select ALWAYS_LOAD_OPROM + select VGA_ROM_RUN if !PAYLOAD_SEABIOS + select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 6fb19d4..45c3ece 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -13,7 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select ALWAYS_LOAD_OPROM + select VGA_ROM_RUN if !PAYLOAD_SEABIOS + select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select CHROMEOS_VBNV_CMOS select LID_SWITCH diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index a7932e1..c19761a 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -2,7 +2,8 @@ if BOARD_INTEL_STRAGO config BOARD_SPECIFIC_OPTIONS def_bool y - select ALWAYS_LOAD_OPROM + select VGA_ROM_RUN if !PAYLOAD_SEABIOS + select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5da8a33..5853118 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,7 +11,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select ALWAYS_LOAD_OPROM + select VGA_ROM_RUN if !PAYLOAD_SEABIOS + select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_BIN select CACHE_MRC_SETTINGS diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6c64cd9..b6d55fd 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -11,7 +11,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select ALWAYS_LOAD_OPROM + select VGA_ROM_RUN if !PAYLOAD_SEABIOS + select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

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Patch merged into coreboot/master: soc/intel/skylake/Kconfig: Fix recursive Kconfig dependency
by gerrit＠coreboot.org 17 Aug '15

17 Aug '15

the following patch was just integrated into master: commit 1afcb23cd7d358153392be1292f17d54f44c0a6d Author: Martin Roth <martinroth(a)google.com> Date: Sat Aug 15 17:36:15 2015 -0600 soc/intel/skylake/Kconfig: Fix recursive Kconfig dependency Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based on this question. The dependency was causing multiple warnings on every platform tested. src/console/Kconfig:21:error: recursive dependency detected! src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on DRIVERS_UART_8250MEM src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by UART_DEBUG src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on CONSOLE_SERIAL Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/11243 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11243 for details. -gerrit

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Patch set updated for coreboot: northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIO
by Timothy Pearson 17 Aug '15

17 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11240 -gerrit commit 5b2569a366fd217353104e2f749cdd081b778c92 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 16:31:14 2015 -0500 northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIO Commit 27baa32 (cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled) deactivated TSeg SMRAM, which had the side effect of routing legacy VGA memory access to DRAM. Restore the correct MMIO mapping via the MMIO configuration registers. TEST: Booted KGPE-D16 with nVidia 7300LE card and verified proper VGA functionality. Change-Id: Ie4b7c0b2d6f9a02af9a022565fe514119513190a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f6f2641..6d91cbd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -492,6 +492,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) { struct bus *link; + struct resource *res; /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ @@ -516,6 +517,18 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); set_vga_enable_reg(nodeid, link->link_num); + + /* Redirect VGA memory access to MMIO + * This signals the Family 10h resource parser + * to add a new MMIO mapping to the Range 11 + * MMIO control registers (starting at F1x1B8), + * and also reserves the resource in the E820 map. + */ + res = new_resource(dev, IOINDEX(0x1000 + 0x1b8, link->link_num)); + res->base = 0xa0000; + res->size = 0x20000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + amdfam10_set_resource(dev, res, nodeid); } static void amdfam10_set_resources(device_t dev)

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Patch set updated for coreboot: soc/intel/skylake/Kconfig: Fix recursive Kconfig dependency
by Martin Roth 17 Aug '15

17 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11243 -gerrit commit f473e6f39bb5ea6497fbbe05960d5907eeeb72b8 Author: Martin Roth <martinroth(a)google.com> Date: Sat Aug 15 17:36:15 2015 -0600 soc/intel/skylake/Kconfig: Fix recursive Kconfig dependency Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based on this question. The dependency was causing multiple warnings on every platform tested. src/console/Kconfig:21:error: recursive dependency detected! src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on DRIVERS_UART_8250MEM src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by UART_DEBUG src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on CONSOLE_SERIAL Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/skylake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6c64cd9..9d920d8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -195,8 +195,8 @@ config VGA_BIOS_ID config UART_DEBUG bool "Enable UART debug port." - default y if CONSOLE_SERIAL default n + select CONSOLE_SERIAL select DRIVERS_UART select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32

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New patch to review for coreboot: inteltool: Add Intel 4-Series chipset detection
by Damien Zammit 17 Aug '15

17 Aug '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11245 -gerrit commit 46e788a88ec9a9fadce3d6978829e05585d108b7 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Aug 17 21:04:41 2015 +1000 inteltool: Add Intel 4-Series chipset detection Previously, X4X was incorrectly named because it provides support for SKUs within XX4X range. This has been renamed. This patch provides support for all X4X SKUs according to datasheet Intel 4 Series Chipset Family Specification Update, namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions). Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- util/inteltool/inteltool.c | 7 ++++++- util/inteltool/inteltool.h | 8 +++++++- util/inteltool/memory.c | 7 ++++++- util/inteltool/pcie.c | 21 ++++++++++++++++++--- 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 06dd20f..a3c7e22 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -61,7 +61,12 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82XX4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q45, "Q45/Q43" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G45, "G45/G43/P45/P43" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G41, "G41" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43, "B43(Base)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43_2, "B43(Soft)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 10b69a9..cff0fd9 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -132,7 +132,13 @@ #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 #define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 -#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82Q45 0x2e10 +#define PCI_DEVICE_ID_INTEL_82G45 0x2e20 +#define PCI_DEVICE_ID_INTEL_82G41 0x2e30 +#define PCI_DEVICE_ID_INTEL_82B43 0x2e40 +#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90 + #define PCI_DEVICE_ID_INTEL_82X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 6c6a67d..313de5a 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -194,7 +194,12 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82830M: printf("This northbridge does not have MCHBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index a3d8270..ebe0877 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -202,7 +202,12 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: @@ -277,7 +282,12 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; @@ -406,7 +416,12 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:

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coreboot-gerrit August 2015