coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch merged into coreboot/master: libpayload: usb: dwc2: fix usb plug/unplug bug
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 4938426783423889717e67f6be85e360a5f02d95 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Tue Aug 11 17:58:14 2015 +0800 libpayload: usb: dwc2: fix usb plug/unplug bug Check device connect status while waiting for usb transfer complete Avoid coreboot get stuck when usb device unplugged BUG=chrome-os-partner:35525 TEST=None BRANCH=None Original-Change-Id: Id103501aa0d8b31b0b81bef773679c0fad79f689 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292630 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292966 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Change-Id: I49396b74131dbfda505d9d3de5adbdc87eb92ce1 Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Reviewed-on: http://review.coreboot.org/11236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11236 for details. -gerrit

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Patch merged into coreboot/master: Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupport
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit f1acb9b69d9fca1b5396e76f5d19781dce46d01b Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Thu Aug 13 15:21:37 2015 -0700 Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupport (1) Wifi is connected on RP1 which is 1c.0 , so enabling 1c.0 and disabling 1d.0 (2) kepler is on RP5 which is 1c.4, so enabling it (3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can get enabled. BRANCH=None BUG=chrome-os-partner:43738 TEST=Built and boot for Kunimitsu. checked all PCIe powersaving states (LTR, L1, L1S) are enabled Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293482 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: http://review.coreboot.org/11237 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11237 for details. -gerrit

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Patch merged into coreboot/master: skylake: correct IO-APIC redirection entry count
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 416bf45480153e7a7d367d7b5da093786f4a433f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 13 09:05:22 2015 -0500 skylake: correct IO-APIC redirection entry count The skylake IO-APIC supports up to 120 redirection entries. In practice it seems FSP has already written to this write-once register. However, it doesn't hurt to actually be correct within the source. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293251 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11235 for details. -gerrit

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Patch merged into coreboot/master: glados: use macros for magic numbers in ASL
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit a537f9a2ecfd2753f06a5707af965658e21dd7e1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 13 03:06:02 2015 -0500 glados: use macros for magic numbers in ASL The skylake SoC code now has macros for the previously hard-code numbers for IRQs and GPEs. Switch over to using those as they bring a little more clarity. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ic8fcc59d680cdddec9dfbc3bf679731f6d786793 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293411 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I594907005372100a3c9d17dda9d17769844ad272 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11234 for details. -gerrit

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Patch merged into coreboot/master: skylake: add gpe.h for ASL generation
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit d3a36b8a4611c3fbafc73c4d178315ccf7f9c7f7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 13 03:00:54 2015 -0500 skylake: add gpe.h for ASL generation One thing that is brittle is lining up GPE0 bits in ASL and with a board's design proper. This results in open calculated magic numbers. To help alleviate this provide just #defines that C preprocessor can use before handing the source off to the ASL compiler. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Everything's intact. Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293410 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11233 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11233 for details. -gerrit

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Patch merged into coreboot/master: Kunimitsu: Enable root ports and clkreqs
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit e56d734816490d4157f94b38331a4ce10fb38366 Author: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Date: Wed Jul 22 17:27:56 2015 +0530 Kunimitsu: Enable root ports and clkreqs This patch enables the root ports and configures the clock req numbers as per the design On kunimitsu FAB3 board with D0 MCP Root port 1 --> Wifi card --> clkreq 1 Root port 4 --> Kepler VP8/VP9--> clkreq 2 BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for Kunimitsu and Boot Kunimitsu board with D0 MCP Original-Change-Id: I4e110d2d07efbfa7a306852301cd1cd89027b2ba Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290051 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Change-Id: I6d66c78496ac3f43e07d96feefed35cf50da6aa1 Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Reviewed-on: http://review.coreboot.org/11232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11232 for details. -gerrit

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Patch merged into coreboot/master: Kunimitsu: Update Mainboard ASL for Kunimitsu FAB3 with D0 MCP
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 8e15bbc6656a7ba0e9eade331b996a8486fa3007 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Tue Jul 28 23:30:45 2015 +0530 Kunimitsu: Update Mainboard ASL for Kunimitsu FAB3 with D0 MCP This patch updates the mainboard.asl file to support Kunimitsu FAB3 board which is based on SKL D0 MCP. BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for kunimitsu; booted on kunimitsu FAB3 with D0 MCP Original-Change-Id: I31a315740d49125591591b20c296babe49004166 Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290050 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I81c22e407d1b3d420744eaf1d3f7ff4e8e749bcb Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/11231 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11231 for details. -gerrit

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Patch merged into coreboot/master: Kunimitsu: Update Gpio table for kunimitsu FAB3 variant
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit fac5eb0c9348b9743b7c16c22e066d7fd395105f Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Wed Jun 24 21:56:57 2015 +0530 Kunimitsu: Update Gpio table for kunimitsu FAB3 variant This patch updates the GPIO table to support Kunimitsu FAB3 variant, based on SKL D0 MCP. BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for kunimitsu; booted on kunimitsu with D0 MCP. Original-Change-Id: I2343187a919f6d29161069135d97484191198056 Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/289939 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I47302062788a90550fd38cb113e418b21d3f756c Signed-off-by: Pravin Angolkar <pravin.k.angolkar(a)intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/11230 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11230 for details. -gerrit

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Patch merged into coreboot/master: ifdtool: handle region masks correctly
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 0a31e5975ec04e70f5e3a284a29e121b94088555 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 12 11:44:02 2015 -0500 ifdtool: handle region masks correctly The get_region() function was using fixed masks for the base and limit. However, newer descriptors (on skylake, e.g.) use a 15-bit mask -- not a 12-bit one. Choose the right mask based on ifd_version. BUG=chrome-os-partner:43461 BRANCH=None TEST=Built glados bootimage. Original-Change-Id: Ibcbfd649a561d36b17ea2cc8fbeb30ffdbbb2c96 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293250 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I7f2ef9fb8e5b6c7114225fecc2798668d6507ac3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11229 for details. -gerrit

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Patch merged into coreboot/master: ifdtool: Update to support Skylake+ descriptor format
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 1f7fd720c81755144423f2d4062c39cc651adc0a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 22 11:14:48 2015 -0700 ifdtool: Update to support Skylake+ descriptor format The descriptor format has changed with Skylake and some fields have moved or been expanded. This includes new SPI frequencies and chip densities, though unfortunately 30MHz in the new format conflicts with 50MHz in the old format... There are also new regions with a few reserved regions inserted before a new embedded controller region. Unfortunately there does not seem to be a documented version field so there does not seem to be an official way to determine if a specific descriptor is new or old. To work around this ifdtool checks the hardcoded "SPI Read Frequency" to see if it set for 20MHz (old descriptor) or 17MHz (new descriptor). BUG=chrome-os-partner:40635 BUG=chrome-os-partner:43461 BRANCH=none TEST=run ifdtool on skylake and broadwell images Original-Change-Id: I0561b3c65fcb3e77c0a24be58b01db9b3a36e5a9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281001 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9a08c26432e13c4000afc50de9d8473e6f911805 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293240 Reviewed-on: http://review.coreboot.org/11228 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11228 for details. -gerrit

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coreboot-gerrit August 2015