coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: inteltool: Add Intel 4-Series chipset detection
by Damien Zammit 19 Aug '15

19 Aug '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11245 -gerrit commit 5608b6c5138f50061c129ca1e5cbe03b6e5bd496 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Aug 17 21:04:41 2015 +1000 inteltool: Add Intel 4-Series chipset detection Previously, X4X was incorrectly named because it provides support for SKUs within XX4X range. This is renamed. This patch provides support for all X4X SKUs according to datasheet Intel 4 Series Chipset Family Specification Update, namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions). Tested on Gigabyte GA-G41M-ES2L Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- util/inteltool/inteltool.c | 7 ++++++- util/inteltool/inteltool.h | 8 +++++++- util/inteltool/memory.c | 7 ++++++- util/inteltool/pcie.c | 21 ++++++++++++++++++--- 4 files changed, 37 insertions(+), 6 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 06dd20f..508b55a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -61,7 +61,12 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82XX4X, "GL40/GS40/GM45/GS45/PM45" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q45, "Q45/Q43" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G45, "G45/G43/P45/P43" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G41, "G41" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43, "B43 (Base)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82B43_2, "B43 (Soft)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 10b69a9..cff0fd9 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -132,7 +132,13 @@ #define PCI_DEVICE_ID_INTEL_82Q33 0x29d0 #define PCI_DEVICE_ID_INTEL_82X38 0x29e0 #define PCI_DEVICE_ID_INTEL_32X0 0x29f0 -#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82XX4X 0x2a40 +#define PCI_DEVICE_ID_INTEL_82Q45 0x2e10 +#define PCI_DEVICE_ID_INTEL_82G45 0x2e20 +#define PCI_DEVICE_ID_INTEL_82G41 0x2e30 +#define PCI_DEVICE_ID_INTEL_82B43 0x2e40 +#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90 + #define PCI_DEVICE_ID_INTEL_82X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 6c6a67d..313de5a 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -194,7 +194,12 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_82830M: printf("This northbridge does not have MCHBAR.\n"); return 1; - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index a3d8270..ebe0877 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -202,7 +202,12 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: @@ -277,7 +282,12 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; @@ -406,7 +416,12 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_82X38: case PCI_DEVICE_ID_INTEL_32X0: - case PCI_DEVICE_ID_INTEL_82X4X: + case PCI_DEVICE_ID_INTEL_82XX4X: + case PCI_DEVICE_ID_INTEL_82Q45: + case PCI_DEVICE_ID_INTEL_82G45: + case PCI_DEVICE_ID_INTEL_82G41: + case PCI_DEVICE_ID_INTEL_82B43: + case PCI_DEVICE_ID_INTEL_82B43_2: case PCI_DEVICE_ID_INTEL_ATOM_DXXX: case PCI_DEVICE_ID_INTEL_ATOM_NXXX: case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:

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Patch merged into coreboot/master: AMD ROMSIG: Only check location if ROMSIG is used
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit e0334e82960aa72c602686f1f8a840002bc3a73a Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 11 09:05:42 2015 -0600 AMD ROMSIG: Only check location if ROMSIG is used The location of the AMD ROMSIG binary was being checked and warnings were being printed even when the ROMSIG file wasn't being used. These false warnings are avoided by moving the warnings into the block where the CBFS file for the ROMSIG is generated. Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/11161 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11161 for details. -gerrit

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Patch set updated for coreboot: Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig
by Martin Roth 19 Aug '15

19 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11270 -gerrit commit 6a4c024d6e5b2bd14bfdd10762c6e71e61e07ced Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 10:41:54 2015 -0600 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/haswell/cache_as_ram.inc | 4 ---- src/cpu/intel/model_206ax/cache_as_ram.inc | 4 ---- src/cpu/intel/socket_rPGA988B/Kconfig | 4 ---- src/cpu/intel/socket_rPGA989/Kconfig | 4 ---- src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 4 ---- src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/broadwell/romstage/cache_as_ram.inc | 4 ---- 8 files changed, 26 deletions(-) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 0a070b2..0978bfb 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -151,7 +151,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -161,7 +160,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -219,7 +217,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -227,7 +224,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2d469ff..a3f1c64 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -146,7 +146,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -156,7 +155,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -211,7 +209,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -219,7 +216,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig index 471e522..753cfb3 100644 --- a/src/cpu/intel/socket_rPGA988B/Kconfig +++ b/src/cpu/intel/socket_rPGA988B/Kconfig @@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE -config CACHE_MRC_BIN - bool - default n - endif diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig index 83d29e7..1d1f64f 100644 --- a/src/cpu/intel/socket_rPGA989/Kconfig +++ b/src/cpu/intel/socket_rPGA989/Kconfig @@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE -config CACHE_MRC_BIN - bool - default n - endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 0a251b8..37dbd2b 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool - select CACHE_MRC_BIN select CPU_INTEL_HASWELL select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 4dede09..093224f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX @@ -27,7 +26,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX @@ -36,7 +34,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX @@ -44,7 +41,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5853118..524366c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select VGA_ROM_RUN if !PAYLOAD_SEABIOS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION - select CACHE_MRC_BIN select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 05d4889..3f1b12a 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -153,7 +153,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -163,7 +162,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -239,7 +237,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -247,7 +244,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33)

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New patch to review for coreboot: util/kconfig: add olddefconfig target
by Martin Roth 18 Aug '15

18 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11273 -gerrit commit f4bbfaae66d2267edf91cff03e61dbd57cd7f269 Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 14:30:27 2015 -0600 util/kconfig: add olddefconfig target There doesn't seem to have been an olddefconfig target in the coreboot version of the Kconfig makefile. It's listed in the .PHONY, but it doesn't seem like it's ever been there. This is useful for expanding a miniconfig saved with 'make savedefconfig'. Change-Id: I3798f8469135b58d32da68d4b0e434ab5351b501 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/kconfig/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile index ab74113..243f763 100644 --- a/util/kconfig/Makefile +++ b/util/kconfig/Makefile @@ -97,6 +97,9 @@ else $< --defconfig=$(KBUILD_DEFCONFIG) $(Kconfig) endif +olddefconfig: $(objk)/conf + $< --olddefconfig $(Kconfig) + %_defconfig: $(objk)/conf $< --defconfig=configs/$@ $(Kconfig)

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New patch to review for coreboot: ChromeOS: Fix Kconfig dependencies
by Martin Roth 18 Aug '15

18 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11272 -gerrit commit ebeee468d4dbef05778a2203bf2f9494e27dab6a Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 14:22:58 2015 -0600 ChromeOS: Fix Kconfig dependencies Add 'if CHROMEOS' dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/auron/Kconfig | 8 ++++---- src/mainboard/google/bolt/Kconfig | 6 +++--- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/cosmos/Kconfig | 2 +- src/mainboard/google/cyan/Kconfig | 6 +++--- src/mainboard/google/daisy/Kconfig | 2 +- src/mainboard/google/falco/Kconfig | 6 +++--- src/mainboard/google/foster/Kconfig | 2 +- src/mainboard/google/glados/Kconfig | 10 +++++----- src/mainboard/google/jecht/Kconfig | 6 +++--- src/mainboard/google/link/Kconfig | 4 ++-- src/mainboard/google/nyan/Kconfig | 4 ++-- src/mainboard/google/nyan_big/Kconfig | 4 ++-- src/mainboard/google/nyan_blaze/Kconfig | 4 ++-- src/mainboard/google/panther/Kconfig | 4 ++-- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/peach_pit/Kconfig | 2 +- src/mainboard/google/peppy/Kconfig | 6 +++--- src/mainboard/google/purin/Kconfig | 2 +- src/mainboard/google/rambi/Kconfig | 6 +++--- src/mainboard/google/rush/Kconfig | 4 ++-- src/mainboard/google/rush_ryu/Kconfig | 4 ++-- src/mainboard/google/samus/Kconfig | 12 ++++++------ src/mainboard/google/slippy/Kconfig | 6 +++--- src/mainboard/google/smaug/Kconfig | 4 ++-- src/mainboard/google/storm/Kconfig | 4 ++-- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/google/veyron_brain/Kconfig | 4 ++-- src/mainboard/google/veyron_danger/Kconfig | 4 ++-- src/mainboard/google/veyron_jerry/Kconfig | 4 ++-- src/mainboard/google/veyron_mickey/Kconfig | 4 ++-- src/mainboard/google/veyron_mighty/Kconfig | 4 ++-- src/mainboard/google/veyron_minnie/Kconfig | 4 ++-- src/mainboard/google/veyron_pinky/Kconfig | 4 ++-- src/mainboard/google/veyron_rialto/Kconfig | 4 ++-- src/mainboard/google/veyron_romy/Kconfig | 4 ++-- src/mainboard/google/veyron_shark/Kconfig | 4 ++-- src/mainboard/google/veyron_speedy/Kconfig | 4 ++-- src/mainboard/intel/baskingridge/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/intel/kunimitsu/Kconfig | 8 ++++---- src/mainboard/intel/sklrvp/Kconfig | 6 +++--- src/mainboard/intel/strago/Kconfig | 6 +++--- src/mainboard/intel/wtm2/Kconfig | 4 ++-- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 4 ++-- src/soc/broadcom/cygnus/Kconfig | 4 ++-- src/soc/marvell/bg4cd/Kconfig | 2 +- src/soc/nvidia/tegra210/Kconfig | 2 +- src/soc/qualcomm/ipq806x/Kconfig | 6 +++--- src/soc/rockchip/rk3288/Kconfig | 6 +++--- 51 files changed, 111 insertions(+), 111 deletions(-) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 3a4cb7e..518be1a 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -5,7 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -14,10 +14,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select CHROMEOS_RAMOOPS_DYNAMIC + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config VBOOT_RAMSTAGE_INDEX hex diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 2e37e25..1c4723f 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -18,8 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index b1a64ee..d992467 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig index a6c87b1..dae16a3 100644 --- a/src/mainboard/google/cosmos/Kconfig +++ b/src/mainboard/google/cosmos/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_2048 - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 91f7587..8f852ab 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -6,11 +6,11 @@ config BOARD_SPECIFIC_OPTIONS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select CHROMEOS - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select ENABLE_BUILTIN_COM1 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH select HAVE_ACPI_RESUME - select LID_SWITCH + select LID_SWITCH if CHROMEOS config DISPLAY_SPD_DATA bool "Display Memory Serial Presence Detect Data" diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index c69c390..6204ffb 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVER_TI_TPS65090 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index e029382..affb14a 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -21,8 +21,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index b8fe708..313bb04 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select SPI_FLASH select SOC_NVIDIA_TEGRA210 select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index c7df2a3..6220400 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -5,24 +5,24 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384 select CACHE_ROM select CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS + select CHROMEOS_VBNV_CMOS if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER - select LID_SWITCH + select LID_SWITCH if CHROMEOS select MAINBOARD_HAS_CHROMEOS select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE - select VBOOT_OPROM_MATTERS + select VBOOT_OPROM_MATTERS if CHROMEOS select VIRTUAL_DEV_SWITCH config IRQ_SLOT_COUNT diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 83b091d..3b9c7ae 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -13,10 +13,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select CHROMEOS_RAMOOPS_DYNAMIC + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select PHYSICAL_REC_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select PHYSICAL_REC_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index fd3390a..3d8347a 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -15,8 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_LPC_TPM select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index d771ca6..ab32e7e 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -25,14 +25,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select TEGRA124_MODEL_CD570M select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select VIRTUAL_DEV_SWITCH - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 55ded30..67c854e 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -26,14 +26,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ID_AUTO select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select TEGRA124_MODEL_CD570M select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select VIRTUAL_DEV_SWITCH - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 5316523..a19611b 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ID_AUTO select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select SOC_NVIDIA_TEGRA124 select TEGRA124_MODEL_CD570M select MAINBOARD_HAS_CHROMEOS @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B select VIRTUAL_DEV_SWITCH - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/panther/Kconfig b/src/mainboard/google/panther/Kconfig index 6fb6c5f..59fd316 100644 --- a/src/mainboard/google/panther/Kconfig +++ b/src/mainboard/google/panther/Kconfig @@ -17,8 +17,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select PHYSICAL_REC_SWITCH - select CHROMEOS_VBNV_CMOS + select PHYSICAL_REC_SWITCH if CHROMEOS + select CHROMEOS_VBNV_CMOS if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 9cf390a..6484dc3 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 3a94dec..23a5d06 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -28,7 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select DRIVER_PARADE_PS8625 - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index b507953..3594644 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -9,7 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -23,8 +23,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_DP select INTEL_DDI select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig index be6d050..2558a46 100644 --- a/src/mainboard/google/purin/Kconfig +++ b/src/mainboard/google/purin/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_2048 - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 45c3ece..27dc04c 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_BAYTRAIL select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select VIRTUAL_DEV_SWITCH select ENABLE_BUILTIN_COM1 select BOARD_ROMSIZE_KB_8192 @@ -15,8 +15,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select VGA_ROM_RUN if !PAYLOAD_SEABIOS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index cee8afa..27deefa 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -24,7 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ID_AUTO select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select MAINBOARD_DO_NATIVE_VGA_INIT select SPI_FLASH select SOC_NVIDIA_TEGRA132 @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select VIRTUAL_DEV_SWITCH select BOARD_ROMSIZE_KB_4096 select ARM64_USE_SPINTABLE - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index a91b9ea..fa8fd00 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C select EC_GOOGLE_CHROMEEC_I2C_PROTO3 - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select MAINBOARD_DO_NATIVE_VGA_INIT select SPI_FLASH select SOC_NVIDIA_TEGRA132 @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select VIRTUAL_DEV_SWITCH select ARM64_USE_SPINTABLE - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/samus/Kconfig b/src/mainboard/google/samus/Kconfig index 0b4d74d..f845eab 100644 --- a/src/mainboard/google/samus/Kconfig +++ b/src/mainboard/google/samus/Kconfig @@ -5,9 +5,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC - select VBOOT_EC_SLOW_UPDATE - select VBOOT_OPROM_MATTERS + select EC_SOFTWARE_SYNC if CHROMEOS + select VBOOT_EC_SLOW_UPDATE if CHROMEOS + select VBOOT_OPROM_MATTERS if CHROMEOS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -16,10 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select CHROMEOS_RAMOOPS_DYNAMIC + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index ba83683..26e6b97 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select VIRTUAL_DEV_SWITCH select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -20,8 +20,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_DP select INTEL_DDI select INTEL_INT15 - select CHROMEOS_VBNV_CMOS - select LID_SWITCH + select CHROMEOS_VBNV_CMOS if CHROMEOS + select LID_SWITCH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 29dae4f..0a60f1a 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -23,12 +23,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C select EC_GOOGLE_CHROMEEC_I2C_PROTO3 - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select MAINBOARD_DO_NATIVE_VGA_INIT select SPI_FLASH select SPI_FLASH_WINBOND diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 55cc5ba..029bbfb 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -31,9 +31,9 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO - select VBOOT_DISABLE_DEV_ON_RECOVERY + select VBOOT_DISABLE_DEV_ON_RECOVERY if CHROMEOS select VIRTUAL_DEV_SWITCH - select WIPEOUT_SUPPORTED + select WIPEOUT_SUPPORTED if CHROMEOS select DRIVERS_UART select CONSOLE_CBMEM_DUMP_TO_UART diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index eca83da..b723a96 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index e76496b..436248b 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -27,14 +27,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS - select PHYSICAL_REC_SWITCH + select PHYSICAL_REC_SWITCH if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND select VIRTUAL_DEV_SWITCH - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index e2128eb..95f9632 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -23,12 +23,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS - select PHYSICAL_REC_SWITCH + select PHYSICAL_REC_SWITCH if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index 3e65e67..8f72df6 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -22,11 +22,11 @@ if BOARD_GOOGLE_VEYRON_JERRY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 9233a91..cc2abf9 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -27,14 +27,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS - select PHYSICAL_REC_SWITCH + select PHYSICAL_REC_SWITCH if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND select VIRTUAL_DEV_SWITCH - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 90cdbb5..4dba498 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -22,11 +22,11 @@ if BOARD_GOOGLE_VEYRON_MIGHTY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig index a2d4846..5852e96 100644 --- a/src/mainboard/google/veyron_minnie/Kconfig +++ b/src/mainboard/google/veyron_minnie/Kconfig @@ -23,11 +23,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 4b0d471..f67cb45 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -22,11 +22,11 @@ if BOARD_GOOGLE_VEYRON_PINKY config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 0061bfa..581034d 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -23,12 +23,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS - select PHYSICAL_REC_SWITCH + select PHYSICAL_REC_SWITCH if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index b7f05d7..8c69238 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -27,14 +27,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS - select PHYSICAL_REC_SWITCH + select PHYSICAL_REC_SWITCH if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND select VIRTUAL_DEV_SWITCH - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig index 0cefbc6..0795fb2 100644 --- a/src/mainboard/google/veyron_shark/Kconfig +++ b/src/mainboard/google/veyron_shark/Kconfig @@ -23,11 +23,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index d4003dc..2aa5d98 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -23,11 +23,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_4096 - select CHROMEOS_VBNV_EC + select CHROMEOS_VBNV_EC if CHROMEOS select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig index f916138..58649e0 100644 --- a/src/mainboard/intel/baskingridge/Kconfig +++ b/src/mainboard/intel/baskingridge/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 74b8270..f31a3bc 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select INTEL_INT15 #select MAINBOARD_HAS_CHROMEOS - #select CHROMEOS_VBNV_CMOS + #select CHROMEOS_VBNV_CMOS if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 78d4081..ae7cd7f 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -5,8 +5,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384 select CACHE_ROM select CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS + select CHROMEOS_VBNV_CMOS if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC @@ -15,13 +15,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_SMI_HANDLER - select LID_SWITCH + select LID_SWITCH if CHROMEOS select MAINBOARD_HAS_CHROMEOS select MARK_GRAPHICS_MEM_WRCOMB select MMCONF_SUPPORT select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE - select VBOOT_OPROM_MATTERS + select VBOOT_OPROM_MATTERS if CHROMEOS select VIRTUAL_DEV_SWITCH config IRQ_SLOT_COUNT diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig index 601efb0..48a39a7 100644 --- a/src/mainboard/intel/sklrvp/Kconfig +++ b/src/mainboard/intel/sklrvp/Kconfig @@ -5,8 +5,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_16384 select CACHE_ROM select CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS + select CHROMEOS_VBNV_CMOS if CHROMEOS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -19,7 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_SKYLAKE select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH - select LID_SWITCH + select LID_SWITCH if CHROMEOS config IRQ_SLOT_COUNT int diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index c19761a..94924b2 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -6,11 +6,11 @@ config BOARD_SPECIFIC_OPTIONS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select CHROMEOS - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP - select EC_SOFTWARE_SYNC + select EC_SOFTWARE_SYNC if CHROMEOS select ENABLE_BUILTIN_COM1 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_BRASWELL select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH - select LID_SWITCH + select LID_SWITCH if CHROMEOS config DISPLAY_SPD_DATA diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index b8f616a..d2a00b8 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,8 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 - select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC if CHROMEOS + select CHROMEOS_VBNV_CMOS if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index fed4610..78d1aa3 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 select HAVE_MRC - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS config MAINBOARD_DIR string diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index f749c39..5ed5a4d 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -12,12 +12,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F - select PHYSICAL_REC_SWITCH + select PHYSICAL_REC_SWITCH if CHROMEOS # LPC47N207 selected for external LPC card # not on board, should be made selectable. select SUPERIO_SMSC_LPC47N207 select HAVE_MRC - select CHROMEOS_VBNV_CMOS + select CHROMEOS_VBNV_CMOS if CHROMEOS select INTEL_INT15 config MAINBOARD_DIR diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig index 7ab305c..33fe752 100644 --- a/src/soc/broadcom/cygnus/Kconfig +++ b/src/soc/broadcom/cygnus/Kconfig @@ -29,8 +29,8 @@ config SOC_BROADCOM_CYGNUS select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select HAS_PRECBMEM_TIMESTAMP_REGION - select SEPARATE_VERSTAGE - select RETURN_FROM_VERSTAGE + select SEPARATE_VERSTAGE if CHROMEOS + select RETURN_FROM_VERSTAGE if CHROMEOS select GENERIC_GPIO_LIB if SOC_BROADCOM_CYGNUS diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig index 930645e..1002781 100644 --- a/src/soc/marvell/bg4cd/Kconfig +++ b/src/soc/marvell/bg4cd/Kconfig @@ -29,7 +29,7 @@ config SOC_MARVELL_BG4CD select GENERIC_UDELAY select HAVE_MONOTONIC_TIMER select GENERIC_GPIO_LIB - select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_STARTS_IN_BOOTBLOCK if CHROMEOS if SOC_MARVELL_BG4CD diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 7aff588..20dd3fc 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -16,7 +16,7 @@ config SOC_NVIDIA_TEGRA210 select ARM_BOOTBLOCK_CUSTOM select ARM64_USE_ARM_TRUSTED_FIRMWARE select HAS_PRECBMEM_TIMESTAMP_REGION - select CHROMEOS_RAMOOPS_NON_ACPI + select CHROMEOS_RAMOOPS_NON_ACPI if CHROMEOS select GENERIC_GPIO_LIB if SOC_NVIDIA_TEGRA210 diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 9a1e4f9..1abc309 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -6,13 +6,13 @@ config SOC_QC_IPQ806X select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE - select CHROMEOS_VBNV_FLASH + select CHROMEOS_VBNV_FLASH if CHROMEOS select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB - select SEPARATE_VERSTAGE - select RETURN_FROM_VERSTAGE + select SEPARATE_VERSTAGE if CHROMEOS + select RETURN_FROM_VERSTAGE if CHROMEOS if SOC_QC_IPQ806X diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 1800b16..6fa4426 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -32,9 +32,9 @@ config SOC_ROCKCHIP_RK3288 select UNCOMPRESSED_RAMSTAGE select GENERIC_GPIO_LIB select RTC - select VBOOT_STARTS_IN_BOOTBLOCK - select SEPARATE_VERSTAGE - select RETURN_FROM_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK if CHROMEOS + select SEPARATE_VERSTAGE if CHROMEOS + select RETURN_FROM_VERSTAGE if CHROMEOS if SOC_ROCKCHIP_RK3288

1 0

New patch to review for coreboot: Intel Kconfig: Add CACHE_MRC_SETTINGS dependency on HAVE_MRC
by Martin Roth 18 Aug '15

18 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11271 -gerrit commit e4cddedbd056e67ff2a05cbcbdebeb71e4545dfd Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 11:09:14 2015 -0600 Intel Kconfig: Add CACHE_MRC_SETTINGS dependency on HAVE_MRC Add dependency on HAVE_MRC for selections of CACHE_MRC_SETTINGS. Fixes Kconfig warnings: warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_SETTINGS which has unmet direct dependencies (SOC_INTEL_BROADWELL && HAVE_MRC || SOC_INTEL_COMMON && HAVE_MRC) Change-Id: I5f3e9e54e20050ba9ac0cd97b05b4490e361581f Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/baytrail/Kconfig | 2 +- src/soc/intel/braswell/Kconfig | 2 +- src/soc/intel/broadwell/Kconfig | 2 +- src/soc/intel/skylake/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..1a1f90b 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION - select CACHE_MRC_SETTINGS + select CACHE_MRC_SETTINGS if HAVE_MRC select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4f7ed6a..07a1bf6 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION - select CACHE_MRC_SETTINGS + select CACHE_MRC_SETTINGS if HAVE_MRC select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 524366c..7009b2f 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS select VGA_ROM_RUN if !PAYLOAD_SEABIOS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION - select CACHE_MRC_SETTINGS + select CACHE_MRC_SETTINGS if HAVE_MRC select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f42d3ab..638d176 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -14,7 +14,7 @@ config CPU_SPECIFIC_OPTIONS select VGA_ROM_RUN if !PAYLOAD_SEABIOS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION - select CACHE_MRC_SETTINGS + select CACHE_MRC_SETTINGS if HAVE_MRC select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION

1 0

New patch to review for coreboot: Intel: Remove CACHE_MRC_BIN - 'selected' everywhere
by Martin Roth 18 Aug '15

18 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11270 -gerrit commit 762afc6301004bfdebb035d64d49ff6e0597b22a Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 10:41:54 2015 -0600 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere The Kconfig symbol CACHE_MRC_BIN was getting forced enabled everywhere it existed. Remove the Kconfig symbol and get rid of the #if statements surrounding the code. This fixes the Kconfig warning for Haswell & Broadwell chips: warning: (NORTHBRIDGE_INTEL_HASWELL && NORTHBRIDGE_INTEL_SANDYBRIDGE && NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE && NORTHBRIDGE_INTEL_IVYBRIDGE && NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && CPU_SPECIFIC_OPTIONS) selects CACHE_MRC_BIN which has unmet direct dependencies (CPU_INTEL_SOCKET_RPGA988B || CPU_INTEL_SOCKET_RPGA989) Change-Id: Ie0f0726e3d6f217e2cb3be73034405081ce0735a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/haswell/cache_as_ram.inc | 4 ---- src/cpu/intel/model_206ax/cache_as_ram.inc | 4 ---- src/cpu/intel/socket_rPGA988B/Kconfig | 4 ---- src/cpu/intel/socket_rPGA989/Kconfig | 4 ---- src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 4 ---- src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/broadwell/romstage/cache_as_ram.inc | 4 ---- 8 files changed, 26 deletions(-) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 0a070b2..0978bfb 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -151,7 +151,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -161,7 +160,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -219,7 +217,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -227,7 +224,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2d469ff..a3f1c64 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -146,7 +146,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -156,7 +155,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -211,7 +209,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -219,7 +216,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig index 471e522..753cfb3 100644 --- a/src/cpu/intel/socket_rPGA988B/Kconfig +++ b/src/cpu/intel/socket_rPGA988B/Kconfig @@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE -config CACHE_MRC_BIN - bool - default n - endif diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig index 83d29e7..1d1f64f 100644 --- a/src/cpu/intel/socket_rPGA989/Kconfig +++ b/src/cpu/intel/socket_rPGA989/Kconfig @@ -8,8 +8,4 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select MMX select SSE -config CACHE_MRC_BIN - bool - default n - endif diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 0a251b8..37dbd2b 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool - select CACHE_MRC_BIN select CPU_INTEL_HASWELL select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 4dede09..093224f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX @@ -27,7 +26,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_206AX @@ -36,7 +34,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX @@ -44,7 +41,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE bool - select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select CPU_INTEL_MODEL_306AX diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5853118..524366c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS select VGA_ROM_RUN if !PAYLOAD_SEABIOS select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION - select CACHE_MRC_BIN select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 05d4889..3f1b12a 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -153,7 +153,6 @@ clear_mtrrs: wrmsr post_code(0x27) -#if CONFIG_CACHE_MRC_BIN /* Enable caching for ram init code to run faster */ movl $MTRRphysBase_MSR(2), %ecx movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax @@ -163,7 +162,6 @@ clear_mtrrs: movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr -#endif post_code(0x28) /* Enable cache. */ @@ -239,7 +237,6 @@ before_romstage: andl $~1, %eax wrmsr -#if CONFIG_CACHE_MRC_BIN /* Clear MTRR that was used to cache MRC */ xorl %eax, %eax xorl %edx, %edx @@ -247,7 +244,6 @@ before_romstage: wrmsr movl $MTRRphysMask_MSR(2), %ecx wrmsr -#endif post_code(0x33)

1 0

New patch to review for coreboot: broadwell/raminit.c: Only use MRC functions when available
by Martin Roth 18 Aug '15

18 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11269 -gerrit commit 246777ed4498cdff37d1275c1a01b896939fca5e Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 15:48:44 2015 -0600 broadwell/raminit.c: Only use MRC functions when available Put a guard on the calls to mrc_cache_get_current and mrc_cache_stash_data so they only get called when they're getting built into the binary. These calls are in soc/intel/common/cache.c which gets included by the makefile with the lines: romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c Change-Id: Ia0a446e70bac4b292fef7f8b3fcea09992a4e397 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/broadwell/romstage/raminit.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 82c88cb..ea14e2b 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -55,7 +55,8 @@ void raminit(struct pei_data *pei_data) if (recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(&cache)) { + } else if ((IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) && + (!mrc_cache_get_current(&cache))) { /* MRC cache found */ pei_data->saved_data_size = cache->size; pei_data->saved_data = &cache->data[0]; @@ -121,7 +122,9 @@ void raminit(struct pei_data *pei_data) printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, pei_data->data_to_save_size); - if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) + if ((IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) && + (pei_data->data_to_save != NULL && + pei_data->data_to_save_size > 0)) mrc_cache_stash_data(pei_data->data_to_save, pei_data->data_to_save_size);

1 0

New patch to review for coreboot: Intel: Move MCRS ResourceTemplate outside of _CRS method
by Martin Roth 18 Aug '15

18 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11268 -gerrit commit 6684dc167f34ea9044f6f36c43314d217a6ae814 Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 18 16:56:05 2015 -0600 Intel: Move MCRS ResourceTemplate outside of _CRS method On Broadwell, this reduces the number of 'remarks' in the IASL build from 222 to 3. Fixes these remarks: Object is not referenced (Name is within method [_CRS]) Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b Signed-off-by: Martin Roth <martinroth(a)google.com> --- .../intel/fsp_rangeley/acpi/hostbridge.asl | 185 ++++++++-------- .../intel/fsp_sandybridge/acpi/hostbridge.asl | 185 ++++++++-------- src/northbridge/intel/gm45/acpi/hostbridge.asl | 233 ++++++++++----------- src/northbridge/intel/haswell/acpi/hostbridge.asl | 233 ++++++++++----------- src/northbridge/intel/i945/acpi/hostbridge.asl | 233 ++++++++++----------- src/northbridge/intel/nehalem/acpi/hostbridge.asl | 233 ++++++++++----------- .../intel/sandybridge/acpi/hostbridge.asl | 233 ++++++++++----------- src/northbridge/intel/sch/acpi/hostbridge.asl | 233 ++++++++++----------- src/soc/intel/broadwell/acpi/systemagent.asl | 233 ++++++++++----------- 9 files changed, 996 insertions(+), 1005 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl index a991494..084bf8c 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl @@ -30,103 +30,102 @@ Name(_BBN, 0) External (BMBD) // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR3) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0, 0x00000000, + 0,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) // End MCRS Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR3) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0, 0x00000000, - 0,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) // End MCRS - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index a1b99b8..537d398 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -239,103 +239,102 @@ Device (MCHC) } // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR3) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR3) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index cdcaa7f..98e2a4f 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -103,127 +103,126 @@ Device (MCHC) // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + IO_APIC_ADDR,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - IO_APIC_ADDR,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region: // Enter actual TOLUD. The TOLUD register contains bits 20-31 of diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 8024a5a..e58d4d0 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -321,127 +321,126 @@ Device (MCHC) } // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index b89ea00..4a4f2b1 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -103,127 +103,126 @@ Device (MCHC) // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + IO_APIC_ADDR,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - IO_APIC_ADDR,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region: // Enter actual TOLUD. The TOLUD register contains bits 27-31 of diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 0b6767e..626d1aa 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -201,127 +201,126 @@ Device (MCHC) } // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + 0xfec00000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 0e97664..1b9d847 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -239,127 +239,126 @@ Device (MCHC) } // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl index cbb17e4..7670776 100644 --- a/src/northbridge/intel/sch/acpi/hostbridge.asl +++ b/src/northbridge/intel/sch/acpi/hostbridge.asl @@ -103,127 +103,126 @@ Device (MCHC) // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + IO_APIC_ADDR,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-0xfebfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - IO_APIC_ADDR,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region: // Enter actual TOLUD. The TOLUD register contains bits 27-31 of diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl index 850eaf0..1a99ca5 100644 --- a/src/soc/intel/broadwell/acpi/systemagent.asl +++ b/src/soc/intel/broadwell/acpi/systemagent.asl @@ -43,127 +43,126 @@ Device (MCHC) } // Current Resource Settings +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) - // Find PCI resource area in MCRS - CreateDwordField(MCRS, PM01._MIN, PMIN) - CreateDwordField(MCRS, PM01._MAX, PMAX) - CreateDwordField(MCRS, PM01._LEN, PLEN) + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) // Fix up PCI memory region // Start with Top of Lower Usable DRAM

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Patch merged into coreboot/master: northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIO
by gerrit＠coreboot.org 18 Aug '15

18 Aug '15

the following patch was just integrated into master: commit 5cac25e6b2331a559394a3e3f636c4a6a80c58ac Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 16:31:14 2015 -0500 northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIO Commit 27baa32 (cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled) deactivated TSeg SMRAM, which had the side effect of routing legacy VGA memory access to DRAM. Restore the correct MMIO mapping via the MMIO configuration registers. TEST: Booted KGPE-D16 with nVidia 7300LE card and verified proper VGA functionality. Change-Id: Ie4b7c0b2d6f9a02af9a022565fe514119513190a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11240 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11240 for details. -gerrit

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coreboot-gerrit August 2015