coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: glados: Implement Chrome OS specific handlers
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11281 -gerrit commit 819ebf1b524855512371707bab8df116b43e7594 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:54:27 2015 -0700 glados: Implement Chrome OS specific handlers Implement the required Chrome OS specific handlers to read the recovery mode, clear the recovery mode, read the lid switch state, and read the write protect state using the appropriate methods. Also update the Chrome OS ACPI device to use the GPIO definitions that are exposed now by the SOC. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados and successfully enter recovery mode Original-Change-Id: Ifd51c11dc71b7d091615c29a618454a6a2cc33d7 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293515 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia6ef83a80b9729654bc87bb81bd8d7c1b01d7f42 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/chromeos.asl | 10 +++++++--- src/mainboard/google/glados/chromeos.c | 28 +++++++++++++++++++++++---- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl index 8edbff3..09f7ed1 100644 --- a/src/mainboard/google/glados/acpi/chromeos.asl +++ b/src/mainboard/google/glados/acpi/chromeos.asl @@ -17,7 +17,11 @@ * Foundation, Inc. */ -Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, // no recovery button - Package () { 0x0003, 1, 71, "INT344B:00" }, // firmware write protect +#include <soc/gpio.h> + +Name (OIPG, Package () { + /* No physical recovery GPIO. */ + Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, + /* Firmware write protect GPIO. */ + Package () { 0x0003, 1, GPP_C23, "INT344B:00" }, }) diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 70d78e0..f7a8770 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -23,10 +23,14 @@ #include <device/device.h> #include <device/pci.h> #include <rules.h> +#include <gpio.h> #include <soc/gpio.h> #include <string.h> +#include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "ec.h" + #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> @@ -55,20 +59,36 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - return 1; + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); } -/* The dev-switch is virtual */ + int get_developer_mode_switch(void) { + /* No physical developer mode switch. */ return 0; } int get_recovery_mode_switch(void) { - return 0; + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) + return 1; + + /* Otherwise check if the EC has posted the keyboard recovery event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int clear_recovery_mode_switch(void) +{ + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_write_protect_state(void) { - return 0; + /* Read PCH_WP GPIO. */ + return gpio_get(GPP_C23); }

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New patch to review for coreboot: chromeec: Add helper function to read EC switch state
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11280 -gerrit commit e052d34b51ce756e0584f41196b0630b5bda9a31 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:52:08 2015 -0700 chromeec: Add helper function to read EC switch state Add a helper function to read the EC switch state on LPC based ECs instead of having each board need to understand and use the specific EC LPC IO method that is required. BUG=chrome-os-partner:43515 BRANCH=none TEST=build and boot on glados Original-Change-Id: Id046c7ddf3a1689d4bf2241be5da31184c32c0e1 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293514 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id11009e0711b13823e4f76dc9db9c9c20abf4809 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_lpc.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 8dfefd4..3bc62c9 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -53,6 +53,7 @@ int google_chromeec_kbbacklight(int percent); void google_chromeec_post(u8 postcode); void google_chromeec_log_events(u32 mask); int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len); +uint8_t google_chromeec_get_switches(void); /* For MEC, access ranges 0x800 thru 0x9ff using EMI interface instead of LPC */ #define MEC_EMI_RANGE_START EC_HOST_CMD_REGION0 diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9d1121b..003a5f2 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -364,6 +364,12 @@ static int google_chromeec_command_v1(struct chromeec_command *cec_command) return 0; } +/* Return the byte of EC switch states */ +uint8_t google_chromeec_get_switches(void) +{ + return read_byte(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); +} + #ifdef __PRE_RAM__ int google_chromeec_command(struct chromeec_command *cec_command)

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New patch to review for coreboot: glados: Fix SPD part number for Hynix H9CCNNN8JTBLAR
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11279 -gerrit commit 4e01c52c7acb9efcc5687a30741dbda7b6cdfe95 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Aug 1 00:25:02 2015 -0700 glados: Fix SPD part number for Hynix H9CCNNN8JTBLAR The part number was the same as the H9CCNNNBLTLAR which means it is not possible to distinguish the two based on part number alone. This breaks mosys and thus the factory tests. BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 SKU3 and verify memory reported by mosys Original-Change-Id: I606ef3989bd7273d134a258bc933088ccc865542 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7cea7cc4c61a20fda47673c8e25c431d391aa3bc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex index f724c74..c296c88 100644 --- a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex @@ -6,7 +6,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 -48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +48 39 43 43 4E 4E 4E 38 4A 54 42 4C 41 52 2D 4E 54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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New patch to review for coreboot: glados: Add touchscreen device in ACPI
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11278 -gerrit commit 8c4ed4d185c9a9ac8f89e555af7eed72273f0227 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:27:56 2015 -0700 glados: Add touchscreen device in ACPI Add the ELAN touchscreen device in ACPI to bind it to the I2C device at bus I2C0, address 0x10, interrupt 31 (GPP_E7). BUG=chrome-os-partner:43514 BRANCH=none TEST=boot on glados P2 and see touchscreen initialized by kernel Original-Change-Id: I23b071b2767547baed239c94216cda6162d045dd Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293512 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8a9492e6fa1f650cef0871329ae8944caffdaf5a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/mainboard.asl | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index f955bb7..e2a1b5f 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -22,6 +22,9 @@ #define BOARD_TOUCHPAD_I2C_ADDR 0x15 #define BOARD_TOUCHPAD_IRQ GPP_B3_IRQ +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 +#define BOARD_TOUCHSCREEN_IRQ GPP_E7_IRQ + #define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a #define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR 0x34 #define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR 0x35 @@ -72,6 +75,38 @@ Scope (\_SB.PCI0.LPCB) #include <drivers/pc80/tpm/acpi/tpm.asl> } +Scope (\_SB.PCI0.I2C0) +{ + /* Touchscreen */ + Device (ELTS) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen") + Name (_UID, 1) + Name (_S0W, 4) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C0", + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + Return (0xF) + } + } +} + Scope (\_SB.PCI0.I2C1) { /* Touchpad */

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New patch to review for coreboot: glados: Clean up mainboard ACPI devices
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11277 -gerrit commit 13369df16ef0af2e37d499a6ac865b066a54cba1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 13 12:18:52 2015 -0700 glados: Clean up mainboard ACPI devices Clean up the device code for the glados mainboard, using the defined values for interrupts by the SOC and moving the various codec i2c addresses to the top of the file. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Original-Change-Id: Iead1aeb54363b15a6176d4f4a9511674195c0505 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293511 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I083c9ef6140e20a433cb2017e4c3cbc7a41e8fed Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/mainboard.asl | 68 ++++++++++++++------------ 1 file changed, 38 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index f8bc462..f955bb7 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -19,8 +19,12 @@ #include <soc/gpio.h> -#define BOARD_TRACKPAD_I2C_ADDR 0x15 -#define BOARD_TRACKPAD_IRQ GPP_B3_IRQ +#define BOARD_TOUCHPAD_I2C_ADDR 0x15 +#define BOARD_TOUCHPAD_IRQ GPP_B3_IRQ + +#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a +#define BOARD_LEFT_SPEAKER_AMP_I2C_ADDR 0x34 +#define BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR 0x35 Scope (\_SB) { @@ -68,30 +72,31 @@ Scope (\_SB.PCI0.LPCB) #include <drivers/pc80/tpm/acpi/tpm.asl> } -/* Trackpad */ Scope (\_SB.PCI0.I2C1) { - Device (ELAN) + /* Touchpad */ + Device (ELTP) { Name (_HID, "ELAN0000") Name (_DDN, "Elan Touchpad") - Name (_UID, 3) + Name (_UID, 1) Name (_S0W, 4) - Name (ISTP, 1) /* TouchPad */ + Name (_CRS, ResourceTemplate() { I2cSerialBus ( - BOARD_TRACKPAD_I2C_ADDR, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C1", /* ResourceSource */ + BOARD_TOUCHPAD_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C1", ) Interrupt (ResourceConsumer, Edge, ActiveLow) { - BOARD_TRACKPAD_IRQ + BOARD_TOUCHPAD_IRQ } }) + Method (_STA) { Return (0xF) @@ -101,7 +106,8 @@ Scope (\_SB.PCI0.I2C1) Scope (\_SB.PCI0.I2C4) { - Device (CODC) // Codec for headset + /* Headphone Codec */ + Device (HPMC) { Name (_HID, "10508825") Name (_DDN, "NAU88L25 Codec") @@ -110,11 +116,11 @@ Scope (\_SB.PCI0.I2C4) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x1A, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C4", /* ResourceSource */ + BOARD_HP_MIC_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", ) }) @@ -124,7 +130,8 @@ Scope (\_SB.PCI0.I2C4) } } - Device (SPK0) // Left speaker Amp + /* Left Speaker Amp */ + Device (SPKL) { Name (_HID, "INT343B") Name (_DDN, "SSM4567 Speaker Amp") @@ -133,11 +140,11 @@ Scope (\_SB.PCI0.I2C4) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x34, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C4", /* ResourceSource */ + BOARD_LEFT_SPEAKER_AMP_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", ) }) @@ -147,7 +154,8 @@ Scope (\_SB.PCI0.I2C4) } } - Device (SPK1) // Right speaker Amp + /* Right Speaker Amp */ + Device (SPKR) { Name (_HID, "INT343B") Name (_DDN, "SSM4567 Speaker Amp") @@ -156,11 +164,11 @@ Scope (\_SB.PCI0.I2C4) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x35, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C4", /* ResourceSource */ + BOARD_RIGHT_SPEAKER_AMP_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C4", ) })

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New patch to review for coreboot: kunimitsu: Enable SMBus device in devicetree
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11276 -gerrit commit 091b4a8b94b7900cb079516eb70cbffbd05f6be8 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Mon Aug 10 11:49:07 2015 +0530 kunimitsu: Enable SMBus device in devicetree this patch enables SMBus in device tree for kunimitsu board. BRANCH=none BUG=none TEST=built for kunimitsu; booted on kunimitsu fab3 and verified with lspci Original-Change-Id: I3b2b8c202b71c2a0c602169841978ed0c4d8bf8d Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292971 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id20e6cafda8664bd0ae3a5acecdd66c58c220694 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index b5f0dbb..6d0e2f4 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -140,7 +140,7 @@ chip soc/intel/skylake end # LPC Interface device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech) - device pci 1f.4 off end # SMBus Controller + device pci 1f.4 on end # SMBus Controller device pci 1f.5 on end # SPI device pci 1f.6 off end # GbE Controller end

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New patch to review for coreboot: Kunimitsu : FAB3 Adding BoardId support
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11275 -gerrit commit 6ab5c7937929bf8055ca90c8b2b5da39ad1b5926 Author: pchandri <preetham.chandrian(a)intel.com> Date: Thu Aug 6 10:26:00 2015 -0700 Kunimitsu : FAB3 Adding BoardId support BRANCH=None BUG=chrome-os-partner:44087 TEST=Build and Boot kunimitsu. Original-Change-Id: I30ba8bad69a4fdf8ec29f9eb43a27d2e1c6b93dd Original-Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293832 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I8f85547865387091c9a6400611e3314f457076d5 Signed-off-by: pchandri <preetham.chandrian(a)intel.com> --- src/mainboard/intel/kunimitsu/Makefile.inc | 2 ++ src/mainboard/intel/kunimitsu/boardid.c | 34 ++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index da996a5..522308f 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -28,4 +28,6 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c ramstage-y += pei_data.c ramstage-y += ramstage.c +ramstage-y += boardid.c +romstage-y += boardid.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/kunimitsu/boardid.c b/src/mainboard/intel/kunimitsu/boardid.c new file mode 100644 index 0000000..58da22e --- /dev/null +++ b/src/mainboard/intel/kunimitsu/boardid.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> + + +uint8_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + if (id < 0) + id = google_chromeec_get_board_version(); + + return id; +} +

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New patch to review for coreboot: Kunimitsu: enable deep S5
by Aaron Durbin 19 Aug '15

19 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11274 -gerrit commit 126c88c12b0a26b2d96aedf5b027676e7acd9d8d Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Fri Jul 10 16:00:51 2015 +0530 Kunimitsu: enable deep S5 This patche enables the deep S5 and disables Deep S3. Kunimitsu does not resume from deep S3. This change will unblock the S3 resume path on kunimitsu board. BRANCH=None BUG=chrome-os-partner:42331 TEST=Built and booted on kunimitsu; check s3 works. Original-Change-Id: Ia828a39bceef615fd194bb3614ba2de87c3af805 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291250 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I07b95a324a27ab658e80674686b47b86412ea097 Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 09e41b9..b5f0dbb 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -82,6 +82,13 @@ chip soc/intel/skylake # Integrated Sensor register "IshEnable" = "0" + # Enable deep Sx states + register "deep_s3_enable" = "0" + register "deep_s5_enable" = "1" + + # CPU Thermal participant device + register "Device4Enable" = "1" + # XDCI controller register "XdciEnable" = "0" @@ -131,6 +138,7 @@ chip soc/intel/skylake device pnp 0c09.0 on end end end # LPC Interface + device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech) device pci 1f.4 off end # SMBus Controller device pci 1f.5 on end # SPI

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Patch merged into coreboot/master: skylake: Update Memory and Silicon Init params
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 5c1c3d69dd47e11bea2e3f61eeb17ed13e5a8e0d Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jul 21 20:21:50 2015 +0530 skylake: Update Memory and Silicon Init params Update the MemoryInit and SilicoInit params as per FSP 1.3.0 release. Note: add SvGv and Rmt to Upd. BRANCH=None BUG=None TEST=Build and Boot FAB3 (Kunimitsu) CQ-DEPEND=CL:*226035, CL:*226045 Original-Change-Id: I62000f6a485fee42ef733c3b548192f2bedfce49 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291573 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Change-Id: Iaafa658b4e710fe512526a521cf6c529efb19bf0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Reviewed-on: http://review.coreboot.org/11238 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11238 for details. -gerrit

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Patch merged into coreboot/master: Skylake: update cbmem_top
by gerrit＠coreboot.org 19 Aug '15

19 Aug '15

the following patch was just integrated into master: commit 188e37072fbd79a7a947a903f9918a49f32a08d6 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 17:40:32 2015 +0530 Skylake: update cbmem_top cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory regions reserved by fsp for chipset use. With that being removed, the function needs to properly walk though the memory map resulted from fsp memory init to find out the usable address for cbmem root. Refer the FSP 1.3.0 Integartion guide for more details on the Memory Map. systemagent should also use the same mechanism to create the reserved RAM resource. BRANCH=None BUG=None TEST=Build and Boot kunimitsu (FAB3) CQ-DEPEND=CL:*226035,CL:*226045,CL:291573 Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291611 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang(a)intel.com> Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: http://review.coreboot.org/11239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11239 for details. -gerrit

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coreboot-gerrit August 2015