coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

1 participants
1048 discussions

New patch to review for coreboot: ARMv8: Bootblock: Fix compile and runtime errors
by Naman Govil 08 Jul '15

08 Jul '15

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10854 -gerrit commit 3e2bee6fed708132cf4240a9afdd03a8f1901990 Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Fri Sep 5 10:49:34 2014 +0530 ARMv8: Bootblock: Fix compile and runtime errors This patch intends to fix following logical errors: 1. bootblock.S is getting compiled everytime even if CONFIG_ARM_BOOTBLOCK_CUSTOM is not defined. bootblock.S contains same declarations as of id.S, hence, compiler complains for duplicate definitions. 2. mmu_enable, exception_hwinit and arch_secondary_cpu_init function calls are happening for all stages without any check but the definitions for these functions are getting compiled only for ramstage. Obviously compiler doesn't find that definitions in case bootblock and complains. 3. bootblock_cpu_init, bootblock_mainboard_init are required to be called from bootblock's main function when CPU_HAS_BOOTBLOCK_INIT and alike CONFIGS are enabled. But these function calls are commented. 4. CONFIG_BOOTBLOCK_CONSOLE is always defined. When it is enbaled it contains value 1 in the final config else 0. Checking this config with #ifdef doesn't make sense, hence, replaced it with if. BRANCH=None BUG=None TEST=Compiled and booted over Jazz board using linaro-4.8 gnu gcc and didn't find errors related to this part of code Change-Id: I72fe02509c25e76c029ee6af0442f059adb54736 Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/arch/arm64/armv8/Makefile.inc | 3 ++- src/arch/arm64/armv8/bootblock_simple.c | 12 ++++++------ src/arch/arm64/c_entry.c | 17 +++++++++++++++++ src/arch/arm64/include/bootblock_common.h | 6 +++++- 4 files changed, 30 insertions(+), 8 deletions(-) diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 0c4778d..13181a8 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -32,8 +32,9 @@ armv8_asm_flags = $(armv8_flags) ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) -ifneq ($(CONFIG_ARM64_BOOTBLOCK_CUSTOM),y) +ifeq ($(CONFIG_ARM64_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock.S +else bootblock-y += bootblock_simple.c endif bootblock-y += cache.c diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c index 5e00890..c93a100 100644 --- a/src/arch/arm64/armv8/bootblock_simple.c +++ b/src/arch/arm64/armv8/bootblock_simple.c @@ -51,14 +51,14 @@ void main(void) */ if (boot_cpu()) { - //bootblock_cpu_init(); - //bootblock_mainboard_init(); + bootblock_cpu_init(); + bootblock_mainboard_init(); } -#ifdef CONFIG_BOOTBLOCK_CONSOLE - console_init(); - exception_init(); -#endif + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + console_init(); + exception_init(); + } run_romstage(); } diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index a4d4773..5970405 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -29,6 +29,12 @@ void __attribute__((weak)) arm64_soc_init(void) /* Default weak implementation does nothing. */ } +unsigned int __attribute__((weak)) smp_processor_id(void) +{ + /* Default weak implementation does nothing. */ + return 0; +} + static void seed_stack(void) { char *stack_begin; @@ -57,6 +63,17 @@ static void arm64_init(void) main(); } +static void secondary_cpu_start(void) +{ +#ifndef __PRE_RAM__ + mmu_enable(); + exception_hwinit(); + + /* This will never return. */ + arch_secondary_cpu_init(); +#endif +} + /* * This variable holds entry point for CPUs starting up. The first * element is the BSP path, and the second is the non-BSP path. diff --git a/src/arch/arm64/include/bootblock_common.h b/src/arch/arm64/include/bootblock_common.h index 2fa705f..ed6569e 100644 --- a/src/arch/arm64/include/bootblock_common.h +++ b/src/arch/arm64/include/bootblock_common.h @@ -5,7 +5,11 @@ #ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT #include CONFIG_BOOTBLOCK_MAINBOARD_INIT #else -static void bootblock_mainboard_init(void) +static inline void bootblock_mainboard_init(void) { + /* + * Do nothing. + * Start adding activities as and when required + */ } #endif

1 0

Patch set updated for coreboot: armv8 : coreboot for qemu aarch64 #Work in progress#
by Naman Govil 08 Jul '15

08 Jul '15

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10527 -gerrit commit 316c57572bd5c675789b940927cca7ff986e7310 Author: Naman Govil <namangov(a)gmail.com> Date: Wed Jun 10 16:18:52 2015 -0400 armv8 : coreboot for qemu aarch64 #Work in progress# This patchset aims to add a new mainboard (emulation) for arm64. By the end of this work, we will have coreboot running on a qemu-system-aarch64. Change-Id: I5550dcaae9981908e0c3bf6961206a70bebac5d1 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/arch/arm64/c_entry.c | 6 +- src/arch/arm64/cpu.c | 3 +- src/arch/arm64/cpu.h | 204 +++++++++++++++++++++ src/arch/arm64/include/arch/cpu.h | 204 +++++++++++++++++++++ src/arch/arm64/include/armv8/arch/secmon.h | 4 +- src/cpu/armltd/armv8/Kconfig | 11 ++ src/include/smp/node.h | 2 +- src/mainboard/emulation/qemu-armv8/Kconfig | 55 ++++++ src/mainboard/emulation/qemu-armv8/Kconfig.name | 2 + src/mainboard/emulation/qemu-armv8/Makefile.inc | 43 +++++ src/mainboard/emulation/qemu-armv8/board_info.txt | 3 + .../emulation/qemu-armv8/bootblock-common.h | 22 +++ src/mainboard/emulation/qemu-armv8/bootblock.c | 25 +++ src/mainboard/emulation/qemu-armv8/cbmem.c | 25 +++ src/mainboard/emulation/qemu-armv8/cpu_lib.S | 29 +++ src/mainboard/emulation/qemu-armv8/devicetree.cb | 20 ++ src/mainboard/emulation/qemu-armv8/mainboard.c | 27 +++ src/mainboard/emulation/qemu-armv8/media.c | 25 +++ src/mainboard/emulation/qemu-armv8/memlayout.ld | 48 +++++ src/mainboard/emulation/qemu-armv8/romstage.c | 40 ++++ src/mainboard/emulation/qemu-armv8/timer.c | 27 +++ src/mainboard/emulation/qemu-armv8/uart.c | 24 +++ util/cbfstool/cbfs_image.c | 1 + util/crossgcc/buildgcc | 2 +- util/genbuild_h/genbuild_h.sh | 6 +- 25 files changed, 849 insertions(+), 9 deletions(-) diff --git a/src/arch/arm64/c_entry.c b/src/arch/arm64/c_entry.c index 5970405..ec0fd08 100644 --- a/src/arch/arm64/c_entry.c +++ b/src/arch/arm64/c_entry.c @@ -78,7 +78,11 @@ static void secondary_cpu_start(void) * This variable holds entry point for CPUs starting up. The first * element is the BSP path, and the second is the non-BSP path. */ -void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init }; +#ifdef __PRE_RAM__ +void (*c_entry[2])(void) = { &arm64_init, NULL}; +#else +void (*c_entry[2])(void) = { &arm64_init, &arch_secondary_cpu_init}; +#endif void *prepare_secondary_cpu_startup(void) { diff --git a/src/arch/arm64/cpu.c b/src/arch/arm64/cpu.c index 3cf73ae..1026434 100644 --- a/src/arch/arm64/cpu.c +++ b/src/arch/arm64/cpu.c @@ -219,8 +219,9 @@ void arch_cpu_wait_for_action(void) action_queue_complete(q, orig); } } - +#ifdef __PRE_RAM__ int boot_cpu(void) { return cpu_is_bsp(); } +#endif diff --git a/src/arch/arm64/cpu.h b/src/arch/arm64/cpu.h new file mode 100644 index 0000000..ae16fa1 --- /dev/null +++ b/src/arch/arm64/cpu.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_CPU_H__ +#define __ARCH_CPU_H__ + +#define asmlinkage + +#if !defined(__PRE_RAM__) +#include <arch/barrier.h> +#include <arch/mpidr.h> +#include <device/device.h> + +enum { + CPU_ID_END = 0x00000000, +}; + +struct cpu_device_id { + uint32_t midr; +}; + +struct cpu_driver { + /* This is excessive as init() is the only one called. */ + struct device_operations *ops; + const struct cpu_device_id *id_table; +}; + +/* Action to run. */ +struct cpu_action { + void (*run)(void *arg); + void *arg; +}; + +/* + * Actions are queued to 'todo'. When picked up 'todo' is cleared. The + * 'completed' field is set to the original 'todo' value when the action + * is complete. + */ +struct cpu_action_queue { + struct cpu_action *todo; + struct cpu_action *completed; +}; + +struct cpu_info { + device_t cpu; + struct cpu_action_queue action_queue; + unsigned int online; + /* Current assumption is that id matches smp_processor_id(). */ + unsigned int id; + uint64_t mpidr; +}; + +/* Obtain cpu_info for current executing CPU. */ +struct cpu_info *cpu_info(void); + +extern struct cpu_info *bsp_cpu_info; +extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; + +static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) +{ + return &cpu_infos[id]; +} + +/* Ran only by BSP at initial boot strapping. */ +static inline void cpu_set_bsp(void) +{ + bsp_cpu_info = cpu_info(); +} + +static inline int cpu_is_bsp(void) +{ + return cpu_info() == bsp_cpu_info; +} + +static inline int cpu_online(struct cpu_info *ci) +{ + return load_acquire(&ci->online) != 0; +} + +static inline void cpu_mark_online(struct cpu_info *ci) +{ + ci->mpidr = read_affinity_mpidr(); + store_release(&ci->online, 1); +} + +/* Provide number of CPUs online. */ +size_t cpus_online(void); + +/* Control routines for starting CPUs. */ +struct cpu_control_ops { + /* Return the maximum number of CPUs supported. */ + size_t (*total_cpus)(void); + /* + * Start the requested CPU and have it start running entry(). + * Returns 0 on success, < 0 on error. + */ + int (*start_cpu)(unsigned int id, void (*entry)(void)); +}; + +/* + * Initialize all DEVICE_PATH_CPUS under the DEVICE_PATH_CPU_CLUSTER cluster. + * type DEVICE_PATH_CPUS. Start up is controlled by cntrl_ops. + */ +void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops); + +/* + * Run cpu_action returning < 0 on error, 0 on success. There are synchronous + * and asynchronous methods. Both cases ensure the action has been picked up + * by the target cpu. The synchronous variants will wait for the action to + * be completed before returning. + * + * Though the current implementation allows queuing actions on the main cpu, + * the main cpu doesn't process its own queue. + */ +int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus(struct cpu_action *action); +int arch_run_on_all_cpus_but_self(struct cpu_action *action); +int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus_async(struct cpu_action *action); +int arch_run_on_all_cpus_but_self_async(struct cpu_action *action); + +/* Wait for actions to be perfomed. */ +void arch_cpu_wait_for_action(void); + +#endif /* !__PRE_RAM__ */ + +/* + * Returns logical cpu in range [0:MAX_CPUS). SoC should define this. + * Additionally, this is needed early in arm64 init so it should not + * rely on a stack. Standard clobber list is fair game: x0-x7 and x0 + * returns the logical cpu number. + */ +unsigned int smp_processor_id(void); + +/* + * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided + * a pointer the correct non-BSP entry point will be returned. The + * first instruction is for BSP and the 2nd is for non-BSP. Instructions + * are all 32-bit on arm64. + */ +static inline void *secondary_entry_point(void *e) +{ + uintptr_t nonbsp = (uintptr_t)e; + + return (void *)(nonbsp + sizeof(uint32_t)); +} + +/* + * The arm64_cpu_startup() initializes a CPU's exception stack and regular + * stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + */ +void arm64_cpu_startup(void); + +/* + * The arm64_cpu_startup_resume() initializes a CPU's exception stack and + * regular stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + * Additionally, it also restores saved register data and enables MMU, caches + * and exceptions before jumping to C environment for both BSP and non-BSP CPUs. + */ +void arm64_cpu_startup_resume(void); + +/* + * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of + * ARM arch timer. + */ +void arm64_arch_timer_init(void); + +/* + * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM. + * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported. + */ +#define NO_L2_FLUSH 0 +#define L2_FLUSH_HW 0 +#define L2_FLUSH_SW 1 + +#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) +void cortex_a57_cpu_power_down(int l2_flush); +#else +static inline void cortex_a57_cpu_power_down(int l2_flush) {} +#endif + +#endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/arch/cpu.h b/src/arch/arm64/include/arch/cpu.h new file mode 100644 index 0000000..ae16fa1 --- /dev/null +++ b/src/arch/arm64/include/arch/cpu.h @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_CPU_H__ +#define __ARCH_CPU_H__ + +#define asmlinkage + +#if !defined(__PRE_RAM__) +#include <arch/barrier.h> +#include <arch/mpidr.h> +#include <device/device.h> + +enum { + CPU_ID_END = 0x00000000, +}; + +struct cpu_device_id { + uint32_t midr; +}; + +struct cpu_driver { + /* This is excessive as init() is the only one called. */ + struct device_operations *ops; + const struct cpu_device_id *id_table; +}; + +/* Action to run. */ +struct cpu_action { + void (*run)(void *arg); + void *arg; +}; + +/* + * Actions are queued to 'todo'. When picked up 'todo' is cleared. The + * 'completed' field is set to the original 'todo' value when the action + * is complete. + */ +struct cpu_action_queue { + struct cpu_action *todo; + struct cpu_action *completed; +}; + +struct cpu_info { + device_t cpu; + struct cpu_action_queue action_queue; + unsigned int online; + /* Current assumption is that id matches smp_processor_id(). */ + unsigned int id; + uint64_t mpidr; +}; + +/* Obtain cpu_info for current executing CPU. */ +struct cpu_info *cpu_info(void); + +extern struct cpu_info *bsp_cpu_info; +extern struct cpu_info cpu_infos[CONFIG_MAX_CPUS]; + +static inline struct cpu_info *cpu_info_for_cpu(unsigned int id) +{ + return &cpu_infos[id]; +} + +/* Ran only by BSP at initial boot strapping. */ +static inline void cpu_set_bsp(void) +{ + bsp_cpu_info = cpu_info(); +} + +static inline int cpu_is_bsp(void) +{ + return cpu_info() == bsp_cpu_info; +} + +static inline int cpu_online(struct cpu_info *ci) +{ + return load_acquire(&ci->online) != 0; +} + +static inline void cpu_mark_online(struct cpu_info *ci) +{ + ci->mpidr = read_affinity_mpidr(); + store_release(&ci->online, 1); +} + +/* Provide number of CPUs online. */ +size_t cpus_online(void); + +/* Control routines for starting CPUs. */ +struct cpu_control_ops { + /* Return the maximum number of CPUs supported. */ + size_t (*total_cpus)(void); + /* + * Start the requested CPU and have it start running entry(). + * Returns 0 on success, < 0 on error. + */ + int (*start_cpu)(unsigned int id, void (*entry)(void)); +}; + +/* + * Initialize all DEVICE_PATH_CPUS under the DEVICE_PATH_CPU_CLUSTER cluster. + * type DEVICE_PATH_CPUS. Start up is controlled by cntrl_ops. + */ +void arch_initialize_cpus(device_t cluster, struct cpu_control_ops *cntrl_ops); + +/* + * Run cpu_action returning < 0 on error, 0 on success. There are synchronous + * and asynchronous methods. Both cases ensure the action has been picked up + * by the target cpu. The synchronous variants will wait for the action to + * be completed before returning. + * + * Though the current implementation allows queuing actions on the main cpu, + * the main cpu doesn't process its own queue. + */ +int arch_run_on_cpu(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus(struct cpu_action *action); +int arch_run_on_all_cpus_but_self(struct cpu_action *action); +int arch_run_on_cpu_async(unsigned int cpu, struct cpu_action *action); +int arch_run_on_all_cpus_async(struct cpu_action *action); +int arch_run_on_all_cpus_but_self_async(struct cpu_action *action); + +/* Wait for actions to be perfomed. */ +void arch_cpu_wait_for_action(void); + +#endif /* !__PRE_RAM__ */ + +/* + * Returns logical cpu in range [0:MAX_CPUS). SoC should define this. + * Additionally, this is needed early in arm64 init so it should not + * rely on a stack. Standard clobber list is fair game: x0-x7 and x0 + * returns the logical cpu number. + */ +unsigned int smp_processor_id(void); + +/* + * Stages and rmodules have 2 entry points: BSP and non-BSP. Provided + * a pointer the correct non-BSP entry point will be returned. The + * first instruction is for BSP and the 2nd is for non-BSP. Instructions + * are all 32-bit on arm64. + */ +static inline void *secondary_entry_point(void *e) +{ + uintptr_t nonbsp = (uintptr_t)e; + + return (void *)(nonbsp + sizeof(uint32_t)); +} + +/* + * The arm64_cpu_startup() initializes a CPU's exception stack and regular + * stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + */ +void arm64_cpu_startup(void); + +/* + * The arm64_cpu_startup_resume() initializes a CPU's exception stack and + * regular stack as well initializing the C environment for the processor. It + * calls into the array of function pointers at symbol c_entry depending + * on BSP state. Note that arm64_cpu_startup contains secondary entry + * point which can be obtained by secondary_entry_point(). + * Additionally, it also restores saved register data and enables MMU, caches + * and exceptions before jumping to C environment for both BSP and non-BSP CPUs. + */ +void arm64_cpu_startup_resume(void); + +/* + * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of + * ARM arch timer. + */ +void arm64_arch_timer_init(void); + +/* + * The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM. + * L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported. + */ +#define NO_L2_FLUSH 0 +#define L2_FLUSH_HW 0 +#define L2_FLUSH_SW 1 + +#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT) +void cortex_a57_cpu_power_down(int l2_flush); +#else +static inline void cortex_a57_cpu_power_down(int l2_flush) {} +#endif + +#endif /* __ARCH_CPU_H__ */ diff --git a/src/arch/arm64/include/armv8/arch/secmon.h b/src/arch/arm64/include/armv8/arch/secmon.h index f8351b5..6458893 100644 --- a/src/arch/arm64/include/armv8/arch/secmon.h +++ b/src/arch/arm64/include/armv8/arch/secmon.h @@ -24,8 +24,8 @@ struct secmon_params { size_t online_cpus; - struct cpu_action bsp; - struct cpu_action secondary; + struct cpu_action *bsp; + struct cpu_action *secondary; }; void secmon_run(void (*entry)(void *), void *arg); diff --git a/src/cpu/armltd/armv8/Kconfig b/src/cpu/armltd/armv8/Kconfig new file mode 100644 index 0000000..e73980c --- /dev/null +++ b/src/cpu/armltd/armv8/Kconfig @@ -0,0 +1,11 @@ +config CPU_ARMLTD_ARMV8 + bool + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + default n + +if CPU_ARMLTD_ARMV8 + +endif diff --git a/src/include/smp/node.h b/src/include/smp/node.h index 4e45c46..91f94db 100644 --- a/src/include/smp/node.h +++ b/src/include/smp/node.h @@ -4,7 +4,7 @@ #if CONFIG_SMP int boot_cpu(void); #else -#define boot_cpu(x) 1 +#define boot_cpu(x) 1 #endif #endif /* _SMP_NODE_H_ */ diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig b/src/mainboard/emulation/qemu-armv8/Kconfig new file mode 100644 index 0000000..d152813 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Kconfig @@ -0,0 +1,55 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# WRITE THE INSTRUCTIONS TO EXECUTE +# To execute, do: +# export QEMU_AUDIO_DRV=none +# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom + +if BOARD_EMULATION_QEMU_ARMV8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select DRIVERS_UART_PL011 + select BOOTBLOCK_CONSOLE + select EARLY_CONSOLE + select CONSOLE_SERIAL + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select BOARD_ROMSIZE_KB_4096 + + +config MAINBOARD_DIR + string + default emulation/qemu-armv8 + +config MAINBOARD_PART_NUMBER + string + default "QEMU ARMv8" + +config MAX_CPUS + int + default 2 + +config MAINBOARD_VENDOR + string + default "ARM Ltd." + +config DRAM_SIZE_MB + int + default 1024 + +endif # BOARD_EMULATION_QEMU_ARMV8 diff --git a/src/mainboard/emulation/qemu-armv8/Kconfig.name b/src/mainboard/emulation/qemu-armv8/Kconfig.name new file mode 100644 index 0000000..bb3a0e4 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_EMULATION_QEMU_ARMV8 + bool "QEMU armv8" diff --git a/src/mainboard/emulation/qemu-armv8/Makefile.inc b/src/mainboard/emulation/qemu-armv8/Makefile.inc new file mode 100644 index 0000000..dfe5342 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/Makefile.inc @@ -0,0 +1,43 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +romstage-y += romstage.c + +romstage-y += cbmem.c +ramstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += timer.c +romstage-y += timer.c +ramstage-y += timer.c + +bootblock-y += uart.c +romstage-y += uart.c +ramstage-y += uart.c + +bootblock-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld + +bootblock-y += cpu_lib.S +romstage-y += cpu_lib.S +ramstage-y += cpu_lib.S + +//bootblock-y += bootblock.c +//romstage-y += bootblock.c +//ramstage-y += bootblock.c diff --git a/src/mainboard/emulation/qemu-armv8/board_info.txt b/src/mainboard/emulation/qemu-armv8/board_info.txt new file mode 100644 index 0000000..69c5eb6 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU armv8 +Category: emulation +Board URL: http://fabrice.bellard.free.fr/qemu/ diff --git a/src/mainboard/emulation/qemu-armv8/bootblock-common.h b/src/mainboard/emulation/qemu-armv8/bootblock-common.h new file mode 100644 index 0000000..1b34a47 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/bootblock-common.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <console/console.h> + +void bootblock_cpu_init(void); + + + diff --git a/src/mainboard/emulation/qemu-armv8/bootblock.c b/src/mainboard/emulation/qemu-armv8/bootblock.c new file mode 100644 index 0000000..47d5308 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <console/console.h> +#include "bootblock-common.h" + +void bootblock_cpu_init(void) +{ + +} + + diff --git a/src/mainboard/emulation/qemu-armv8/cbmem.c b/src/mainboard/emulation/qemu-armv8/cbmem.c new file mode 100644 index 0000000..d3a2d6f --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <stddef.h> +#include <cbmem.h> +#include <symbols.h> + +void *cbmem_top(void) +{ + return _dram + (CONFIG_DRAM_SIZE_MB << 20); +} diff --git a/src/mainboard/emulation/qemu-armv8/cpu_lib.S b/src/mainboard/emulation/qemu-armv8/cpu_lib.S new file mode 100644 index 0000000..13eed4b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/cpu_lib.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright 2015, Naman Govil <namangov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + +.text +.global smp_processor_id +smp_processor_id: + /* Core 0 and 1 are encoded in the Aff0 (7:0) field of MPIDR_EL1. */ + /* Multiprocessor Afinity Register (MPIDR) contains CPU ID for a57 */ + mrs x0, mpidr_el1 + uxtb w0, w0 + ret diff --git a/src/mainboard/emulation/qemu-armv8/devicetree.cb b/src/mainboard/emulation/qemu-armv8/devicetree.cb new file mode 100644 index 0000000..fa3c03a --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +# TODO fill with Versatile Express board data in QEMU. +chip cpu/armltd/armv8 + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end diff --git a/src/mainboard/emulation/qemu-armv8/mainboard.c b/src/mainboard/emulation/qemu-armv8/mainboard.c new file mode 100644 index 0000000..b73ab9d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Enable qemu/armv8 device...\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/emulation/qemu-armv8/media.c b/src/mainboard/emulation/qemu-armv8/media.c new file mode 100644 index 0000000..4d4edd8 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/media.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> + +/* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-armv8/memlayout.ld b/src/mainboard/emulation/qemu-armv8/memlayout.ld new file mode 100644 index 0000000..ee8132d --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/memlayout.ld @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C )2015, Naman Govil <namangov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Memory map for qemu armv8: + * + * 0x0000_0000: jump instruction (required by qemu) + * 0x0001_0000: bootblock (entry of kernel / firmware) + * 0x0002_0000: romstage, assume up to 128KB in size. + * 0x0007_ff00: stack pointer + * 0x0010_0000: CBFS header + * 0x0011_0000: CBFS data + * 0x0100_0000: reserved for ramstage + * 0x1000_0000: I/O map address + */ + +SECTIONS +{ + /* TODO: does this thing emulate SRAM? */ + + BOOTBLOCK(0x10000, 64K) + ROMSTAGE(0x20000, 128K) + STACK(0x000FC000, 16K) + + DRAM_START(0x01000000) + RAMSTAGE(0x01000000, 16M) +} diff --git a/src/mainboard/emulation/qemu-armv8/romstage.c b/src/mainboard/emulation/qemu-armv8/romstage.c new file mode 100644 index 0000000..6f6ed5b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/romstage.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +#include <cbfs.h> +#include <console/console.h> +#include <program_loading.h> +#include <arch/stages.h> + +void main(void) +{ + void *entry; + console_init(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); + //run_ramstage(); +} + +*/ +#include <console/console.h> +#include <program_loading.h> + +void main(void) +{ + console_init(); + run_ramstage(); +} diff --git a/src/mainboard/emulation/qemu-armv8/timer.c b/src/mainboard/emulation/qemu-armv8/timer.c new file mode 100644 index 0000000..b6d048b --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015, Naman Govil <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void udelay(unsigned int n); +void udelay(unsigned int n) +{ + /* TODO provide delay here. */ +} + +int init_timer(void); +int init_timer(void) +{ + return 0; +} diff --git a/src/mainboard/emulation/qemu-armv8/uart.c b/src/mainboard/emulation/qemu-armv8/uart.c new file mode 100644 index 0000000..0fc2390 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv8/uart.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Naman Govil, <namangov(a)gmail.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/uart.h> + +#define UART0_IO_ADDRESS (0x1C090000) + +uintptr_t uart_platform_base(int idx) +{ + return UART0_IO_ADDRESS; +} diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2ce4bdd..fb313d3 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -24,6 +24,7 @@ #include <stdlib.h> #include <string.h> #include <strings.h> +#include <arpa/inet.h> #include "common.h" #include "cbfs_image.h" diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b78b141..f7a8023 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -387,7 +387,7 @@ build_BINUTILS() { fi CC="$CC" ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR \ --target=${TARGETARCH} --enable-targets=${TARGETARCH}${ADDITIONALTARGET} \ - --disable-werror --disable-nls --enable-lto --enable-gold \ + --disable-werror --disable-nls --enable-lto \ --enable-plugins --enable-multilibs CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index be72f81..8e38d1b 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -33,16 +33,16 @@ if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then else GITREV=Unknown TIMESOURCE="LANG=C LC_ALL=C TZ=UTC date" - DATE=$(date +%s) + DATE=$(gdate +%s) fi our_date() { case $(uname) in NetBSD|OpenBSD|DragonFly|FreeBSD) - date -r $1 $2 + gdate -r $1 $2 ;; *) - date -d @$1 $2 + gdate -d @$1 $2 esac }

1 0

Patch merged into coreboot/master: vboot: Don't count boot attempts if lid is closed
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit c88b8c24d9e357de64ecd3e863efb43f4be014bf Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jul 8 11:33:35 2015 +0200 vboot: Don't count boot attempts if lid is closed This can be a problem with freshly updated devices that are periodically powered on while closed (as explained in the bug report). In this case, just don't count down. In case of actual errors (where we want the system to fall back to the old code), this now means that the retries have to happen with the lid open. Bump vboot's submodule revision for the vboot-side support of this. BUG=chromium:446945 TEST=to test the OS update side, follow the test protocol in https://code.google.com/p/chromium/issues/detail?id=446945#c43 With a servo, it can be sped up using the EC console interface to start the closed system - no need to wait 60min and plugging in power to get to that state. Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10851 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10851 for details. -gerrit

1 0

Patch merged into coreboot/master: build system / amd64: Avoid GCC taking the ABI spec too literally
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit 668210966887a9d8e1dd7cb5df5103d11b46798a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jul 8 18:12:49 2015 +0200 build system / amd64: Avoid GCC taking the ABI spec too literally -mno-red-zone is an option that pretty much every barebone software package (eg. kernel, bootloader, ...) needs to use. We weren't hurt by it yet, but make sure we won't in the future. Change-Id: Ide5b63424ec1be5bf7bcade10540190b9871593b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10852 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10852 for details. -gerrit

1 0

New patch to review for coreboot: buildgcc: Show the archive URL
by Paul Menzel 08 Jul '15

08 Jul '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10853 -gerrit commit 1fdc9fced88e4653329078836562fd4d43df685b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jun 12 11:58:14 2015 +0200 buildgcc: Show the archive URL In case of downloading errors, the URL is handy for analyzing the cause. Change-Id: I6874cdc3c881cfdd52c80f80323536c30723654b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 7f440f7..f4a228e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -192,7 +192,7 @@ download() { "$($CHECKSUM tarballs/$FILE 2>/dev/null | \ sed -e 's,.*$[0-9a-f]\{40\}$.*,\1,')" ) && \ printf "(cached)" || ( - printf "(downloading)" + printf "(downloading from $archive)" rm -f tarballs/$FILE cd tarballs wget --no-check-certificate -q $archive

1 0

New patch to review for coreboot: build system / amd64: Avoid GCC taking the ABI spec too literally
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10852 -gerrit commit 9f44e93d0444f001ea56f3736a383d7f787ec723 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jul 8 18:12:49 2015 +0200 build system / amd64: Avoid GCC taking the ABI spec too literally -mno-red-zone is an option that pretty much every barebone software package (eg. kernel, bootloader, ...) needs to use. We weren't hurt by it yet, but make sure we won't in the future. Change-Id: Ide5b63424ec1be5bf7bcade10540190b9871593b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- toolchain.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index 3e28bb9..47e407f 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -72,7 +72,7 @@ CFLAGS_mips += -mno-abicalls -fno-pic CFLAGS_x86_32 += -ffunction-sections -fdata-sections CFLAGS_riscv += -ffunction-sections -fdata-sections -CFLAGS_x86_64 += -mcmodel=large +CFLAGS_x86_64 += -mcmodel=large -mno-red-zone toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\

1 0

Patch set updated for coreboot: intel/fsp_baytrail: Remove PcdEnableLan option
by York Yang 08 Jul '15

08 Jul '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10837 -gerrit commit 481247cf121059c91a7a91c2445c799bbcabd386 Author: York Yang <york.yang(a)intel.com> Date: Tue Jul 7 10:07:51 2015 -0700 intel/fsp_baytrail: Remove PcdEnableLan option Bay Trail SOCs do not integrate LAN controller hence Baytrail FSP has no LAN control function. Remove PcdEnableLan option from UPD_DATA_REGION structure. Change-Id: I9b4ec9d72c8c60b928a6d9755e94203fb90b658f Signed-off-by: York Yang <york.yang(a)intel.com> --- src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h old mode 100644 new mode 100755 index b001cdb..02de3cb --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2013-2015 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -67,7 +67,7 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableHsuart0; /* Offset 0x0029 */ UINT8 PcdEnableHsuart1; /* Offset 0x002A */ UINT8 PcdEnableSpi; /* Offset 0x002B */ - UINT8 PcdEnableLan; /* Offset 0x002C */ + UINT8 ReservedUpdSpace1; /* Offset 0x002C */ UINT8 PcdEnableSata; /* Offset 0x002D */ UINT8 PcdSataMode; /* Offset 0x002E */ UINT8 PcdEnableAzalia; /* Offset 0x002F */

1 0

Patch merged into filo/master: Fix Makefiles for mixed use Kconfig usage
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit 3e01efbc3071b7c4008551818ff7f7bfaf691e44 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jun 30 17:38:36 2015 -0700 Fix Makefiles for mixed use Kconfig usage Change-Id: Ibcf7051a6e0e4b17536a4f18bd3a632c7463aae1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10747 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10747 for details. -gerrit

1 0

Patch merged into filo/master: Rename Config.in to Kconfig
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit 0204cdddb4b7c6bd6ca69a9a63eb8df3addd13c7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jun 30 17:05:02 2015 -0700 Rename Config.in to Kconfig This is the standard name for all other Kconfig based projects surrounding coreboot. Let's adopt this in FILO, too. Change-Id: I6366468bd127485cc6f5fdbba216b55a593e062a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10746 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10746 for details. -gerrit

1 0

Patch set updated for coreboot: intel/fsp_baytrail: Support Baytrail FSP Gold4 release
by York Yang 08 Jul '15

08 Jul '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10838 -gerrit commit d02e48aa5b59a2e59f9d81e7618cd24c7b6fe1ef Author: York Yang <york.yang(a)intel.com> Date: Tue Jul 7 11:09:02 2015 -0700 intel/fsp_baytrail: Support Baytrail FSP Gold4 release Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION structure to include these new PCD options and initialized the setting when given in devicetree.cb. Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f Signed-off-by: York Yang <york.yang(a)intel.com> --- src/soc/intel/fsp_baytrail/chip.h | 34 +++++++++++++++++++++- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 7 ++++- .../intel/fsp1_0/baytrail/include/fspvpd.h | 7 ++++- 3 files changed, 45 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h old mode 100644 new mode 100755 index 57e2427..b69054d --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation + * Copyright (C) 2014-2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -189,6 +189,38 @@ struct soc_intel_fsp_baytrail_config { #define TXE_UMA_DISABLE UPD_DISABLE #define TXE_UMA_ENABLE UPD_ENABLE + /* + * PcdOsSelection + * Selection 0x1 , "Android" + * Selection 0x4 , "Linux OS" + */ + uint8_t PcdOsSelection; + #define OS_SELECTION_DEFAULT UPD_DEFAULT + #define OS_SELECTION_ANDROID INCREMENT_FOR_DEFAULT(1) + #define OS_SELECTION_LINUX INCREMENT_FOR_DEFAULT(4) + + /* PcdEMMC45DDR50Enabled */ + uint8_t PcdEMMC45DDR50Enabled; + #define EMMC45_DDR50_DEFAULT UPD_DEFAULT + #define EMMC45_DDR50_DISABLE UPD_DISABLE + #define EMMC45_DDR50_ENABLE UPD_ENABLE + + /* PcdEMMC45HS200Enabled */ + uint8_t PcdEMMC45HS200Enabled; + #define EMMC45_HS200_DEFAULT UPD_DEFAULT + #define EMMC45_HS200_DISABLE UPD_DISABLE + #define EMMC45_HS200_ENABLE UPD_ENABLE + + /* PcdEMMC45RetuneTimerValue */ + uint8_t PcdEMMC45RetuneTimerValue; + #define EMMC45_RETURN_TIMER_DEFAULT UPD_DEFAULT + + /* PcdEnableIgd */ + uint8_t PcdEnableIgd; + #define ENABLE_IGD_DEFAULT UPD_DEFAULT + #define ENABLE_IGD_DISABLE UPD_DISABLE + #define ENABLE_IGD_ENABLE UPD_ENABLE + /* Memory down data */ uint8_t EnableMemoryDown; #define MEMORY_DOWN_DEFAULT UPD_DEFAULT diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c old mode 100644 new mode 100755 index 0abab98..ad85c5b --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation + * Copyright (C) 2014-2015 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -112,6 +112,11 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U UPD_DEFAULT_CHECK(PcdSccEnablePciMode); UPD_DEFAULT_CHECK(IgdRenderStandby); UPD_DEFAULT_CHECK(TxeUmaEnable); + UPD_DEFAULT_CHECK(PcdOsSelection); + UPD_DEFAULT_CHECK(PcdEMMC45DDR50Enabled); + UPD_DEFAULT_CHECK(PcdEMMC45HS200Enabled); + UPD_DEFAULT_CHECK(PcdEMMC45RetuneTimerValue); + UPD_DEFAULT_CHECK(PcdEnableIgd); if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) || (config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE)) diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h index 02de3cb..76f7ce7 100755 --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -97,7 +97,12 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSccEnablePciMode; /* Offset 0x004D */ UINT8 IgdRenderStandby; /* Offset 0x004E */ UINT8 TxeUmaEnable; /* Offset 0x004F */ - UINT8 UnusedUpdSpace1[160]; /* Offset 0x0050 */ + UINT8 PcdOsSelection; /* Offset 0x0050 */ + UINT8 PcdEMMC45DDR50Enabled; /* Offset 0x0051 */ + UINT8 PcdEMMC45HS200Enabled; /* Offset 0x0052 */ + UINT8 PcdEMMC45RetuneTimerValue; /* Offset 0x0053 */ + UINT8 PcdEnableIgd; /* Offset 0x0054 */ + UINT8 UnusedUpdSpace1[155]; /* Offset 0x0055 */ MEMORY_DOWN_DATA PcdMemoryParameters; /* Offset 0x00F0 */ UINT16 PcdRegionTerminator; /* Offset 0x0100 */ } UPD_DATA_REGION;

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2015