coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: ipq8064: enable timestamp collection
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10847 -gerrit commit 2fd0015e5234a477ca34726b847a3caea9a08463 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri Dec 12 17:54:27 2014 -0800 ipq8064: enable timestamp collection One kilobyte of SRAM needs to be allocated and the feature enabled. BRANCH=storm BUG=chrome-os-partner:34161 TEST=timer error messages do not show up in the coreboot log any more Change-Id: I1d5e5521bf9ae495d4f4f50ff017c846a8420719 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ffb9bfb0cdfab1391f8ae07669a2ab6b24d88dd7 Original-Change-Id: I60066672334db36f5e7adbef6794d7afd177d292 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235893 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/qualcomm/ipq806x/Kconfig | 1 + src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index ecc52e2..9a1e4f9 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -7,6 +7,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select BOOTBLOCK_CONSOLE select CHROMEOS_VBNV_FLASH + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING select GENERIC_GPIO_LIB diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 426d35b..cf417ba 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -34,8 +34,9 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K) VBOOT2_WORK(0x2A022000, 16K) PRERAM_CBMEM_CONSOLE(0x2A026000, 32K) + TIMESTAMP(0x2A02E000, 1K) -/* 0x2e400..0x3F000 67KB free */ +/* 0x2e400..0x3F000 67 KB free */ /* Keep the below area reserved at all times, it is used by various QCA components as shared data

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New patch to review for coreboot: cbfs: look for CBFS header in a predefined place
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10846 -gerrit commit ce26a6fcd586a724c54047e1809e8ff3572140e3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Dec 25 15:07:22 2014 -0800 cbfs: look for CBFS header in a predefined place This patch adds a facility to set the CBFS header offset. The offset value of zero means default. i.e. the CBFS initialization code still discovers the offset through the value saved at the top of the ROM. [pg: stripped to cover only the CBFS_HEADER_OFFSET memory region since CBFS diverged too much and will be worked on further in short order.] Change-Id: I9f2ca1842b479ea4371cfcce02bce7dd28e77ce2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e57a3a15bba7cdcca4a5d684ed78f8ac6dbbc95e Original-Change-Id: I4c026389ec4fbaa19bd11b2160202282d2f9283c Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/237569 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memlayout.h | 2 ++ src/include/symbols.h | 1 + 2 files changed, 3 insertions(+) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..caae25a 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -105,4 +105,6 @@ . += sz; #endif +#define CBFS_HEADER_OFFSET(addr) REGION(cbfs_header_offset, addr, 4, 4) + #endif /* __MEMLAYOUT_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index 3fbf819..5f59f33 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -27,6 +27,7 @@ extern u8 _esram[]; #define _sram_size (_esram - _sram) extern u8 _dram[]; +extern u32 _cbfs_header_offset[]; extern u8 _timestamp[]; extern u8 _etimestamp[];

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New patch to review for coreboot: libpayload: Add LZ4 decompression algorithm
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10845 -gerrit commit bde3501271794820525aafafb895bdb042cadda4 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Jun 30 10:30:30 2015 -0700 libpayload: Add LZ4 decompression algorithm This patch adds support for the LZ4 decompression algorithm to libpayload. It's what all the cool kids are using for decompression these days and has many interesting advantages over LZMA (and everything else I know of): blazing fast decompression (20(!) times faster than LZMA, twice as fast as LZO on my Cortex-A72), no memory requirements on decompression, and possibly in-place decompression support. It pays for that with a lower compression ratio (about 50% larger compressed size than LZMA, 10% larger than LZO for an ARM64 Linux kernel binary), but the boot time math still works in its favor for our IO speeds. This patch only adds the raw decompression functions for use by external payloads, we can later try integrating them in CBFS. It copies the decompression code itself unmodified from the upstream LZ4 library at github.com/Cyan4973/lz4 which will hopefully make it easy to update. The frame format parsing is reimplemented since the upstream version looks unnecessarily complex and unreadable for our needs. BRANCH=smaug BUG=chrome-os-partner:32184 TEST=With other patches, booted ARM64 kernel that got compressed from 15M to 5.1M and decompresses in 44ms. Change-Id: I65bdc4b2b19bd51c7b7e17a4e4b79da301a2a014 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f8a1fc996d5b0234d07f567fa8163d0f802d5144 Original-Change-Id: I15c0620da05561ade2552b15ffdf6bb3afd7eb26 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282743 Original-Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/Kconfig | 7 + payloads/libpayload/LICENSES | 4 + payloads/libpayload/Makefile.inc | 2 + payloads/libpayload/include/lz4.h | 47 ++++++ payloads/libpayload/liblz4/Makefile.inc | 28 ++++ payloads/libpayload/liblz4/lz4.c | 266 +++++++++++++++++++++++++++++++ payloads/libpayload/liblz4/lz4_wrapper.c | 158 ++++++++++++++++++ 7 files changed, 512 insertions(+) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index dee970c..5da4f92 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -172,6 +172,13 @@ config LZMA help LZMA decoder implementation, usable eg. by CBFS, but also externally. + +config LZ4 + bool "LZ4 decoder" + default y + help + Decoder implementation for the LZ4 compression algorithm. + Adds standalone functions (CBFS support coming soon). endmenu menu "Console Options" diff --git a/payloads/libpayload/LICENSES b/payloads/libpayload/LICENSES index f340ead..ab8daa4 100644 --- a/payloads/libpayload/LICENSES +++ b/payloads/libpayload/LICENSES @@ -131,3 +131,7 @@ holders, and the exact license terms that apply. Source: GNU C Library (glibc), http://www.gnu.org/software/libc/libc.html Original files: sysdeps/i386/memset.c Current version we use: 2.14 + +* liblz4/lz4.c: 2-clause BSD + Source: LZ4 library, https://github.com/Cyan4973/lz4 + Current version we use: r130 (baf78e7e4dcbdf824a76f990ffeb573d113bbbdb) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index c8a49fc..b84e322 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -45,6 +45,7 @@ classes-$(CONFIG_LP_CURSES) += libcurses classes-$(CONFIG_LP_PDCURSES) += libmenu libform libpanel classes-$(CONFIG_LP_CBFS) += libcbfs classes-$(CONFIG_LP_LZMA) += liblzma +classes-$(CONFIG_LP_LZ4) += liblz4 classes-$(CONFIG_LP_REMOTEGDB) += libgdb libraries := $(classes-y) classes-y += head.o @@ -54,6 +55,7 @@ subdirs-y += crypto libc drivers libpci gdb subdirs-$(CONFIG_LP_CURSES) += curses subdirs-$(CONFIG_LP_CBFS) += libcbfs subdirs-$(CONFIG_LP_LZMA) += liblzma +subdirs-$(CONFIG_LP_LZ4) += liblz4 INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h diff --git a/payloads/libpayload/include/lz4.h b/payloads/libpayload/include/lz4.h new file mode 100644 index 0000000..1f2830d --- /dev/null +++ b/payloads/libpayload/include/lz4.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __LZ4_H_ +#define __LZ4_H_ + +#include <stddef.h> + +/* Decompresses an LZ4F image (multiple LZ4 blocks with frame header) from src + * to dst, ensuring that it doesn't read more than srcn bytes and doesn't write + * more than dstn. Buffer sizes must stay below 2GB. + * Returns amount of decompressed bytes, or 0 on error. + */ +size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn); + +/* Same as ulz4fn() but does not perform any bounds checks. */ +size_t ulz4f(const void *src, void *dst); + +#endif /* __LZO_H_ */ diff --git a/payloads/libpayload/liblz4/Makefile.inc b/payloads/libpayload/liblz4/Makefile.inc new file mode 100644 index 0000000..272a5a5 --- /dev/null +++ b/payloads/libpayload/liblz4/Makefile.inc @@ -0,0 +1,28 @@ +## +## Copyright 2015 Google Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +liblz4-$(CONFIG_LP_LZ4) += lz4_wrapper.c diff --git a/payloads/libpayload/liblz4/lz4.c b/payloads/libpayload/liblz4/lz4.c new file mode 100644 index 0000000..fb89090 --- /dev/null +++ b/payloads/libpayload/liblz4/lz4.c @@ -0,0 +1,266 @@ +/* + LZ4 - Fast LZ compression algorithm + Copyright (C) 2011-2015, Yann Collet. + + BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following disclaimer + in the documentation and/or other materials provided with the + distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + You can contact the author at : + - LZ4 source repository : https://github.com/Cyan4973/lz4 + - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c +*/ + + +/************************************** +* Reading and writing into memory +**************************************/ + +/* customized version of memcpy, which may overwrite up to 7 bytes beyond dstEnd */ +static void LZ4_wildCopy(void* dstPtr, const void* srcPtr, void* dstEnd) +{ + BYTE* d = (BYTE*)dstPtr; + const BYTE* s = (const BYTE*)srcPtr; + BYTE* e = (BYTE*)dstEnd; + do { LZ4_copy8(d,s); d+=8; s+=8; } while (d<e); +} + + +/************************************** +* Common Constants +**************************************/ +#define MINMATCH 4 + +#define COPYLENGTH 8 +#define LASTLITERALS 5 +#define MFLIMIT (COPYLENGTH+MINMATCH) +static const int LZ4_minLength = (MFLIMIT+1); + +#define KB *(1 <<10) +#define MB *(1 <<20) +#define GB *(1U<<30) + +#define MAXD_LOG 16 +#define MAX_DISTANCE ((1 << MAXD_LOG) - 1) + +#define ML_BITS 4 +#define ML_MASK ((1U<<ML_BITS)-1) +#define RUN_BITS (8-ML_BITS) +#define RUN_MASK ((1U<<RUN_BITS)-1) + + +/************************************** +* Local Structures and types +**************************************/ +typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive; +typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive; +typedef enum { full = 0, partial = 1 } earlyEnd_directive; + + + +/******************************* +* Decompression functions +*******************************/ +/* + * This generic decompression function cover all use cases. + * It shall be instantiated several times, using different sets of directives + * Note that it is essential this generic function is really inlined, + * in order to remove useless branches during compilation optimization. + */ +FORCE_INLINE int LZ4_decompress_generic( + const char* const source, + char* const dest, + int inputSize, + int outputSize, /* If endOnInput==endOnInputSize, this value is the max size of Output Buffer. */ + + int endOnInput, /* endOnOutputSize, endOnInputSize */ + int partialDecoding, /* full, partial */ + int targetOutputSize, /* only used if partialDecoding==partial */ + int dict, /* noDict, withPrefix64k, usingExtDict */ + const BYTE* const lowPrefix, /* == dest if dict == noDict */ + const BYTE* const dictStart, /* only if dict==usingExtDict */ + const size_t dictSize /* note : = 0 if noDict */ + ) +{ + /* Local Variables */ + const BYTE* ip = (const BYTE*) source; + const BYTE* const iend = ip + inputSize; + + BYTE* op = (BYTE*) dest; + BYTE* const oend = op + outputSize; + BYTE* cpy; + BYTE* oexit = op + targetOutputSize; + const BYTE* const lowLimit = lowPrefix - dictSize; + + const BYTE* const dictEnd = (const BYTE*)dictStart + dictSize; + const size_t dec32table[] = {4, 1, 2, 1, 4, 4, 4, 4}; + const size_t dec64table[] = {0, 0, 0, (size_t)-1, 0, 1, 2, 3}; + + const int safeDecode = (endOnInput==endOnInputSize); + const int checkOffset = ((safeDecode) && (dictSize < (int)(64 KB))); + + + /* Special cases */ + if ((partialDecoding) && (oexit> oend-MFLIMIT)) oexit = oend-MFLIMIT; /* targetOutputSize too high => decode everything */ + if ((endOnInput) && (unlikely(outputSize==0))) return ((inputSize==1) && (*ip==0)) ? 0 : -1; /* Empty output buffer */ + if ((!endOnInput) && (unlikely(outputSize==0))) return (*ip==0?1:-1); + + + /* Main Loop */ + while (1) + { + unsigned token; + size_t length; + const BYTE* match; + + /* get literal length */ + token = *ip++; + if ((length=(token>>ML_BITS)) == RUN_MASK) + { + unsigned s; + do + { + s = *ip++; + length += s; + } + while (likely((endOnInput)?ip<iend-RUN_MASK:1) && (s==255)); + if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)(op))) goto _output_error; /* overflow detection */ + if ((safeDecode) && unlikely((size_t)(ip+length)<(size_t)(ip))) goto _output_error; /* overflow detection */ + } + + /* copy literals */ + cpy = op+length; + if (((endOnInput) && ((cpy>(partialDecoding?oexit:oend-MFLIMIT)) || (ip+length>iend-(2+1+LASTLITERALS))) ) + || ((!endOnInput) && (cpy>oend-COPYLENGTH))) + { + if (partialDecoding) + { + if (cpy > oend) goto _output_error; /* Error : write attempt beyond end of output buffer */ + if ((endOnInput) && (ip+length > iend)) goto _output_error; /* Error : read attempt beyond end of input buffer */ + } + else + { + if ((!endOnInput) && (cpy != oend)) goto _output_error; /* Error : block decoding must stop exactly there */ + if ((endOnInput) && ((ip+length != iend) || (cpy > oend))) goto _output_error; /* Error : input must be consumed */ + } + memcpy(op, ip, length); + ip += length; + op += length; + break; /* Necessarily EOF, due to parsing restrictions */ + } + LZ4_wildCopy(op, ip, cpy); + ip += length; op = cpy; + + /* get offset */ + match = cpy - LZ4_readLE16(ip); ip+=2; + if ((checkOffset) && (unlikely(match < lowLimit))) goto _output_error; /* Error : offset outside destination buffer */ + + /* get matchlength */ + length = token & ML_MASK; + if (length == ML_MASK) + { + unsigned s; + do + { + if ((endOnInput) && (ip > iend-LASTLITERALS)) goto _output_error; + s = *ip++; + length += s; + } while (s==255); + if ((safeDecode) && unlikely((size_t)(op+length)<(size_t)op)) goto _output_error; /* overflow detection */ + } + length += MINMATCH; + + /* check external dictionary */ + if ((dict==usingExtDict) && (match < lowPrefix)) + { + if (unlikely(op+length > oend-LASTLITERALS)) goto _output_error; /* doesn't respect parsing restriction */ + + if (length <= (size_t)(lowPrefix-match)) + { + /* match can be copied as a single segment from external dictionary */ + match = dictEnd - (lowPrefix-match); + memmove(op, match, length); op += length; + } + else + { + /* match encompass external dictionary and current segment */ + size_t copySize = (size_t)(lowPrefix-match); + memcpy(op, dictEnd - copySize, copySize); + op += copySize; + copySize = length - copySize; + if (copySize > (size_t)(op-lowPrefix)) /* overlap within current segment */ + { + BYTE* const endOfMatch = op + copySize; + const BYTE* copyFrom = lowPrefix; + while (op < endOfMatch) *op++ = *copyFrom++; + } + else + { + memcpy(op, lowPrefix, copySize); + op += copySize; + } + } + continue; + } + + /* copy repeated sequence */ + cpy = op + length; + if (unlikely((op-match)<8)) + { + const size_t dec64 = dec64table[op-match]; + op[0] = match[0]; + op[1] = match[1]; + op[2] = match[2]; + op[3] = match[3]; + match += dec32table[op-match]; + LZ4_copy4(op+4, match); + op += 8; match -= dec64; + } else { LZ4_copy8(op, match); op+=8; match+=8; } + + if (unlikely(cpy>oend-12)) + { + if (cpy > oend-LASTLITERALS) goto _output_error; /* Error : last LASTLITERALS bytes must be literals */ + if (op < oend-8) + { + LZ4_wildCopy(op, match, oend-8); + match += (oend-8) - op; + op = oend-8; + } + while (op<cpy) *op++ = *match++; + } + else + LZ4_wildCopy(op, match, cpy); + op=cpy; /* correction */ + } + + /* end of decoding */ + if (endOnInput) + return (int) (((char*)op)-dest); /* Nb of output bytes decoded */ + else + return (int) (((const char*)ip)-source); /* Nb of input bytes read */ + + /* Overflow error detected */ +_output_error: + return (int) (-(((const char*)ip)-source))-1; +} diff --git a/payloads/libpayload/liblz4/lz4_wrapper.c b/payloads/libpayload/liblz4/lz4_wrapper.c new file mode 100644 index 0000000..b046597 --- /dev/null +++ b/payloads/libpayload/liblz4/lz4_wrapper.c @@ -0,0 +1,158 @@ +/* + * Copyright 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <assert.h> +#include <endian.h> +#include <libpayload.h> +#include <lz4.h> + +/* LZ4 comes with its own supposedly portable memory access functions, but they + * seem to be very inefficient in practice (at least on ARM64). Since libpayload + * knows about endinaness and allows some basic assumptions (such as unaligned + * access support), we can easily write the ones we need ourselves. */ +static u16 LZ4_readLE16(const void *src) { return le16toh(*(u16 *)src); } +static void LZ4_copy4(void *dst, const void *src) { *(u32 *)dst = *(u32 *)src; } +static void LZ4_copy8(void *dst, const void *src) { *(u64 *)dst = *(u64 *)src; } + +typedef uint8_t BYTE; +typedef uint16_t U16; +typedef uint32_t U32; +typedef int32_t S32; +typedef uint64_t U64; + +#define FORCE_INLINE static inline __attribute__((always_inline)) +#define likely(expr) __builtin_expect((expr) != 0, 1) +#define unlikely(expr) __builtin_expect((expr) != 0, 0) + +/* Unaltered (except removing unrelated code) from github.com/Cyan4973/lz4. */ +#include "lz4.c" /* #include for inlining, do not link! */ + +#define LZ4F_MAGICNUMBER 0x184D2204 + +struct lz4_frame_header { + u32 magic; + union { + u8 flags; + struct { + u8 reserved0 : 2; + u8 has_content_checksum : 1; + u8 has_content_size : 1; + u8 has_block_checksum : 1; + u8 independent_blocks : 1; + u8 version : 2; + }; + }; + union { + u8 block_descriptor; + struct { + u8 reserved1 : 4; + u8 max_block_size : 3; + u8 reserved2 : 1; + }; + }; + /* + u64 content_size iff has_content_size is set */ + /* + u8 header_checksum */ +} __attribute__((packed)); + +struct lz4_block_header { + union { + u32 raw; + struct { + u32 size : 31; + u32 not_compressed : 1; + }; + }; + /* + size bytes of data */ + /* + u32 block_checksum iff has_block_checksum is set */ +} __attribute__((packed)); + +size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) +{ + const void *in = src; + void *out = dst; + int has_block_checksum; + + { /* With in-place decompression the header may become invalid later. */ + const struct lz4_frame_header *h = in; + + if (srcn < sizeof(*h) + sizeof(u64) + sizeof(u8)) + return 0; /* input overrun */ + + /* We assume there's always only a single, standard frame. */ + if (le32toh(h->magic) != LZ4F_MAGICNUMBER || h->version != 1) + return 0; /* unknown format */ + if (h->reserved0 || h->reserved1 || h->reserved2) + return 0; /* reserved must be zero */ + if (!h->independent_blocks) + return 0; /* we don't support block dependency */ + has_block_checksum = h->has_block_checksum; + + in += sizeof(*h); + if (h->has_content_size) + in += sizeof(u64); + in += sizeof(u8); + } + + while (1) { + struct lz4_block_header b = { .raw = le32toh(*(u32 *)in) }; + in += sizeof(struct lz4_block_header); + + if (in - src + b.size > srcn) + return 0; /* input overrun */ + + if (!b.size) + return out - dst; /* decompression successful */ + + if (b.not_compressed) { + memcpy(out, in, b.size); + out += b.size; + } else { + /* constant folding essential, do not touch params! */ + int ret = LZ4_decompress_generic(in, out, b.size, + dst + dstn - out, endOnInputSize, + full, 0, noDict, out, NULL, 0); + if (ret < 0) + return 0; /* decompression error */ + else + out += ret; + } + + in += b.size; + if (has_block_checksum) + in += sizeof(u32); + } +} + +size_t ulz4f(const void *src, void *dst) +{ + /* LZ4 uses signed size parameters, so can't just use ((u32)-1) here. */ + return ulz4fn(src, 1*GiB, dst, 1*GiB); +}

1 0

New patch to review for coreboot: veyron_{brain, danger, mickey, romy}: Select PHYSICAL_REC_SWITCH
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10844 -gerrit commit 27575f26bf6f04641a4153ee2469eebb19c60600 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jul 6 16:52:11 2015 -0700 veyron_{brain,danger,mickey,romy}: Select PHYSICAL_REC_SWITCH BUG=chrome-os-partner:42220 BRANCH=veyron TEST=Used physical recovery button to enter dev mode on mickey Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283546 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_brain/Kconfig | 1 + src/mainboard/google/veyron_danger/Kconfig | 1 + src/mainboard/google/veyron_mickey/Kconfig | 1 + src/mainboard/google/veyron_romy/Kconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index ca5d0fc..e76496b 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select PHYSICAL_REC_SWITCH select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 562f281..e2128eb 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select PHYSICAL_REC_SWITCH select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index d40cbae..9233a91 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select PHYSICAL_REC_SWITCH select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index c15e29f..b7f05d7 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select PHYSICAL_REC_SWITCH select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH

1 0

New patch to review for coreboot: smaug: Update PMIC settings
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10843 -gerrit commit 1e6e432f5b510d77b052a9e5afa6f03b892fca88 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 6 13:40:50 2015 -0700 smaug: Update PMIC settings Update PMIC settings as per table provided by hardware eng team. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283543 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/smaug/pmic.c | 37 +++++++++++++++++++++---------------- src/mainboard/google/smaug/pmic.h | 3 +++ 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index 17d65e5..73aa0de 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -84,29 +84,34 @@ void pmic_init(unsigned bus) /* Restore PMIC POR defaults, in case kernel changed 'em */ pmic_slam_defaults(bus); - /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ - pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1); - - /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */ - pmic_write_reg_77620(bus, MAX77620_GPIO1_REG, 0x09, 1); + /* MAX77620: Set SD0 to 1.0V - VDD_CORE */ + pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1); + pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1); - /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ - pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x1c, 1); + /* MAX77620: GPIO 0,1,2,5,6,7 = GPIO, 3,4 = alt mode */ + pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x18, 1); - /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */ + /* MAX77620: Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125V */ pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1); - pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1); - /* Max77621 VREG for CPU needs to be set to 0.85V as per SysEng */ + /* MAX77621: Set VOUT_REG to 1.0V - CPU VREG */ + pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xBF, 1); + + /* MAX77621: Set VOUT_DVC_REG to 1.0V - CPU VREG DVC */ + pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xBF, 1); - /* Max77621 CPU VREG, register 0, 0.85V = 0x27(0.60625 + (39*6.25mV)) */ - pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0x27, 1); - pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xa7, 1); + /* MAX77621: Set CONTROL1 to 0x38 */ + pmic_write_reg_77621(bus, MAX77621_CONTROL1_REG, 0x38, 1); + + /* MAX77621: Set CONTROL2 to 0xD2 */ + pmic_write_reg_77621(bus, MAX77621_CONTROL2_REG, 0xD2, 1); + + /* MAX77620: Setup/Enable GPIO5 - EN_VDD_CPU */ + pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1); - /* Max77621 CPU VREG DVC, register 1, 0.85V = 0x27 */ - pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0x27, 1); - pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xa7, 1); + /* Required delay of 2msec */ + udelay(2000); printk(BIOS_DEBUG, "PMIC init done\n"); } diff --git a/src/mainboard/google/smaug/pmic.h b/src/mainboard/google/smaug/pmic.h index d38b328..4cdae42 100644 --- a/src/mainboard/google/smaug/pmic.h +++ b/src/mainboard/google/smaug/pmic.h @@ -25,6 +25,7 @@ #define MAX77620_SD1_REG 0x17 #define MAX77620_SD2_REG 0x18 #define MAX77620_SD3_REG 0x19 +#define MAX77620_VDVSSD0_REG 0x1B #define MAX77620_CNFG2SD_REG 0x22 #define MAX77620_CNFG1_L0_REG 0x23 @@ -71,6 +72,8 @@ #define MAX77621_VOUT_REG 0x00 #define MAX77621_VOUT_DVC_REG 0x01 +#define MAX77621_CONTROL1_REG 0x02 +#define MAX77621_CONTROL2_REG 0x03 void pmic_init(unsigned bus); void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val,

1 0

New patch to review for coreboot: arm64: Print sp value when dumping registers for exception
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10842 -gerrit commit 054ad6eb7032a30eb2158a95ff8819b2b31b1c2d Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 6 13:13:32 2015 -0700 arm64: Print sp value when dumping registers for exception BUG=None BRANCH=None TEST=Compiles successfully, sp verified during exception Change-Id: Idbeb93b1dbf163e2d86cd42369941ff98a3d2d9e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ca73b40f0248497143b6ab42bd0f5cc6cddf7713 Original-Change-Id: I38ee403200acb0e3d9015231c274568930b58987 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283542 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/arm64/armv8/exception.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index a633e3a..afbaf6d 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -68,6 +68,7 @@ static void print_regs(struct exc_state *exc_state) printk(BIOS_DEBUG, "ESR = 0x%016llx\n", elx_esr); printk(BIOS_DEBUG, "SPSR = 0x%08llx\n", elx->spsr); printk(BIOS_DEBUG, "FAR = 0x%016llx\n", elx_far); + printk(BIOS_DEBUG, "SP = 0x%016llx\n", regs->sp); for (i = X0_INDEX; i < XMAX_INDEX; i++) printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, regs->x[i]); }

1 0

New patch to review for coreboot: t210: set CAR2PMC_CPU_ACK_WIDTH to 0
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10841 -gerrit commit 48a571063c6f702e9c5a5b1542e89908e7590949 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed May 6 13:56:50 2015 -0700 t210: set CAR2PMC_CPU_ACK_WIDTH to 0 HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/ccplex.c | 17 +++++++++++++++++ src/soc/nvidia/tegra210/include/soc/clk_rst.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c index f3c61cb..a3c6722 100644 --- a/src/soc/nvidia/tegra210/ccplex.c +++ b/src/soc/nvidia/tegra210/ccplex.c @@ -92,9 +92,26 @@ static void request_ram_repair(void) stopwatch_duration_usecs(&sw)); } +static void set_cpu_ack_width(uint32_t val) +{ + uint32_t reg; + + reg = read32(CLK_RST_REG(cpu_softrst_ctrl2)); + reg &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; + reg |= val; + write32(CLK_RST_REG(cpu_softrst_ctrl2), reg); +} + void ccplex_cpu_prepare(void) { enable_cpu_clocks(); + + /* + * The POR value of CAR2PMC_CPU_ACK_WIDTH is 0x200. + * The recommended value is 0. + */ + set_cpu_ack_width(0); + enable_cpu_power_partitions(); mainboard_configure_pmc(); diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h index 817a041..87790d5 100644 --- a/src/soc/nvidia/tegra210/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -534,6 +534,9 @@ enum { #define PCLK_DIVISOR_SHIFT 0 #define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +/* CPU_SOFTRST_CTRL2_0 0x388 */ +#define CAR2PMC_CPU_ACK_WIDTH_MASK 0xfff + /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29)

1 0

New patch to review for coreboot: t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to work
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10840 -gerrit commit 29dc9d6e7a2b070f9aa114c29dd97bc4a3c6ac85 Author: Yen Lin <yelin(a)nvidia.com> Date: Fri May 29 14:36:19 2015 -0700 t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to work I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/i2c6.c | 3 +++ src/soc/nvidia/tegra210/include/soc/clock.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c index 915a538..9213057 100644 --- a/src/soc/nvidia/tegra210/i2c6.c +++ b/src/soc/nvidia/tegra210/i2c6.c @@ -65,6 +65,9 @@ void soc_configure_i2c6pad(void) */ soc_configure_host1x(); + /* enable SOR_SAFE and DPAUX_1 clocks */ + clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE); + /* Now we can write the I2C6 mux in DPAUX */ write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); /* Finally, power up the pads */ diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index ff9b282..8564c83 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -158,7 +158,9 @@ enum { CLK_X_SPARE = 0x1 << 0, CLK_Y_APE = 0x1 << 6, + CLK_Y_DPAUX1 = 0x1 << 15, CLK_Y_QSPI = 0x1 << 19, + CLK_Y_SOR_SAFE = 0x1 << 30, }; enum {

1 0

New patch to review for coreboot: veyron_danger: Enable developer mode switch
by Patrick Georgi 08 Jul '15

08 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10839 -gerrit commit 69b7244b06af3f18efa0ee3a3454d2c6ccdc58c3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 3 16:40:16 2015 -0700 veyron_danger: Enable developer mode switch Danger has a physical developer mode switch, it was just never set up. This patch defines it, sets it up in fill_lb_gpios(), and disables VIRTUAL_DEV_SWITCH. Note: For now at least, dev mode is a bit wonky on Danger. It's connected to both a DIP switch and a button. The button is normally open, pulling dev mode high (defaulting to ON). The switch's "ON" position will pull the value low, so we invert the value in coreboot to see the expected behavior. Dev mode is enabled by holding the button down during boot or by setting switch 2 in the DIP bank to the ON position. BUG=none BRANCH=none TEST=toggled dev switch on Danger and saw dev screen show up (or not) as expected Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318 Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280852 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_danger/Kconfig | 1 - src/mainboard/google/veyron_danger/chromeos.c | 10 ++++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index 5a41690..562f281 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND - select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string diff --git a/src/mainboard/google/veyron_danger/chromeos.c b/src/mainboard/google/veyron_danger/chromeos.c index 7eed42e..62bc1a4 100644 --- a/src/mainboard/google/veyron_danger/chromeos.c +++ b/src/mainboard/google/veyron_danger/chromeos.c @@ -28,11 +28,13 @@ #define GPIO_WP GPIO(7, A, 6) #define GPIO_POWER GPIO(0, A, 5) #define GPIO_RECOVERY GPIO(0, B, 1) +#define GPIO_DEV_MODE GPIO(7, B, 2) void setup_chromeos_gpios(void) { gpio_input(GPIO_WP); gpio_input(GPIO_POWER); + gpio_input(GPIO_DEV_MODE); gpio_input_pullup(GPIO_RECOVERY); } @@ -64,9 +66,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; - /* Developer: GPIO active high */ - gpios->gpios[count].port = -1; - gpios->gpios[count].polarity = ACTIVE_HIGH; + /* Developer: Danger has a physical dev switch that is active low */ + gpios->gpios[count].port = GPIO_DEV_MODE.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; gpios->gpios[count].value = get_developer_mode_switch(); strncpy((char *)gpios->gpios[count].name, "developer", GPIO_MAX_NAME_LENGTH); @@ -88,7 +90,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - return 0; + return !gpio_get(GPIO_DEV_MODE); } int get_recovery_mode_switch(void)

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Patch merged into coreboot/master: toolchain.inc: Don't overwrite architecture specific CFLAGS
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit 2941b28080fff82503484a99c3fa740a01bb30cc Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 7 23:37:11 2015 +0200 toolchain.inc: Don't overwrite architecture specific CFLAGS For almost all platforms the CFLAGS_<arch> specified in .xcompile were overwritten by toolchain.inc, effectively breaking the build in different places and in subtle ways. Change-Id: I8e1db0eee7ca417ec56ed2156ae1b0b318e57e81 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10831 for details. -gerrit

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coreboot-gerrit July 2015