the following patch was just integrated into master:
commit d05a6c80c7fd6e94e172b463467e449364943f3e
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Jul 7 15:17:05 2015 -0700
vendorcode/intel/edk2: Fix EFI_PEI_GRAPHICS_INFO_HOB structure
Change the FrameBufferSize field from UINT64 to UINT32 to match the
Platform Initialization 2.4 specification.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I28dc0608675ed5840863ecd15bd2f57e6b2f4c1d
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: http://review.coreboot.org/10834
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/10834 for details.
-gerrit
the following patch was just integrated into master:
commit 45980bd9f74206947c68a43042131fdffb97591e
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Jul 7 15:21:21 2015 -0700
Braswell: Fix error in the warranty statement
Fix a cut and paste error in the warranty statement.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: If64b02f2c0fc2970932f23b99ad64beab5ab754e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
Reviewed-on: http://review.coreboot.org/10835
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>
See http://review.coreboot.org/10835 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10851
-gerrit
commit d090266fd86023020f7bf340033bc70233dcda11
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Jul 8 11:33:35 2015 +0200
vboot: Don't count boot attempts if lid is closed
This can be a problem with freshly updated devices that are periodically
powered on while closed (as explained in the bug report).
In this case, just don't count down. In case of actual errors (where we
want the system to fall back to the old code), this now means that the
retries have to happen with the lid open.
Bump vboot's submodule revision for the vboot-side support of this.
BUG=chromium:446945
TEST=to test the OS update side, follow the test protocol in
https://code.google.com/p/chromium/issues/detail?id=446945#c43
With a servo, it can be sped up using the EC console interface to start
the closed system - no need to wait 60min and plugging in power to get
to that state.
Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
3rdparty/vboot | 2 +-
src/vendorcode/google/chromeos/vboot2/verstage.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 7dd3bd0..fbf631c 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 7dd3bd0fcf565901aacc512cd29cefe19291c2e7
+Subproject commit fbf631c845c08299f0bcbae3f311c5807d34c0d6
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 783d1b6..2a2a956 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -270,6 +270,9 @@ void verstage_main(void)
if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+ if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+ ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
/* Do early init (set up secdata and NVRAM, load GBB) */
printk(BIOS_INFO, "Phase 1\n");
rv = vb2api_fw_phase1(&ctx);
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10851
-gerrit
commit 0686105b62a53bfd8d541362046cd35c95f1ad61
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Jul 8 11:33:35 2015 +0200
vboot: Don't count boot attempts if lid is closed
This can be a problem with freshly updated devices that are periodically
powered on while closed (as explained in the bug report).
In this case, just don't count down. In case of actual errors (where we
want the system to fall back to the old code), this now means that the
retries have to happen with the lid open.
BUG=chromium:446945
TEST=to test the OS update side, follow the test protocol in
https://code.google.com/p/chromium/issues/detail?id=446945#c43
With a servo, it can be sped up using the EC console interface to start
the closed system - no need to wait 60min and plugging in power to get
to that state.
Change-Id: I0e39aadc52195fe53ee4a29a828ed9a40d28f5e6
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
3rdparty/vboot | 2 +-
src/vendorcode/google/chromeos/vboot2/verstage.c | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 7dd3bd0..fbf631c 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 7dd3bd0fcf565901aacc512cd29cefe19291c2e7
+Subproject commit fbf631c845c08299f0bcbae3f311c5807d34c0d6
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 783d1b6..2a2a956 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -270,6 +270,9 @@ void verstage_main(void)
if (IS_ENABLED(CONFIG_WIPEOUT_SUPPORTED) && get_wipeout_mode_switch())
ctx.flags |= VB2_CONTEXT_FORCE_WIPEOUT_MODE;
+ if (IS_ENABLED(CONFIG_LID_SWITCH) && !get_lid_switch())
+ ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT;
+
/* Do early init (set up secdata and NVRAM, load GBB) */
printk(BIOS_INFO, "Phase 1\n");
rv = vb2api_fw_phase1(&ctx);
the following patch was just integrated into master:
commit 838c88f1b75f9bd5a0c439d2ef75139fe6ee4d6b
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Mon Jul 6 09:12:42 2015 +0000
libpayload: update defconfigs
That way they don't need an initial 'make oldconfig' pass to
be useful again.
Change-Id: I3724fffab24b69478b8077f34e9d787555fd157b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/10805
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10805 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10850
-gerrit
commit cefb7744c63ee95e42e15d76de079dcb46aa155a
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Wed Jul 1 10:37:04 2015 -0700
cbfs: make size for CBFS_HEADER_OFFSET explicit
It's currently not visible in memlayout.ld how much space is
allocated for CBFS_HEADER_OFFSET, thus, it cannot be validated whether
the field following it has the right address and size. This change makes
CBFS_HEADER_OFFSET macro take size argument explicitly, which also makes
it consistent with other fields with a fixed size.
BUG=none
BRANCH=tot
TEST=built storm
Change-Id: Ifedc21abf4c41038a6021f221d924400d9ef41d6
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f30577fc8f8cb24ec83868ecbbea1fe9b2ff4a71
Original-Change-Id: I61bfb53b5604661504bbe8af3f8bb8310b543d14
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283062
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/memlayout.h | 6 +++++-
src/soc/broadcom/cygnus/include/soc/memlayout.ld | 2 +-
src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 2 +-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index caae25a..0eab785 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -105,6 +105,10 @@
. += sz;
#endif
-#define CBFS_HEADER_OFFSET(addr) REGION(cbfs_header_offset, addr, 4, 4)
+/* space used to store cbfs header offset, which is 4 bytes */
+#define CBFS_HEADER_OFFSET(addr, sz) \
+ REGION(cbfs_header_offset, addr, sz, 4) \
+ _ = ASSERT(sz == 4, \
+ STR(cbfs_header_offset must be exactly 4 bytes (sz)));
#endif /* __MEMLAYOUT_H */
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
index bd3621a..e1d30e8 100644
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
@@ -35,7 +35,7 @@ SECTIONS
OVERLAP_VERSTAGE_ROMSTAGE(0x02014000, 120K)
PRERAM_CBFS_CACHE(0x02032000, 1K)
TIMESTAMP(0x02032400, 1K)
- CBFS_HEADER_OFFSET(0x02032800)
+ CBFS_HEADER_OFFSET(0x02032800, 4)
STACK(0x02033000, 12K)
REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4)
SRAM_END(0x02040000)
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index c66d0c8..c74d580 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -35,7 +35,7 @@ SECTIONS
VBOOT2_WORK(0x2A022000, 16K)
PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
TIMESTAMP(0x2A02E000, 1K)
- CBFS_HEADER_OFFSET(0x2A02E400)
+ CBFS_HEADER_OFFSET(0x2A02E400, 4)
/* 0x2e404..0x3F000 4 bytes shy of 67KB free */
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10848
-gerrit
commit 2c72c9d1b6b97443583745189c8060f85c17596b
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Thu Dec 25 15:16:25 2014 -0800
storm: define location for storing CBFS header value
The 4 byte offset value will be stored in SRAM and shared between
different coreboot stages.
Change-Id: If321403b389e8bfd074b0ff7d6ef7e3c9397262a
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 8f2f7cf6263f4c2db70b1c87ec67f6b0308059b3
Original-Change-Id: I1ebfada93e222992300cd695d04669988206d4b1
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/237660
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
index cf417ba..c66d0c8 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
@@ -35,8 +35,9 @@ SECTIONS
VBOOT2_WORK(0x2A022000, 16K)
PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
TIMESTAMP(0x2A02E000, 1K)
+ CBFS_HEADER_OFFSET(0x2A02E400)
-/* 0x2e400..0x3F000 67 KB free */
+/* 0x2e404..0x3F000 4 bytes shy of 67KB free */
/* Keep the below area reserved at all times, it is used by various QCA
components as shared data