coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

Patch merged into coreboot/master: veyron_{brain, danger, mickey, romy}: Select PHYSICAL_REC_SWITCH
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit c55d8390009f389fcdbb15b6a65bd311c06e2575 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Jul 6 16:52:11 2015 -0700 veyron_{brain,danger,mickey,romy}: Select PHYSICAL_REC_SWITCH BUG=chrome-os-partner:42220 BRANCH=veyron TEST=Used physical recovery button to enter dev mode on mickey Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/283546 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10844 for details. -gerrit

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Patch merged into coreboot/master: smaug: Update PMIC settings
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit 9761a7a2950796fe33b01c10a6d1026a855bb670 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 6 13:40:50 2015 -0700 smaug: Update PMIC settings Update PMIC settings as per table provided by hardware eng team. Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283543 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10843 for details. -gerrit

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Patch merged into coreboot/master: arm64: Print sp value when dumping registers for exception
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit dc197619cd64104d30e5155e0cfec332ec4bce07 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Jul 6 13:13:32 2015 -0700 arm64: Print sp value when dumping registers for exception BUG=None BRANCH=None TEST=Compiles successfully, sp verified during exception Change-Id: Idbeb93b1dbf163e2d86cd42369941ff98a3d2d9e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ca73b40f0248497143b6ab42bd0f5cc6cddf7713 Original-Change-Id: I38ee403200acb0e3d9015231c274568930b58987 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283542 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10842 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10842 for details. -gerrit

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Patch merged into coreboot/master: t210: set CAR2PMC_CPU_ACK_WIDTH to 0
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit cad9e7a6ecf2db58ba30c49847851248d4712110 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed May 6 13:56:50 2015 -0700 t210: set CAR2PMC_CPU_ACK_WIDTH to 0 HW team has suggested to set CAR2PMC_CPU_ACK_WIDTH to 0. BUG=None BRANCH=None TEST=Tested on Smaug; still boot to kernel Change-Id: I4d13a4048b73455b16da7a40c408c912fa97e4e7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8891a79e72af26d986af9e415149d4ca0aa6fedd Original-Change-Id: I850a6756d7743993802fb85aad403e4cbef7a661 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282416 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10841 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10841 for details. -gerrit

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Patch merged into coreboot/master: t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to work
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit 13fb74927ee3d3527494622ca022010c519edd26 Author: Yen Lin <yelin(a)nvidia.com> Date: Fri May 29 14:36:19 2015 -0700 t210: i2c6: enable SOR_SAFE and DPAUX1 clocks for i2c6 to work I2C6 controller needs SOR_SAFE and DPAUX1 clocks to work. These 2 clocks are mistakenly enabled by MBIST. MBIST fix will be submitted next, which will disable these 2 clocks as initial states. Enable these 2 clocks now so I2C6 will continue to work after MBIST fix. BUG=None BRANCH=None TEST=Tested on Smaug, make sure that panel shows display (I2C6 is used to turn on backlight) Change-Id: Id47453e784d53fd6831e8d19a8d57c04c4e1f82f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 83e935f100be85e1e831a3f9f16962304f7cd7d6 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Change-Id: If312881c94570066bdc54f0f5c48226e862bddc6 Original-Reviewed-on: https://chromium-review.googlesource.com/282415 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10840 for details. -gerrit

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Patch merged into coreboot/master: veyron_danger: Enable developer mode switch
by gerrit＠coreboot.org 08 Jul '15

08 Jul '15

the following patch was just integrated into master: commit cc74221581f0b21dcf288532267da01680eb9cc1 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jun 3 16:40:16 2015 -0700 veyron_danger: Enable developer mode switch Danger has a physical developer mode switch, it was just never set up. This patch defines it, sets it up in fill_lb_gpios(), and disables VIRTUAL_DEV_SWITCH. Note: For now at least, dev mode is a bit wonky on Danger. It's connected to both a DIP switch and a button. The button is normally open, pulling dev mode high (defaulting to ON). The switch's "ON" position will pull the value low, so we invert the value in coreboot to see the expected behavior. Dev mode is enabled by holding the button down during boot or by setting switch 2 in the DIP bank to the ON position. BUG=none BRANCH=none TEST=toggled dev switch on Danger and saw dev screen show up (or not) as expected Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318 Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/280852 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10839 for details. -gerrit

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New patch to review for coreboot: arm: add __umoddi3() to libgcc implementation
by Stefan Reinauer 08 Jul '15

08 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10860 -gerrit commit dce8ca34672682cea2f64122ab1192f7d98fb3dd Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 8 23:59:15 2015 +0200 arm: add __umoddi3() to libgcc implementation Change-Id: Ida01506406d1d74211f0155a84c2b25dbaac5f1c Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/arm/libgcc/Makefile.inc | 1 + src/arch/arm/libgcc/libgcc.h | 26 ++++++++++++++++++++++ src/arch/arm/libgcc/udivmoddi4.c | 48 ++++++++++++++++++++++++++++++++++++++++ src/arch/arm/libgcc/umoddi3.c | 24 ++++++++++++++++++++ 4 files changed, 99 insertions(+) diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index aa2acfe..6724ee6 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -20,6 +20,7 @@ ################################################################################ libgcc_files = ashldi3.S lib1funcs.S lshrdi3.S muldi3.S ucmpdi2.S uldivmod.S +libgcc_files += udivmoddi4.c umoddi3.c ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) bootblock-y += $(libgcc_files) diff --git a/src/arch/arm/libgcc/libgcc.h b/src/arch/arm/libgcc/libgcc.h new file mode 100644 index 0000000..afd219c --- /dev/null +++ b/src/arch/arm/libgcc/libgcc.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_ARM_LIBGCC_LIBGCC_H__ +#define __ARCH_ARM_LIBGCC_LIBGCC_H__ + +#include <stdint.h> + +uint64_t __umoddi3(uint64_t num, uint64_t den); +uint64_t __udivmoddi4(uint64_t num, uint64_t den, uint64_t *rem); + +#endif diff --git a/src/arch/arm/libgcc/udivmoddi4.c b/src/arch/arm/libgcc/udivmoddi4.c new file mode 100644 index 0000000..afc91f4 --- /dev/null +++ b/src/arch/arm/libgcc/udivmoddi4.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "libgcc.h" + +uint64_t __udivmoddi4(uint64_t num, uint64_t den, uint64_t *rem_p) +{ + uint64_t quot = 0, qbit = 1; + if (den == 0) { + return 1 / ((unsigned)den); /* Intentional divide by zero, without + triggering a compiler warning which + would abort the build */ + } + + /* Left-justify denominator and count shift */ + while ((int64_t)den >= 0) { + den <<= 1; + qbit <<= 1; + } + + while (qbit) { + if (den <= num) { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } + + if (rem_p) + *rem_p = num; + + return quot; +} diff --git a/src/arch/arm/libgcc/umoddi3.c b/src/arch/arm/libgcc/umoddi3.c new file mode 100644 index 0000000..4064427 --- /dev/null +++ b/src/arch/arm/libgcc/umoddi3.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "libgcc.h" +uint64_t __umoddi3(uint64_t num, uint64_t den) +{ + uint64_t v; + (void) __udivmoddi4(num, den, &v); + return v; +}

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New patch to review for coreboot: rk3288: Fix & vs && mix up in hdmi driver
by Stefan Reinauer 08 Jul '15

08 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10859 -gerrit commit 044a7e138d20526e68ea824d0d46f6c888cf6260 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 8 23:31:46 2015 +0200 rk3288: Fix & vs && mix up in hdmi driver Change-Id: I54650671adaef3bc129c662d6e972474c869afaa Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/rockchip/rk3288/hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index ac58fbf..c9cc232 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -238,7 +238,7 @@ static void hdmi_update_csc_coeffs(void) for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) { u32 coeff = csc_coeff_default[i][j]; write32(&hdmi_regs->csc_coef[i][j].msb, coeff >> 8); - write32(&hdmi_regs->csc_coef[i][j].lsb, coeff && 0xff); + write32(&hdmi_regs->csc_coef[i][j].lsb, coeff & 0xff); } }

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New patch to review for coreboot: device: remove unused x86 include from common code
by Stefan Reinauer 08 Jul '15

08 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10858 -gerrit commit e7e249ca019fd82d91d00b91da9d55d42dd0b90c Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 8 23:25:17 2015 +0200 device: remove unused x86 include from common code The include breaks compilation on ARM with clang. Change-Id: I1ce0d58dbcbb8785c23739670c8c9574c329a81c Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/device/cpu_device.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index 613f1b9..f48946f 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <console/console.h> -#include <cpu/x86/lapic.h> device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) {

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New patch to review for coreboot: arm: enhance eabi compat functions
by Stefan Reinauer 08 Jul '15

08 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10857 -gerrit commit 58bc840948c36b537bd8461a909ea3fbb4ba1fbb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jul 8 23:18:11 2015 +0200 arm: enhance eabi compat functions This fixes issues with our clang reference toolchain on ARM. Change-Id: Ib754941059285f15332bc694814aff6285969545 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/arm/eabi_compat.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 0c79cd5..7c818c6 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -9,6 +9,9 @@ * License, or (at your option) any later version. */ +#include <stdint.h> +#include <stddef.h> +#include <string.h> #include <console/console.h> /* FIXME(dhendrix): prototypes added for assembler */ @@ -23,9 +26,21 @@ int raise (int signum) void __aeabi_unwind_cpp_pr0(void) __attribute__((used)); void __aeabi_unwind_cpp_pr0(void) { -}; +} void __aeabi_unwind_cpp_pr1(void) __attribute__((used)); void __aeabi_unwind_cpp_pr1(void) { -}; +} + +void __aeabi_memcpy(void *dest, const void *src, size_t n); +void __aeabi_memcpy(void *dest, const void *src, size_t n) +{ + (void) memcpy(dest, src, n); +} + +void __aeabi_memset(void *dest, size_t n, int c); +void __aeabi_memset(void *dest, size_t n, int c) +{ + (void) memset(dest, c, n); +}

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coreboot-gerrit July 2015