coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: t210: audio: add CLK_V_EXTPERIPH1 clock
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit ff40196c6c5a83b7cf2ceeb2dd027d4f2587b94a Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 14 11:20:08 2015 -0700 t210: audio: add CLK_V_EXTPERIPH1 clock For audio to work, need to enable CLK_V_EXTPERIPH1 clock. This CL is needed because after MBIST workaround is applied, CLK_V_EXTPERIPH1 clock is default to be off. BUG=None BRANCH=None TEST=Tested on Smaug, hear beep when press Ctrl+U at serial console when DEV screen is showing Change-Id: I32dccc0c7983f8fa86812d845a2f00ac9881d521 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 149d04e6ba642734d5ea36cac8206fad3ac13ce0 Original-Change-Id: Ifa1afb0798c1039c8ea9084b5a7ee3b09b4d70ac Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285604 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/11041 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11041 for details. -gerrit

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Patch merged into coreboot/master: t210: Enable WRAP to INCR burst type conversion in MSELECT
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit c2eae1a4f961da7cdba0c68185b503b1600d1f74 Author: Yen Lin <yelin(a)nvidia.com> Date: Thu May 7 12:28:43 2015 -0700 t210: Enable WRAP to INCR burst type conversion in MSELECT Enable WRAP to INCR burst type conversion in MSELECT. MSELECT CONFIG register can only be accessed by CPU. So do it in ramstage when CPU is started. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: Iee05531c45e566f47af24870be6068247c2d9a00 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 21d9e4d3a8827f7bba57c03ca36b702aaba1ce20 Original-Change-Id: I6a241455b28f24b8756ad09bf7605a2e7e52af57 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282418 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/11040 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11040 for details. -gerrit

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Patch merged into coreboot/master: t210: implement MBIST workaround
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit a501a8f27fb1f5c2ede77191831628d9857e5ef0 Author: Yen Lin <yelin(a)nvidia.com> Date: Wed May 6 18:08:22 2015 -0700 t210: implement MBIST workaround MBIST has left some registers in non-suggested states. This CL restores CAR CE's, SLCG overrides & PLLD settings. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I1ddb19dd9fb6d8fb4d36e67eedeb847c6fd9f774 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 37a1c90c6deb351b2ae2caa03e5076553126744b Original-Change-Id: I613b4ef622d64305d436cb8379a5170b0fe1c9af Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282417 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/11039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11039 for details. -gerrit

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Patch merged into coreboot/master: t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 21ee13c3ca5581c41a53a7e255709aa3c22b373a Author: Yen Lin <yelin(a)nvidia.com> Date: Thu Jul 16 10:23:34 2015 -0700 t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0 Like in cold boot path, need to set CAR2PMC_CPU_ACK_WIDTH to 0 in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: Iffd7fa4d0266e2ec482ec17e5203ceff8afe748f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 052b649b1e6a4e34d621d710ee43aec7149ab8a8 Original-Change-Id: Icdf9879469485fb37b820b30c9663eda528ac013 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286600 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Tom Warren <twarren(a)nvidia.com> Reviewed-on: http://review.coreboot.org/11037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11037 for details. -gerrit

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Patch merged into coreboot/master: t210: change memlayout.ld
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit cbaf92782ed035efd7eca615c64750a5dcdf4161 Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 21 12:48:12 2015 -0700 t210: change memlayout.ld MBIST workaround needs more space in bootblock. bootblock += 4KB; romstage -= 4KB BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I8338d0a134185a425af36e302dcf0ed1520b7e21 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 388523bf4fa25ff3ecf9607ff36ce7c6109485ed Original-Change-Id: Ib08f2ff438f9d96a19b44af1b3e13260966f98f1 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287286 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/11038 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11038 for details. -gerrit

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Patch merged into coreboot/master: google/veyron_rialto: enable VIRTUAL_DEV_SWITCH
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 8868172b8c9eca5bb042373561ed396127d130ae Author: Jonathan Dixon <joth(a)google.com> Date: Tue Jul 21 12:04:05 2015 -0700 google/veyron_rialto: enable VIRTUAL_DEV_SWITCH BUG=chrome-os-partner:43022 TEST=None BRANCH=None Change-Id: I41c904603e7213da1c8d8e0945b572f6ba844031 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d91722317ffc55a4848e8e3bdac8412218fe1dc4 Original-Change-Id: I1ed4c7aaa35158815f8f7a94eafb77db55a381d0 Original-Signed-off-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287300 Original-Reviewed-by: Jason Simmons <jsimmons(a)chromium.org> Original-Reviewed-by: Karl Townsend <karlt(a)chromium.org> Reviewed-on: http://review.coreboot.org/11036 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11036 for details. -gerrit

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Patch merged into coreboot/master: glados: Fix the write protect GPIO exported in ACPI
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 58ae417e23e99dd980b7b20bbef49f1abea66d82 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 17:39:25 2015 -0700 glados: Fix the write protect GPIO exported in ACPI Update the write protect GPIO reported in ACPI to be 71 which is GPP_C23. Also update the controller id to INT344B:00 which will point at the sunrisepoint device in /sys/class/gpio. BUG=chrome-os-partner:42560 BRANCH=none TEST=verify crossystem output with and without WP enabled Change-Id: I625859bd8ac371a5c0cae18697dccf216c26a8b6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8fc5cb6b72dacd6aefe69fe8204f4e0d209ed8a4 Original-Change-Id: I04892e75f9bfe739c44eb40e7c6a969c33e157ca Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286842 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11035 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11035 for details. -gerrit

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Patch merged into coreboot/master: glados: Add SPD manufacturer and part number
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 82286219557baa0a46ab110d8f21afc1980553ac Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 16:59:20 2015 -0700 glados: Add SPD manufacturer and part number The FSP memory info hob does not return this data so we need to supply it from the SPD included with the mainboard. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=execute "mosys memory spd print all" on glados Change-Id: Idfb71d36d1f8163d0daceb68675b10194db7cde7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7feece45900e5166864927047ad3ab7b997f8258 Original-Change-Id: Id2bc544ac5faf53f0f676fe132fea1db5640a401 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286877 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11034 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11034 for details. -gerrit

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Patch merged into coreboot/master: intel: common: Let mainboard supplement FSP memory info
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 46a2c77aaf6e2a74cffbe6ebcfed568a1277f738 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 16:48:55 2015 -0700 intel: common: Let mainboard supplement FSP memory info Since the FSP memory info HOB does not return all the data that we need about a DIMM add a weak function that will allow the mainboard to supplement the generated memory_info structure. Ideally this would not be necessary but until FSP returns the module part number we need this. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=run "mosys memory spd print all" on glados Change-Id: Ic6d0ee0a31d23efcf7e7d7f18a74e944e09e7b46 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 34ad7f1906ba526e52d38d5a6bce7b88b83f0c13 Original-Change-Id: I8509c5c627c1605894473fdea567e7f7ede08cf9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286876 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11033 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11033 for details. -gerrit

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Patch merged into coreboot/master: intel/common: Add SMBIOS memory width
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 0be6d939596249c6a0d6790648cadd7812ffe427 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jun 26 11:15:42 2015 -0700 intel/common: Add SMBIOS memory width Add SMBIOS symbols to define the memory width. Update the Intel common code to display the memory width and provide the memory width to SMBIOS. Also display the memory frequency, size and bus width in decimal. BRANCH=none BUG=None TEST=None Change-Id: I67b814d79fdbbf6ce65ac6b4a8282ab15fb91369 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0e59c7260afd180f3adcbeda7cef1b9eca3ed846 Original-Change-Id: Ibd26812c2aad4deaab62111b1e018be69c4faa7b Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282115 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11032 for details. -gerrit

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coreboot-gerrit July 2015