coreboot-gerrit July 2015

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Patch set updated for coreboot: amd/family14: Add k10temp thermal zone.
by Tobias Diedrich 25 Jul '15

25 Jul '15

Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10940 -gerrit commit 899f697e8e7c14a3197fab3294dac80deb2d4c0d Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Sun Jun 21 18:25:38 2015 +0200 amd/family14: Add k10temp thermal zone. The thermal sensor interface exposed in function 3 of the northbridge is a more convenient and faster way to access the processor-internal thermal sensor than using the SMBus/SB-TSI interface from the FCH, see the Family14 BKDG: "Tctl is a processor temperature control value used for processor thermal management. Tctl is accessible through SB-TSI and D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the processors cooling requirements" Also on at least some of these boards the existing thermal zone is broken and always returns 40C (the default value if the SMBus read failed) because the SMBus muxing register (SmBus0Sel) is not set up correctly. Case in point: The fallback "smbus read failed" temperature is 40 C and the the logs taken from the board status repository for the Asrock E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)" e.g. http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1… and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1… and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1… Example lm-sensors output with this patch on the pcengines APU1, on Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and CONFIG_SENSORS_K10TEMP enabled): acpitz-virtual-0 Adapter: Virtual device temp1: +54.0 C (crit = +100.0 C) k10temp-pci-00c3 Adapter: PCI adapter temp1: +54.0 C (high = +70.0 C) (crit = +100.0 C, hyst = +97.0 C) Change-Id: Id9c5b783ba424246816677099ec6651814e59f21 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- src/mainboard/amd/inagua/acpi/thermal.asl | 90 ---------------------- src/mainboard/amd/inagua/dsdt.asl | 2 - src/mainboard/amd/persimmon/acpi/thermal.asl | 21 ----- src/mainboard/amd/persimmon/dsdt.asl | 2 - src/mainboard/amd/south_station/acpi/thermal.asl | 90 ---------------------- src/mainboard/amd/south_station/dsdt.asl | 2 - src/mainboard/amd/union_station/acpi/thermal.asl | 90 ---------------------- src/mainboard/amd/union_station/dsdt.asl | 2 - src/mainboard/asrock/e350m1/acpi/thermal.asl | 88 --------------------- src/mainboard/asrock/e350m1/dsdt.asl | 2 - src/mainboard/gizmosphere/gizmo/acpi/thermal.asl | 21 ----- src/mainboard/gizmosphere/gizmo/dsdt.asl | 2 - src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl | 21 ----- src/mainboard/jetway/nf81-t56n-lf/dsdt.asl | 2 - src/mainboard/pcengines/apu1/acpi/thermal.asl | 21 ----- src/mainboard/pcengines/apu1/dsdt.asl | 2 - .../amd/agesa/family14/acpi/northbridge.asl | 8 ++ 17 files changed, 8 insertions(+), 458 deletions(-) diff --git a/src/mainboard/amd/inagua/acpi/thermal.asl b/src/mainboard/amd/inagua/acpi/thermal.asl deleted file mode 100644 index 2f9e8d7..0000000 --- a/src/mainboard/amd/inagua/acpi/thermal.asl +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#if 0 -/* THERMAL */ -Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ -} -#endif diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 86cde02..faaa288 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -63,7 +63,5 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/mainboard/amd/persimmon/acpi/thermal.asl b/src/mainboard/amd/persimmon/acpi/thermal.asl deleted file mode 100644 index baa4043..0000000 --- a/src/mainboard/amd/persimmon/acpi/thermal.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Thermal Zones have been #if 0 for a long time. - * Removing it for now because it doesn't seem to - * do anything when enabled anyway. - */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 86cde02..faaa288 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -63,7 +63,5 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/mainboard/amd/south_station/acpi/thermal.asl b/src/mainboard/amd/south_station/acpi/thermal.asl deleted file mode 100644 index 2f9e8d7..0000000 --- a/src/mainboard/amd/south_station/acpi/thermal.asl +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#if 0 -/* THERMAL */ -Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ -} -#endif diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index 86cde02..faaa288 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -63,7 +63,5 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/mainboard/amd/union_station/acpi/thermal.asl b/src/mainboard/amd/union_station/acpi/thermal.asl deleted file mode 100644 index 2f9e8d7..0000000 --- a/src/mainboard/amd/union_station/acpi/thermal.asl +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#if 0 -/* THERMAL */ -Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ -} -#endif diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 86cde02..faaa288 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -63,7 +63,5 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/mainboard/asrock/e350m1/acpi/thermal.asl b/src/mainboard/asrock/e350m1/acpi/thermal.asl deleted file mode 100644 index 440c17d..0000000 --- a/src/mainboard/asrock/e350m1/acpi/thermal.asl +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* THERMAL */ -Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ -} diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 6dcf0a6..71ea450 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -57,7 +57,5 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/mainboard/gizmosphere/gizmo/acpi/thermal.asl b/src/mainboard/gizmosphere/gizmo/acpi/thermal.asl deleted file mode 100644 index baa4043..0000000 --- a/src/mainboard/gizmosphere/gizmo/acpi/thermal.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Thermal Zones have been #if 0 for a long time. - * Removing it for now because it doesn't seem to - * do anything when enabled anyway. - */ diff --git a/src/mainboard/gizmosphere/gizmo/dsdt.asl b/src/mainboard/gizmosphere/gizmo/dsdt.asl index d960622..a4d3034 100644 --- a/src/mainboard/gizmosphere/gizmo/dsdt.asl +++ b/src/mainboard/gizmosphere/gizmo/dsdt.asl @@ -58,7 +58,5 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl deleted file mode 100644 index baa4043..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Thermal Zones have been #if 0 for a long time. - * Removing it for now because it doesn't seem to - * do anything when enabled anyway. - */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl index 529fd72..64b00d0 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/dsdt.asl @@ -57,8 +57,6 @@ DefinitionBlock ( #include "acpi/sleep.asl" #include "acpi/gpe.asl" - #include <southbridge/amd/cimx/sb800/acpi/smbus.asl> - #include "acpi/thermal.asl" #include "acpi/superio.asl" } /* End of ASL file */ diff --git a/src/mainboard/pcengines/apu1/acpi/thermal.asl b/src/mainboard/pcengines/apu1/acpi/thermal.asl deleted file mode 100644 index baa4043..0000000 --- a/src/mainboard/pcengines/apu1/acpi/thermal.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Thermal Zones have been #if 0 for a long time. - * Removing it for now because it doesn't seem to - * do anything when enabled anyway. - */ diff --git a/src/mainboard/pcengines/apu1/dsdt.asl b/src/mainboard/pcengines/apu1/dsdt.asl index 523b445..b70528f 100644 --- a/src/mainboard/pcengines/apu1/dsdt.asl +++ b/src/mainboard/pcengines/apu1/dsdt.asl @@ -63,7 +63,5 @@ DefinitionBlock ( #include "acpi/buttons.asl" #include "acpi/gpio.asl" #include "acpi/leds.asl" - - #include "acpi/thermal.asl" } /* End of ASL file */ diff --git a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl index bb051b9..ef51e7c 100644 --- a/src/northbridge/amd/agesa/family14/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family14/acpi/northbridge.asl @@ -126,3 +126,11 @@ Device(PE23) { Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */ + +/* Northbridge function 3 */ +Device(NBF3) { + Name(_ADR, 0x00180003) + + /* k10temp thermal zone */ + #include <northbridge/amd/amdfam10/thermal_mixin.asl> +} /* end NBF3 */

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Patch set updated for coreboot: cpu/intel: Add SoC specific microcode update check in ramstage
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11055 -gerrit commit e0c0e9af9e69e56ad09a27ace6ee9221916f5165 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:31:51 2015 +0530 cpu/intel: Add SoC specific microcode update check in ramstage Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid relading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++ src/include/cpu/intel/microcode.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 3492bfd..673f3b9 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,6 +28,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> +#include <rules.h> #if !defined(__PRE_RAM__) #include <cbfs.h> @@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; +#if ENV_RAMSTAGE + /* SoC specific check to update microcode */ + if (soc_ucode_update_required(current_rev, m->rev) < 0) { + printk(BIOS_DEBUG, "Skip microcode update\n"); + return; + } +#endif + msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); @@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } + +#if ENV_RAMSTAGE +__attribute__((weak)) int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id) +{ + return 0; +} +#endif diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index d2fa1b7..d951a63 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -29,6 +29,10 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); + +/* SoC specific check to determine if microcode update is really + * required, return value of < 0 will skip microcode update. */ +int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id); #endif #endif

1 0

Patch set updated for coreboot: cpu/intel: Add SoC specific microcode update check in ramstage
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11055 -gerrit commit fc97be57fce6f1b1f91eee4baed3b67570e2b796 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:31:51 2015 +0530 cpu/intel: Add SoC specific microcode update check in ramstage Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid relading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++ src/include/cpu/intel/microcode.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 3492bfd..1ee1299 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,6 +28,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> +#include <rules.h> #if !defined(__PRE_RAM__) #include <cbfs.h> @@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; +#if ENV_RAMSTAGE + /*SoC specific check to update microcode*/ + if (soc_ucode_update_required(current_rev, m->rev) < 0) { + printk(BIOS_DEBUG, "Skip microcode update\n"); + return; + } +#endif + msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); @@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } + +#if ENV_RAMSTAGE +__attribute__((weak)) int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id) +{ + return 0; +} +#endif diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index d2fa1b7..d951a63 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -29,6 +29,10 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); + +/* SoC specific check to determine if microcode update is really + * required, return value of < 0 will skip microcode update. */ +int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id); #endif #endif

1 0

New patch to review for coreboot: skylake: Update microcode reload in ramstage.
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11056 -gerrit commit 5042aad4ded1651638ae9b60e34114b65e4f211e Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:40:53 2015 +0530 skylake: Update microcode reload in ramstage. For Skylake, Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootclock and ramstage (MP init). Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:287513 Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287674 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index cd88c10..97b928d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -574,3 +574,19 @@ void soc_init_cpus(device_t dev) if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) restore_default_smm_area(smm_save_area); } + +int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id) +{ + msr_t msr; + /* If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + if ((msr.lo & PRMRR_SUPPORTED) && currrent_patch_id == new_patch_id - 1) { + return -1; + } + return 0; +}

1 0

New patch to review for coreboot: Add SoC specific microcode update check in ramstage
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11055 -gerrit commit 3d9c72ee7ef82d69b5186d40e6c742a7b7b878cf Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:31:51 2015 +0530 Add SoC specific microcode update check in ramstage Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid relading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++ src/include/cpu/intel/microcode.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 3492bfd..1ee1299 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,6 +28,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> +#include <rules.h> #if !defined(__PRE_RAM__) #include <cbfs.h> @@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; +#if ENV_RAMSTAGE + /*SoC specific check to update microcode*/ + if (soc_ucode_update_required(current_rev, m->rev) < 0) { + printk(BIOS_DEBUG, "Skip microcode update\n"); + return; + } +#endif + msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); @@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } + +#if ENV_RAMSTAGE +__attribute__((weak)) int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id) +{ + return 0; +} +#endif diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index d2fa1b7..d951a63 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -29,6 +29,10 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); + +/* SoC specific check to determine if microcode update is really + * required, return value of < 0 will skip microcode update. */ +int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id); #endif #endif

1 0

New patch to review for coreboot: skylake: remove the redundant fspNotify in chip final.
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11054 -gerrit commit 4402fd8874192c966e4a53f0e1388131596a7ab3 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Thu Jul 23 17:31:56 2015 -0700 skylake: remove the redundant fspNotify in chip final. The fspNotify(EnumInitPhaseAfterPciEnumeration) is already registered in fsp_util.c as a generic callback, this is some code left from early development. Also I don't see a need for the chip_final function, although we could keep it as a placeholder but i decided to remove it. BUG=chrome-os-partner:42979 BRANCH=None TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3. Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7 Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287991 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/chip.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f1a104c..b1b66fc 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -38,17 +38,8 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_bus_default_ops, }; -static void chip_final(device_t dev) -{ - /* Notify FSP done device setup */ - printk(BIOS_DEBUG, - "Calling FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - fsp_notify(EnumInitPhaseAfterPciEnumeration); -} - static struct device_operations cpu_bus_ops = { .init = &soc_init_cpus, - .final = &chip_final, }; static void soc_enable(device_t dev)

1 0

New patch to review for coreboot: skylake: Rework microcode include path
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11053 -gerrit commit 14af53633ca39fcb450a1701f6a6dee1a9184841 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 13 10:44:05 2015 -0700 skylake: Rework microcode include path Remove the microcode include path config options and include the mainboard blob directory by default. BUG=chrome-os-partner:42109 BRANCH=none TEST=emerge-glados coreboot CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922 Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448 Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285150 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 9 --------- src/soc/intel/skylake/microcode/Makefile.inc | 3 --- src/soc/intel/skylake/microcode/microcode_blob.c | 2 +- src/soc/intel/skylake/microcode/microcode_blob.h | 21 --------------------- 4 files changed, 1 insertion(+), 34 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d3c541d..d21fe3a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -96,11 +96,6 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. -config EXTRA_MICROCODE_INCLUDE_PATH - string "Include path for extra microcode patches." - help - The path to any extra microcode patches from other sources. - config HAVE_IFD_BIN bool "Use Intel Firmware Descriptor from existing binary" default n @@ -166,10 +161,6 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" -config MICROCODE_INCLUDE_PATH - string - default "src/soc/intel/skylake/microcode" - config MMCONF_BASE_ADDRESS hex "MMIO Base Address" default 0xe0000000 diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index 2356b84..a5e8981 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,9 +1,6 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c -# Include path for addition microcode sources. -INCLUDES += -I$(CONFIG_EXTRA_MICROCODE_INCLUDE_PATH) - # This section overrides the default build process for the microcode to place # it at a known location in the CBFS. This only needs to be enabled if FSP is # being used. diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c index 511c899..48c1aa2 100644 --- a/src/soc/intel/skylake/microcode/microcode_blob.c +++ b/src/soc/intel/skylake/microcode/microcode_blob.c @@ -19,6 +19,6 @@ */ unsigned int microcode[] = { -#include "microcode_blob.h" +#include <microcode/microcode_blob.h> }; diff --git a/src/soc/intel/skylake/microcode/microcode_blob.h b/src/soc/intel/skylake/microcode/microcode_blob.h deleted file mode 100644 index 82a8664..0000000 --- a/src/soc/intel/skylake/microcode/microcode_blob.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include "MC0406E2_00000017_00000018.h"

1 0

New patch to review for coreboot: Skylake: Fix Microcode reload in bootblock cpu init
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11052 -gerrit commit 11ae30e90a67061970812ba2dd4ee1b2c88f8203 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jul 7 18:18:15 2015 +0530 Skylake: Fix Microcode reload in bootblock cpu init For Skylake Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in the bootblock cpu init. Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286054 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/bootblock/cpu.c | 20 +++++++++++++++++++- src/soc/intel/skylake/include/soc/msr.h | 2 +- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index d4506e5..3c893f6 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -180,9 +180,27 @@ static void check_for_clean_reset(void) static void bootblock_cpu_init(void) { + const struct microcode *patch; + u32 current_rev; + msr_t msr; + /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - intel_update_microcode_from_cbfs(); + + patch = intel_microcode_find(); + + current_rev = read_microcode_rev(); + + /* If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + if (msr.lo & PRMRR_SUPPORTED && current_rev != patch->rev - 1) { + intel_update_microcode_from_cbfs(); + } } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index b857dbe..3903757 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -105,6 +105,6 @@ /* MTRRcap_MSR bits */ #define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define PRMRR_SUPPORTED (1<<12) #endif

1 0

New patch to review for coreboot: veyron: update mickey sdram-lpddr3-samsung-2GB.inc
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11051 -gerrit commit 018852cab9a7cca8eb263e3cc5a8cc542fc3679c Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Jul 23 11:51:51 2015 +0800 veyron: update mickey sdram-lpddr3-samsung-2GB.inc Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This resolves an issue that was observed on some Mickey boards with the Samsung 2GB LPDDR3 and is believed to be caused by inferior routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.) BUG=chrome-os-partner:41905 TEST=Boot from mickey BRANCH=None Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286333 --- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 0f15ba5..cc39f62 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -65,7 +65,8 @@ .mr[0] = 0x0, .mr[1] = 0xC3, .mr[2] = 0x6, - .mr[3] = 0x1 + /* 60Ohms instead of 34.3 due to bad PCB routing on Mickey. */ + .mr[3] = 0x4 }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6,

1 0

New patch to review for coreboot: Revert "smaug: Do not gate XUSB partitions"
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11050 -gerrit commit db142843d162f06be7ac2fbd14f65cf5ec72cb8d Author: Andrew Bresticker <abrestic(a)chromium.org> Date: Mon Jul 20 10:34:06 2015 -0700 Revert "smaug: Do not gate XUSB partitions" The PLLU and UTMIPLL power-up sequences have been fixed in the kernel. It's no longer necessary for the XUSB partitions to be ungated at boot. This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7. BUG=chrome-os-partner:41244 TEST=Build and boot on Smaug; xHCI still works. BRANCH=none CQ-DEPEND=CL:282765 Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1 Original-Signed-off-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286810 Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Mark Kuo <mkuo(a)nvidia.com> Original-Reviewed-by: Mark Kuo <mkuo(a)nvidia.com> --- src/mainboard/google/smaug/mainboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1a197b4..1cf4d32 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -178,6 +178,9 @@ static void powergate_unused_partitions(void) static const uint32_t partitions[] = { POWER_PARTID_PCX, POWER_PARTID_SAX, + POWER_PARTID_XUSBA, + POWER_PARTID_XUSBB, + POWER_PARTID_XUSBC, POWER_PARTID_NVDEC, POWER_PARTID_NVJPG, POWER_PARTID_DFD,

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coreboot-gerrit July 2015