coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

1 participants
1048 discussions

New patch to review for coreboot: tegra lp0: fix checkpatch errors
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11048 -gerrit commit 29e18015843f0a88bb4c4149459f9d547eb1d1d5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 14 12:00:28 2015 -0700 tegra lp0: fix checkpatch errors The checkpatch.pl scripts complains about the placing of the inline keyword: ERROR: inline keyword should sit between storage class and type Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> BUG=chrome-os-partner:38073 BRANCH=none TEST=repo upload works ;) Change-Id: Ibd2b8a437eda2fc720f8fc32c5821bae3be41d12 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d20c0d34240966d5ae39c1667d4486b4341e183b Original-Change-Id: I36d600c4677c622c334d849bf260323592a8a4fc Original-Reviewed-on: https://chromium-review.googlesource.com/285543 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Original-Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 8 ++++---- src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c | 8 ++++---- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index e8cd571..afb01e5 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -270,22 +270,22 @@ static inline void __attribute__((always_inline)) for (;;); } -inline static uint32_t read32(const void *addr) +static inline uint32_t read32(const void *addr) { return *(volatile uint32_t *)addr; } -inline static void write32(void *addr, uint32_t val) +static inline void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } -inline static void setbits32(uint32_t bits, void *addr) +static inline void setbits32(uint32_t bits, void *addr) { write32(addr, read32(addr) | bits); } -inline static void clrbits32(uint32_t bits, void *addr) +static inline void clrbits32(uint32_t bits, void *addr) { write32(addr, read32(addr) & ~bits); } diff --git a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c index 621c4b7..da60c4b 100644 --- a/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c @@ -249,22 +249,22 @@ static inline void __attribute__((always_inline)) for (;;); } -inline static uint32_t read32(const void *addr) +static inline uint32_t read32(const void *addr) { return *(volatile uint32_t *)addr; } -inline static void write32(void *addr, uint32_t val) +static inline void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; } -inline static void setbits32(uint32_t bits, void *addr) +static inline void setbits32(uint32_t bits, void *addr) { write32(addr, read32(addr) | bits); } -inline static void clrbits32(uint32_t bits, void *addr) +static inline void clrbits32(uint32_t bits, void *addr) { write32(addr, read32(addr) & ~bits); } diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index dc61cba..cf9c212 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -408,22 +408,22 @@ static inline void __attribute__((always_inline)) for (;;); } -inline static uint32_t read32(const void *addr) +static inline uint32_t read32(const void *addr) { return *(volatile uint32_t *)addr; } -inline static void write32(uint32_t val, void *addr) +static inline void write32(uint32_t val, void *addr) { *(volatile uint32_t *)addr = val; } -inline static void setbits32(uint32_t bits, void *addr) +static inline void setbits32(uint32_t bits, void *addr) { write32(addr, read32(addr) | bits); } -inline static void clrbits32(uint32_t bits, void *addr) +static inline void clrbits32(uint32_t bits, void *addr) { write32(addr, read32(addr) & ~bits); }

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Patch set updated for coreboot: glados: Add ACPI configs for speaker amps and codec
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11044 -gerrit commit 437eaea1f0630e002a5a3b9fd6d3543b47acb176 Author: Ben Zhang <benzh(a)chromium.org> Date: Fri Jun 26 17:17:53 2015 -0700 glados: Add ACPI configs for speaker amps and codec The audio codec nau8825 and two ssm4567 speaker amps are instantiated via ACPI. BUG=chrome-os-partner:41280 BRANCH=none TEST=The devices are instantiated. Speaker/headphone playback works on glados. Change-Id: I1297c2435b3051dd749ad7de324b64ba1504cf09 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 59e5eb2682a2fc2cb58068dfcb6dd2415d43b286 Original-Change-Id: Ib7ec8c868251601f67cdf365cd3e935d256c8ac5 Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282364 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/mainboard.asl | 72 ++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index ab40d62..7c26e42 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -93,3 +93,75 @@ Scope (\_SB.PCI0.I2C1) } } } + +Scope (\_SB.PCI0.I2C4) +{ + Device (CODC) // Codec for headset + { + Name (_HID, "10508825") + Name (_DDN, "NAU88L25 Codec") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x1A, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C4", /* ResourceSource */ + ) + }) + + Method (_STA) + { + Return (0xF) + } + } + + Device (SPK0) // Left speaker Amp + { + Name (_HID, "INT343B") + Name (_DDN, "SSM4567 Speaker Amp") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x34, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C4", /* ResourceSource */ + ) + }) + + Method (_STA) + { + Return (0xF) + } + } + + Device (SPK1) // Right speaker Amp + { + Name (_HID, "INT343B") + Name (_DDN, "SSM4567 Speaker Amp") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x35, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C4", /* ResourceSource */ + ) + }) + + Method (_STA) + { + Return (0xF) + } + } +}

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Patch merged into coreboot/master: sklrvp: Add board_info file
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 65459b3cc8c983e30c2b2ce22887b848363052b7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jul 17 13:33:13 2015 -0700 sklrvp: Add board_info file Change-Id: I658f88189857e25dde474d59875650f72c680818 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/10972 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10972 for details. -gerrit

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New patch to review for coreboot: README: improve description of compiler requirements
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11047 -gerrit commit 438b506c5dd39de56682bc6900097cbefe923a08 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jul 23 21:08:30 2015 +0200 README: improve description of compiler requirements People run into "building bootblock without the required toolchain" too often. Update documentation so they don't try to use random compilers to build coreboot. Change-Id: I9715b52a4bac9b886cc5627add074c04e06a0828 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- README | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/README b/README index 2c25bef..357ec02 100644 --- a/README +++ b/README @@ -41,15 +41,22 @@ For details please consult: Build Requirements ------------------ - * gcc / g++ * make + * gcc / g++ + Because Linux distribution compilers tend to use lots of patches. coreboot + does lots of "unusual" things in its build system, some of which break due + to those patches, sometimes by gcc aborting, sometimes - and that's worse - + by generating broken object code. + Two options: use our toolchain (eg. make crosstools-i386) or enable the + ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this + case). + * iasl (for targets with ACPI support) Optional: * doxygen (for generating/viewing documentation) - * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) - * ncurses (for 'make menuconfig') + * ncurses (for 'make menuconfig' and 'make nconfig') * flex and bison (for regenerating parsers)

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New patch to review for coreboot: glados: Support reading memory strap GPIOs to select SPD
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11046 -gerrit commit 37e56e97df38bb63bc30754e9e27c44271b11ec3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 22 09:21:29 2015 -0700 glados: Support reading memory strap GPIOs to select SPD Add some board specific code to enable the memory configuration GPIOs in GPIO input mode and read them to determine which memory type is on the board. Also add the other memory types that are not yet present in the glados mainboard directory. This should be replaced with the real gpio infrastructure once it is ready. BUG=chrome-os-partner:43069 BRANCH=none TEST=build and boot on glados Change-Id: I7a9ce10e92ad6681528572e87b6cfee29880841a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d81e969c5950fd89bb745d1403abddb08a942f83 Original-Change-Id: Iffb0bd5c176f2adbdd9302d9bff5b7bde725d671 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287436 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/spd/Makefile.inc | 6 ++- .../glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex | 16 ++++++++ .../glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex | 16 ++++++++ src/mainboard/google/glados/spd/spd.c | 44 +++++++++++++++++++--- 4 files changed, 75 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/glados/spd/Makefile.inc b/src/mainboard/google/glados/spd/Makefile.inc index d8c0c51..f415ef8 100644 --- a/src/mainboard/google/glados/spd/Makefile.inc +++ b/src/mainboard/google/glados/spd/Makefile.inc @@ -23,8 +23,10 @@ romstage-y += spd.c SPD_BIN = $(obj)/spd.bin # SPD data by index. No method for board identification yet -SPD_SOURCES = samsung_dimm_K4E6E304EE-EGCF # 0 -SPD_SOURCES += empty # 1 +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF # 0b0001 +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR # 0b0010 +SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR # 0b0011 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex new file mode 100644 index 0000000..f724c74 --- /dev/null +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex new file mode 100644 index 0000000..c3a3888 --- /dev/null +++ b/src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 5ee12f5..1882fa7 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -24,6 +24,7 @@ #include <string.h> #include <soc/gpio.h> #include <soc/pei_data.h> +#include <soc/pcr.h> #include <soc/romstage.h> #include "spd.h" @@ -84,6 +85,42 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) char *spd_file; size_t spd_file_len; int spd_index; + int spd_gpio[4]; + + /************************************************************* + * FIXME: Remove when real GPIO support is ready. + */ + GPIO_PAD gpio_set[4] = { + GPIO_LP_GPP_C12, /* PCH_MEM_CONFIG[0] */ + GPIO_LP_GPP_C13, /* PCH_MEM_CONFIG[1] */ + GPIO_LP_GPP_C14, /* PCH_MEM_CONFIG[2] */ + GPIO_LP_GPP_C15, /* PCH_MEM_CONFIG[3] */ + }; + int index; + + for (index = 0; index < ARRAY_SIZE(gpio_set); index++) { + u32 number = GPIO_GET_PAD_NUMBER(gpio_set[index]); + u32 cfgreg = 8 * number + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET; + /* + * Set GPIO mode and enable input + * Clear PMODE0 | PMODE1 | GPIORXDIS + */ + u32 dw0mask = (1 << 10) | (1 << 11) | (1 << 9); + u32 dw0reg = 0; + pcr_andthenor32(PID_GPIOCOM1, cfgreg, ~dw0mask, dw0reg); + + /* Read current input value */ + pcr_read32(PID_GPIOCOM1, cfgreg, &dw0reg); + spd_gpio[index] = !!(dw0reg & (1 << 1)); + } + /*************************************************************/ + + spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | + (spd_gpio[1] << 1) | spd_gpio[0]; + + printk(BIOS_DEBUG, + "SPD: index %d (GPP_C15=%d GPP_C14=%d GPP_C13=%d GPP_C12=%d)\n", + spd_index, spd_gpio[3], spd_gpio[2], spd_gpio[1], spd_gpio[0]); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -95,13 +132,10 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) if (spd_file_len < SPD_LEN) die("Missing SPD data."); - /* Add board SKU detection here. Currently we only support one. */ - spd_index = 0; - /* Make sure we did not overrun the buffer */ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; + printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); + spd_index = 1; } /* Assume same memory in both channels */

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New patch to review for coreboot: glados: Enable internal pullup for EC_IN_RW
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11045 -gerrit commit 727b4c5971a65e37737ad6db94b626d72e2e53f9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 22 09:22:13 2015 -0700 glados: Enable internal pullup for EC_IN_RW Enable 20K internal pullup for the EC_IN_RW GPIO. BUG=chrome-os-partner:42285 BRANCH=none TEST=build and boot on glados Change-Id: I499164fb5050d350510072d2a06eb97fb7f9fcb1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e2de7d4800797a1585165a34dd39af3d635b1f55 Original-Change-Id: I7af1b78482197701aa452998106c2c3476fcc330 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287437 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index 35b1ae4..0b18222 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -96,7 +96,7 @@ const GPIO_INIT_CONFIG mainboard_gpio_table[] = { GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* EC_IN_RW */ {GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, + GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, /* EN_PP3300_KEPLER */ {GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},

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New patch to review for coreboot: glados: Add ACPI configs for speaker amps and codec
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11044 -gerrit commit a0816b41f1c788033f64b934a9c7c7c1dca8013c Author: Ben Zhang <benzh(a)chromium.org> Date: Fri Jun 26 17:17:53 2015 -0700 glados: Add ACPI configs for speaker amps and codec The audio codec nau8825 and two ssm4567 speaker amps are instantiated via ACPI. BUG=chrome-os-partner:41280 BRANCH=none TEST=The devices are instantiated. Speaker/headphone playback works on glados. Change-Id: I1297c2435b3051dd749ad7de324b64ba1504cf09 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 59e5eb2682a2fc2cb58068dfcb6dd2415d43b286 Original-Change-Id: Ib7ec8c868251601f67cdf365cd3e935d256c8ac5 Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282364 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/acpi/mainboard.asl | 72 ++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index ab40d62..e4b3c59 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -93,3 +93,75 @@ Scope (\_SB.PCI0.I2C1) } } } + +Scope (\_SB.PCI0.I2C4) +{ + Device (CODC) // Codec for headset + { + Name (_HID, "10508825") + Name (_DDN, "NAU88L25 Codec") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x1A, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C4", // ResourceSource + ) + }) + + Method (_STA) + { + Return (0xF) + } + } + + Device (SPK0) // Left speaker Amp + { + Name (_HID, "INT343B") + Name (_DDN, "SSM4567 Speaker Amp") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x34, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C4", // ResourceSource + ) + }) + + Method (_STA) + { + Return (0xF) + } + } + + Device (SPK1) // Right speaker Amp + { + Name (_HID, "INT343B") + Name (_DDN, "SSM4567 Speaker Amp") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x35, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C4", // ResourceSource + ) + }) + + Method (_STA) + { + Return (0xF) + } + } +}

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New patch to review for coreboot: skylake: Fix building without serial console
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11043 -gerrit commit ff57c438b9a260fe235a45227e9f2cc06c0d4727 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 22 09:24:23 2015 -0700 skylake: Fix building without serial console In order to build without CONFIG_CONSOLE_SERIAL the Skylake SOC Kconfig should not be enabling serial console by default. Also fix other compile issues when serial console is disabled. BUG=chrome-os-partner:40857 BRANCH=none TEST=build glados without serial console enabled Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55 Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287438 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 2 -- src/soc/intel/skylake/romstage/romstage.c | 3 ++- src/soc/intel/skylake/uart.c | 3 ++- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index dbf68a7..d3c541d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -17,8 +17,6 @@ config CPU_SPECIFIC_OPTIONS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION - select CONSOLE_SERIAL8250MEM - select CONSOLE_SERIAL8250MEM_32 select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_MICROCODE_IN_CBFS diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 919b747..04ffa3e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,7 +50,8 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init(); - pch_uart_init(); + if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32)) + pch_uart_init(); } /* SOC initialization before RAM is enabled */ diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 03d2ba6..9304118 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -36,7 +36,8 @@ static void pch_uart_read_resources(struct device *dev) pci_dev_read_resources(dev); /* Set the configured UART base address for the debug port */ - if (pch_uart_is_debug(dev)) { + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) && + pch_uart_is_debug(dev)) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); res->size = 0x1000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |

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New patch to review for coreboot: rockchip: rk3288: extend jerry backlight vcc_led delay time
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11042 -gerrit commit 1ff014c6a9e150a5bb60c7eb288611bcd630f4c2 Author: huang lin <hl(a)rock-chips.com> Date: Wed Jul 22 10:49:11 2015 +0800 rockchip: rk3288: extend jerry backlight vcc_led delay time some jerry panel need more delay time between the vcc_led and bl_en, so we extend the delay time. BUG=chrome-os-partner:42997 TEST=Boot from jerry, and do not flicker again BRANCH=none Change-Id: Ifcf84578038eb5c2e5a0dfae936ee63cef671968 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0b00b6bd108f0aae461085d00819eca08ec892b3 Original-Change-Id: I74999601b41ccac22493cc9cd0bf52cd4dbb8c26 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287373 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_jerry/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c index 7412243..2a945c4 100644 --- a/src/mainboard/google/veyron_jerry/mainboard.c +++ b/src/mainboard/google/veyron_jerry/mainboard.c @@ -158,7 +158,7 @@ void mainboard_power_on_backlight(void) break; default: gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */ - mdelay(20); + mdelay(120); gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */ mdelay(10); gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */

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Patch merged into coreboot/master: nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit acba73aefcbd7dacb547b61570a1836b745be2e5 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 20 09:51:34 2015 -0500 nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10984 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See http://review.coreboot.org/10984 for details. -gerrit

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coreboot-gerrit July 2015