coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: glados: Set the write protect GPIO
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit caa5149b1ef4a77e9ce9abf65bbfcd54232ea129 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 15:50:42 2015 -0700 glados: Set the write protect GPIO The write protect gpio is not added to the gpio map so the structure is not valid for vboot to consume. BUG=chrome-os-partner:42560 BRANCH=none TEST=build and boot on glados, check basic crossytem output CQ-DEPEND=CL:286911 Change-Id: I228d75049b919449072e395699c822203a08f1c6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d15438c4bf56d92189f2f501a62b55b5d00ba461 Original-Change-Id: I3290c4b96e1cc675c618a983915b778f11175020 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286930 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11031 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11031 for details. -gerrit

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Patch merged into coreboot/master: skylake: sanitize pcr header for ACPI and assembler
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 97892bd557cfae6d103a9e685f475461cb35cb41 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 20 16:46:19 2015 -0500 skylake: sanitize pcr header for ACPI and assembler Remove the C types and functions from PCR so that pcr.h can be included from assembly and ACPI. While in there make the PCR reg caclulation using a C function and place the P2SB (PCH_PCR_BASE_ADDRESS) address in iomap.h. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I9cde178bcdbf49327ef7892393fc277f6c74f34b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fdf5c77ecfa0ca8d3c45604d15b9dec9a6e85193 Original-Change-Id: I5996efaa9869f8f412e4d45c13f30233384a38b2 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286901 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11030 for details. -gerrit

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Patch merged into coreboot/master: skylake: provide more clarity for PCR access
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 1383920fef40f9ee7b1dd7e9f019ba67c77f2d58 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 20 14:28:01 2015 -0500 skylake: provide more clarity for PCR access The current primary to sideband (P2SB) code for private configuration register (PCR) access weren't very clear with the naming or reasoning for some of the code. Provide more verbiage surrounding this interface. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I5b2e84444a29b2fc2f527502e8c9f26eb60e687a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 06345ba1abd893059a6584856851f92f43289247 Original-Change-Id: If57a4bbc90365c1135b4986dce328b5dbabe483b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286900 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11029 for details. -gerrit

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Patch set updated for coreboot: google/veyron_rialto: enable VIRTUAL_DEV_SWITCH
by Patrick Georgi 23 Jul '15

23 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11036 -gerrit commit 3b43acc314eab875bda88566c43ce622f883a442 Author: Jonathan Dixon <joth(a)google.com> Date: Tue Jul 21 12:04:05 2015 -0700 google/veyron_rialto: enable VIRTUAL_DEV_SWITCH BUG=chrome-os-partner:43022 TEST=None BRANCH=None Change-Id: I41c904603e7213da1c8d8e0945b572f6ba844031 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d91722317ffc55a4848e8e3bdac8412218fe1dc4 Original-Change-Id: I1ed4c7aaa35158815f8f7a94eafb77db55a381d0 Original-Signed-off-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287300 Original-Reviewed-by: Jason Simmons <jsimmons(a)chromium.org> Original-Reviewed-by: Karl Townsend <karlt(a)chromium.org> --- src/mainboard/google/veyron_rialto/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 1886db9..42ecb97 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND + select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string

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Patch merged into coreboot/master: cyan/strago: disable Ambient Light Sensor device
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit e95b7d80a2c3dc22280b9b1e8f22da5043e8b552 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu Jul 16 17:56:18 2015 -0700 cyan/strago: disable Ambient Light Sensor device No devices are connected to i2c4 bus on both strago and cyan board. Hence disabling the ALS platform data. This will fix the i2c4 timeout issue and also help in boot time optimization. Removed unused macros. BUG=None BRANCH=chrome-os-partner:41934 TEST=After booting to kernel, i2c4 timeout error message should not appear in dmesg. Change-Id: Ib7ab4c95b0830a8d4e53c6c0ee919649ad1ed354 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3c52b64037b46016fe01f1d55c4c58f7684eb778 Original-Change-Id: Ia7acdcef67a2f2837866f56aa0426a02ee05db46 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283608 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11005 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: BCRD2: Enable Realtek Audio codec on I2C4
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 0a754021cf7eecf385bc6e9885ce57c5b9a33c0d Author: Jenny TC <jenny.tc(a)intel.com> Date: Thu Jun 18 16:06:57 2015 +0530 intel/strago: BCRD2: Enable Realtek Audio codec on I2C4 In BCRD2, RTEK audio codec is connected to I2C4. Create a RTEK device entry on I2C4 to enable Audio on BCRD2. In BCRD1, RTEK device is connected to I2C2. Having two devices with same HID breaks the Audio on BCRD2 even if I2C2.RTEK._STA returns 0. The Audio codec driver in kernel is hard coded to use first instance of the device (:00). When two devices are present with same HID, first device gets an instance number :00 even though _STA returns 0. Second device which is on I2C4 and POR for BCRD2 assigned with instance number :01. The device with :01 is not getting enabled since the Audio codec driver supports only :00. This need a proper fix in kernel which is in the pipeline. Audio on non BCRD2 platforms on Strago build would be disabled since RTEK device is not present on I2C2. BRANCH=None BUG=None TEST=Build and boot the system Change-Id: Ia97d011c951275e6179c8b79a22c496b8169356b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d71a41ee703e6f60299b9e31a408af2ca06d8e24 Original-Change-Id: I4b032e930e46da77474f8f5969e95f9560b3e905 Original-Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285193 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass(a)intel.com> Reviewed-on: http://review.coreboot.org/11003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11003 for details. -gerrit

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Patch merged into coreboot/master: vboot: set software write protect flag
by gerrit＠coreboot.org 23 Jul '15

23 Jul '15

the following patch was just integrated into master: commit 5d8ef4c66173095ecad58c5b5734e9f28340d61a Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Jul 22 11:49:17 2015 -0700 vboot: set software write protect flag TEST=built for samus and veyron_jerry Change-Id: I7173f46d2ed2e323bff227a484c32c4bb6f6c828 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-on: http://review.coreboot.org/11028 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11028 for details. -gerrit

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Patch set updated for coreboot: vboot: set software write protect flag
by Aaron Durbin 22 Jul '15

22 Jul '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11028 -gerrit commit 333ccbd08eab777798bc7c980cda421d9e067e5c Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Jul 22 11:49:17 2015 -0700 vboot: set software write protect flag TEST=built for samus and veyron_jerry Change-Id: I7173f46d2ed2e323bff227a484c32c4bb6f6c828 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index 955d72f..c8ba114 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -38,8 +38,6 @@ /** * Sets vboot_handoff based on the information in vb2_shared_data - * - * TODO: Add VBSD_BOOT_FIRMWARE_SW_WP_ENABLED logic */ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, struct vb2_shared_data *vb2_sd) @@ -63,6 +61,8 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, if (get_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED; + if (vboot_get_sw_write_protect()) + vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED; if (vb2_sd->recovery_reason) { vb_sd->firmware_index = 0xFF;

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Patch set updated for coreboot: t210: change memlayout.ld
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11038 -gerrit commit e551efd328abbb2293973ca0294e2c56f7c4fe90 Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 21 12:48:12 2015 -0700 t210: change memlayout.ld MBIST workaround needs more space in bootblock. bootblock += 4KB; romstage -= 4KB BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I8338d0a134185a425af36e302dcf0ed1520b7e21 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 388523bf4fa25ff3ecf9607ff36ce7c6109485ed Original-Change-Id: Ib08f2ff438f9d96a19b44af1b3e13260966f98f1 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287286 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index dc25775..c140e01 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -37,9 +37,9 @@ SECTIONS VBOOT2_WORK(0x4000B000, 16K) STACK(0x4000F000, 2K) TIMESTAMP(0x4000F800, 2K) - BOOTBLOCK(0x40010000, 24K) - VERSTAGE(0x40016000, 64K) - ROMSTAGE(0x40026000, 104K) + BOOTBLOCK(0x40010000, 28K) + VERSTAGE(0x40017000, 64K) + ROMSTAGE(0x40027000, 100K) SRAM_END(0x40040000) DRAM_START(0x80000000)

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New patch to review for coreboot: t210: audio: add CLK_V_EXTPERIPH1 clock
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11041 -gerrit commit b9f1744d520ce4b1d2150ec8ce792ca2fcaa5e0e Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 14 11:20:08 2015 -0700 t210: audio: add CLK_V_EXTPERIPH1 clock For audio to work, need to enable CLK_V_EXTPERIPH1 clock. This CL is needed because after MBIST workaround is applied, CLK_V_EXTPERIPH1 clock is default to be off. BUG=None BRANCH=None TEST=Tested on Smaug, hear beep when press Ctrl+U at serial console when DEV screen is showing Change-Id: I32dccc0c7983f8fa86812d845a2f00ac9881d521 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 149d04e6ba642734d5ea36cac8206fad3ac13ce0 Original-Change-Id: Ifa1afb0798c1039c8ea9084b5a7ee3b09b4d70ac Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285604 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/clock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 9cbae81..be44bdf 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -791,6 +791,7 @@ void clock_enable_audio(void) */ clock_enable_clear_reset(CLK_L_I2S1 | CLK_L_I2S2 | CLK_L_I2S3 | CLK_L_SPDIF, 0, 0, - CLK_V_I2S4 | CLK_V_I2S5 | CLK_V_AHUB | CLK_V_APB2APE, + CLK_V_I2S4 | CLK_V_I2S5 | CLK_V_AHUB | CLK_V_APB2APE | + CLK_V_EXTPERIPH1, 0, 0, 0); }

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coreboot-gerrit July 2015