coreboot-gerrit July 2015

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New patch to review for coreboot: skylake: sanitize pcr header for ACPI and assembler
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11030 -gerrit commit f885723e9543289ba2d788ce9b244373a7ec5b75 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 20 16:46:19 2015 -0500 skylake: sanitize pcr header for ACPI and assembler Remove the C types and functions from PCR so that pcr.h can be included from assembly and ACPI. While in there make the PCR reg caclulation using a C function and place the P2SB (PCH_PCR_BASE_ADDRESS) address in iomap.h. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I9cde178bcdbf49327ef7892393fc277f6c74f34b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fdf5c77ecfa0ca8d3c45604d15b9dec9a6e85193 Original-Change-Id: I5996efaa9869f8f412e4d45c13f30233384a38b2 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286901 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/include/soc/iomap.h | 3 ++ src/soc/intel/skylake/include/soc/pcr.h | 59 ++++++++++++++----------------- src/soc/intel/skylake/pcr.c | 58 ++++++++++++++++-------------- 3 files changed, 61 insertions(+), 59 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 05c5419..920b6f6 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -24,6 +24,9 @@ #define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define MCFG_BASE_SIZE 0x4000000 +#define PCH_PCR_BASE_ADDRESS 0xfd000000 +#define PCH_BCR_BASE_SIZE 0x1000000 + #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index a6987cb..3f8ee2f 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -20,8 +20,9 @@ * Primary to sideband (P2SB) for private configuration registers (PCR). */ -/* PCH (SunRisePoint LP) */ -#define PCH_PCR_BASE_ADDRESS 0xFD000000 +/* Port Id lives in bits 23:16 and register offset lives in 15:0 of address. */ +#define PCR_PORTID_SHIFT 16 +#define PCR_OFFSET_SHIFT 0 /* DMI Control Register */ #define R_PCH_PCR_DMI_DMIC 0x2234 @@ -70,38 +71,30 @@ #define SIO_PCH_LEGACY_UART2 (1 << 2) /* - * Definition for PCR address - * The PCR address is used to the PCR MMIO programming + * P2SB port ids. */ -#define PCH_PCR_ADDRESS(pid, offset) (void *)(\ - PCH_PCR_BASE_ADDRESS | ((u8)(pid) << 16) | (u16)(offset)) +#define PID_PSTH 0x89 +#define PID_GPIOCOM3 0xAC +#define PID_GPIOCOM2 0xAD +#define PID_GPIOCOM1 0xAE +#define PID_GPIOCOM0 0xAF +#define PID_LPC 0xC7 +#define PID_ITSS 0xC4 +#define PID_RTC 0xC3 +#define PID_SERIALIO 0xCB +#define PID_DMI 0xEF -/* - * Definition for SBI PID - * The PCH_SBI_PID defines the PID for PCR MMIO programming and - * PCH SBI programming as well. - */ -typedef enum { - PID_PSTH = 0x89, - PID_GPIOCOM3 = 0xAC, - PID_GPIOCOM2 = 0xAD, - PID_GPIOCOM1 = 0xAE, - PID_GPIOCOM0 = 0xAF, - PID_LPC = 0xC7, - PID_ITSS = 0xC4, - PID_RTC = 0xC3, - PID_SERIALIO = 0xCB, - PID_DMI = 0xEF, -} PCH_SBI_PID; - -u8 pcr_read32(PCH_SBI_PID pid, u16 offset, u32 *outdata); -u8 pcr_read16(PCH_SBI_PID pid, u16 offset, u16 *outdata); -u8 pcr_read8(PCH_SBI_PID pid, u16 offset, u8 *outdata); -u8 pcr_write32(PCH_SBI_PID pid, u16 offset, u32 indata); -u8 pcr_write16(PCH_SBI_PID pid, u16 offset, u16 indata); -u8 pcr_write8(PCH_SBI_PID pid, u16 offset, u8 indata); -u8 pcr_andthenor32(PCH_SBI_PID pid, u16 offset, u32 anddata, u32 ordata); -u8 pcr_andthenor16(PCH_SBI_PID pid, u16 offset, u16 anddata, u16 ordata); -u8 pcr_andthenor8(PCH_SBI_PID pid, u16 offset, u8 anddata, u8 ordata); +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +/* All these return 0 on success and < 0 on errror. */ +int pcr_read32(u8 pid, u16 offset, u32 *outdata); +int pcr_read16(u8 pid, u16 offset, u16 *outdata); +int pcr_read8(u8 pid, u16 offset, u8 *outdata); +int pcr_write32(u8 pid, u16 offset, u32 indata); +int pcr_write16(u8 pid, u16 offset, u16 indata); +int pcr_write8(u8 pid, u16 offset, u8 indata); +int pcr_andthenor32(u8 pid, u16 offset, u32 anddata, u32 ordata); +int pcr_andthenor16(u8 pid, u16 offset, u16 anddata, u16 ordata); +int pcr_andthenor8(u8 pid, u16 offset, u8 anddata, u8 ordata); +#endif /* if !defined(__ASSEMBLER__) && !defined(__ACPI__) */ #endif /* _SOC_PCR_H_ */ diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 79c32f9..0e97265 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -22,15 +22,24 @@ #include <soc/iomap.h> #include <console/console.h> +static inline void *pcr_reg_address(u8 pid, u16 offset) +{ + uintptr_t reg_addr; + + /* Create an address based off of port id and offset. */ + reg_addr = PCH_PCR_BASE_ADDRESS; + reg_addr += ((uintptr_t)pid) << PCR_PORTID_SHIFT; + reg_addr += ((uintptr_t)offset) << PCR_OFFSET_SHIFT; + + return (void *)reg_addr; +} + /* * Read PCR register. (This is internal function) * It returns PCR register and size in 1/2/4 bytes. * The offset should not exceed 0xFFFF and must be aligned with size - * - * PCH_SBI_PID defines as 8 bit Port ID that will be used when sending - * transaction to sideband. */ -static u8 pch_pcr_read(PCH_SBI_PID pid, u16 offset, u32 size, void *data) +static int pch_pcr_read(u8 pid, u16 offset, u32 size, void *data) { if ((offset & (size - 1)) != 0) { printk(BIOS_DEBUG, @@ -40,13 +49,13 @@ static u8 pch_pcr_read(PCH_SBI_PID pid, u16 offset, u32 size, void *data) } switch (size) { case 4: - *(u32 *) data = read32(PCH_PCR_ADDRESS(pid, offset)); + *(u32 *) data = read32(pcr_reg_address(pid, offset)); break; case 2: - *(u16 *) data = read16(PCH_PCR_ADDRESS(pid, offset)); + *(u16 *) data = read16(pcr_reg_address(pid, offset)); break; case 1: - *(u8 *) data = read8(PCH_PCR_ADDRESS(pid, offset)); + *(u8 *) data = read8(pcr_reg_address(pid, offset)); break; default: break; @@ -54,17 +63,17 @@ static u8 pch_pcr_read(PCH_SBI_PID pid, u16 offset, u32 size, void *data) return 0; } -u8 pcr_read32(PCH_SBI_PID pid, u16 offset, u32 *outdata) +int pcr_read32(u8 pid, u16 offset, u32 *outdata) { return pch_pcr_read(pid, offset, sizeof(u32), (u32 *)outdata); } -u8 pcr_read16(PCH_SBI_PID pid, u16 offset, u16 *outdata) +int pcr_read16(u8 pid, u16 offset, u16 *outdata) { return pch_pcr_read(pid, offset, sizeof(u16), (u32 *)outdata); } -u8 pcr_read8(PCH_SBI_PID pid, u16 offset, u8 *outdata) +int pcr_read8(u8 pid, u16 offset, u8 *outdata) { return pch_pcr_read(pid, offset, sizeof(u8), (u32 *)outdata); } @@ -79,18 +88,15 @@ static inline void complete_write(void) { /* Read the general control and function disable register. */ const size_t R_PCH_PCR_LPC_GCFD = 0x3418; - read32(PCH_PCR_ADDRESS(PID_LPC, R_PCH_PCR_LPC_GCFD)); + read32(pcr_reg_address(PID_LPC, R_PCH_PCR_LPC_GCFD)); } /* * Write PCR register. (This is internal function) * It returns PCR register and size in 1/2/4 bytes. * The offset should not exceed 0xFFFF and must be aligned with size - * - * PCH_SBI_PID defines as 8 bit Port ID that will be used when sending - * transaction to sideband. */ -static u8 pch_pcr_write(PCH_SBI_PID pid, u16 offset, u32 size, u32 data) +static int pch_pcr_write(u8 pid, u16 offset, u32 size, u32 data) { if ((offset & (size - 1)) != 0) { printk(BIOS_DEBUG, @@ -103,13 +109,13 @@ static u8 pch_pcr_write(PCH_SBI_PID pid, u16 offset, u32 size, u32 data) */ switch (size) { case 4: - write32(PCH_PCR_ADDRESS(pid, offset), (u32) data); + write32(pcr_reg_address(pid, offset), (u32) data); break; case 2: - write16(PCH_PCR_ADDRESS(pid, offset), (u16) data); + write16(pcr_reg_address(pid, offset), (u16) data); break; case 1: - write8(PCH_PCR_ADDRESS(pid, offset), (u8) data); + write8(pcr_reg_address(pid, offset), (u8) data); break; default: break; @@ -120,17 +126,17 @@ static u8 pch_pcr_write(PCH_SBI_PID pid, u16 offset, u32 size, u32 data) return 0; } -u8 pcr_write32(PCH_SBI_PID pid, u16 offset, u32 indata) +int pcr_write32(u8 pid, u16 offset, u32 indata) { return pch_pcr_write(pid, offset, sizeof(u32), indata); } -u8 pcr_write16(PCH_SBI_PID pid, u16 offset, u16 indata) +int pcr_write16(u8 pid, u16 offset, u16 indata) { return pch_pcr_write(pid, offset, sizeof(u16), indata); } -u8 pcr_write8(PCH_SBI_PID pid, u16 offset, u8 indata) +int pcr_write8(u8 pid, u16 offset, u8 indata) { return pch_pcr_write(pid, offset, sizeof(u8), indata); } @@ -140,10 +146,10 @@ u8 pcr_write8(PCH_SBI_PID pid, u16 offset, u8 indata) * It programs PCR register and size in 1/2/4 bytes. * The offset should not exceed 0xFFFF and must be aligned with size * - * PCH_SBI_PID defines as 8 bit Port ID that will be used when sending + * u8 defines as 8 bit Port ID that will be used when sending * transaction to sideband. */ -static u8 pcr_and_then_or(PCH_SBI_PID pid, u16 offset, u32 size, u32 anddata, +static int pcr_and_then_or(u8 pid, u16 offset, u32 size, u32 anddata, u32 ordata) { u8 status; @@ -160,17 +166,17 @@ static u8 pcr_and_then_or(PCH_SBI_PID pid, u16 offset, u32 size, u32 anddata, return status; } -u8 pcr_andthenor32(PCH_SBI_PID pid, u16 offset, u32 anddata, u32 ordata) +int pcr_andthenor32(u8 pid, u16 offset, u32 anddata, u32 ordata) { return pcr_and_then_or(pid, offset, sizeof(u32), anddata, ordata); } -u8 pcr_andthenor16(PCH_SBI_PID pid, u16 offset, u16 anddata, u16 ordata) +int pcr_andthenor16(u8 pid, u16 offset, u16 anddata, u16 ordata) { return pcr_and_then_or(pid, offset, sizeof(u16), anddata, ordata); } -u8 pcr_andthenor8(PCH_SBI_PID pid, u16 offset, u8 anddata, u8 ordata) +int pcr_andthenor8(u8 pid, u16 offset, u8 anddata, u8 ordata) { return pcr_and_then_or(pid, offset, sizeof(u8), anddata, ordata); }

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New patch to review for coreboot: skylake: provide more clarity for PCR access
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11029 -gerrit commit fb2f0c0fa2c1a8cb5194ce0cfce2cd63a025eab3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 20 14:28:01 2015 -0500 skylake: provide more clarity for PCR access The current primary to sideband (P2SB) code for private configuration register (PCR) access weren't very clear with the naming or reasoning for some of the code. Provide more verbiage surrounding this interface. BUG=None BRANCH=None TEST=Built and booted glados. Change-Id: I5b2e84444a29b2fc2f527502e8c9f26eb60e687a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 06345ba1abd893059a6584856851f92f43289247 Original-Change-Id: If57a4bbc90365c1135b4986dce328b5dbabe483b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286900 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/include/soc/pcr.h | 5 ++++- src/soc/intel/skylake/pcr.c | 16 +++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index 9ac9edd..a6987cb 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -16,9 +16,12 @@ #ifndef _SOC_PCR_H_ #define _SOC_PCR_H_ +/* + * Primary to sideband (P2SB) for private configuration registers (PCR). + */ + /* PCH (SunRisePoint LP) */ #define PCH_PCR_BASE_ADDRESS 0xFD000000 -#define R_PCH_PCR_LPC_GCFD 0x3418 /* DMI Control Register */ #define R_PCH_PCR_DMI_DMIC 0x2234 diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 33d6cd1..79c32f9 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -70,6 +70,19 @@ u8 pcr_read8(PCH_SBI_PID pid, u16 offset, u8 *outdata) } /* + * After every write one needs to perform a read an innocuous register to + * ensure the writes are completed for certain ports. This is done for + * all ports so that the callers don't need the per-port knowledge for + * each transaction. + */ +static inline void complete_write(void) +{ + /* Read the general control and function disable register. */ + const size_t R_PCH_PCR_LPC_GCFD = 0x3418; + read32(PCH_PCR_ADDRESS(PID_LPC, R_PCH_PCR_LPC_GCFD)); +} + +/* * Write PCR register. (This is internal function) * It returns PCR register and size in 1/2/4 bytes. * The offset should not exceed 0xFFFF and must be aligned with size @@ -101,7 +114,8 @@ static u8 pch_pcr_write(PCH_SBI_PID pid, u16 offset, u32 size, u32 data) default: break; } - read32(PCH_PCR_ADDRESS(PID_LPC, R_PCH_PCR_LPC_GCFD)); + /* Ensure the writes complete. */ + complete_write(); return 0; }

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New patch to review for coreboot: vboot: set software write protect flag
by Daisuke Nojiri 22 Jul '15

22 Jul '15

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11028 -gerrit commit 269efec2f8f4289c9009fb59530eb62f122e1716 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Jul 22 11:49:17 2015 -0700 vboot: set software write protect flag TEST=built for samus and veyron_jerry Change-Id: I7173f46d2ed2e323bff227a484c32c4bb6f6c828 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_handoff.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c index 955d72f..c8ba114 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_handoff.c @@ -38,8 +38,6 @@ /** * Sets vboot_handoff based on the information in vb2_shared_data - * - * TODO: Add VBSD_BOOT_FIRMWARE_SW_WP_ENABLED logic */ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, struct vb2_shared_data *vb2_sd) @@ -63,6 +61,8 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, if (get_write_protect_state()) vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED; + if (vboot_get_sw_write_protect()) + vb_sd->flags |= VBSD_BOOT_FIRMWARE_SW_WP_ENABLED; if (vb2_sd->recovery_reason) { vb_sd->firmware_index = 0xFF;

1 0

Patch set updated for coreboot: tlcl: remove vboot code
by Daisuke Nojiri 22 Jul '15

22 Jul '15

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11019 -gerrit commit 4e06279352a850ae40149610ac922808a8bbcbff Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jul 20 16:43:32 2015 -0700 tlcl: remove vboot code This change removes vboot specific code from tlcl library. BUG=none BRANCH=tot TEST=built for veyron_jerry Change-Id: Id5b4edfcb2d5339071ccd094e4dd8ebdb8929061 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- 3rdparty/blobs | 2 +- src/include/tpm_lite/tlcl.h | 6 ---- src/lib/mocked_tlcl.c | 47 +++++++++++++----------------- src/lib/tlcl.c | 69 ++++++++++++++++++++------------------------- 4 files changed, 52 insertions(+), 72 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 61d663e..612cd24 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 61d663e39bc96530900c3232ccea7365ab9dad0b +Subproject commit 612cd24575ab8bb77260e22f3665f46b77794ffe diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h index 7724592..5bbd303 100644 --- a/src/include/tpm_lite/tlcl.h +++ b/src/include/tpm_lite/tlcl.h @@ -23,12 +23,6 @@ */ uint32_t tlcl_lib_init(void); -/** - * Perform a raw TPM request/response transaction. - */ -uint32_t tlcl_send_receive(const uint8_t *request, uint8_t *response, - int max_length); - /* Commands */ /** diff --git a/src/lib/mocked_tlcl.c b/src/lib/mocked_tlcl.c index c5c12bf..7234080 100644 --- a/src/lib/mocked_tlcl.c +++ b/src/lib/mocked_tlcl.c @@ -17,120 +17,113 @@ * Foundation, Inc. */ -#include <tpm_lite/tlcl.h> - -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else #include <console/console.h> -#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) -#endif +#include <tpm_lite/tlcl.h> uint32_t tlcl_lib_init(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_startup(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_resume(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_self_test_full(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_continue_self_test(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_assert_physical_presence(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_physical_presence_cmd_enable(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_finalize_physical_presence(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_nv_locked(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_force_clear(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_enable(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_deactivated(uint8_t flag) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, uint8_t *nvlocked) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_global_lock(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, uint8_t* out_digest) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } diff --git a/src/lib/tlcl.c b/src/lib/tlcl.c index ccf4e80..7407fce 100644 --- a/src/lib/tlcl.c +++ b/src/lib/tlcl.c @@ -15,21 +15,13 @@ */ #include <assert.h> +#include <console/console.h> #include <string.h> #include <tpm_lite/tlcl.h> #include <tpm.h> -#include <vb2_api.h> #include "tlcl_internal.h" #include "tlcl_structures.h" -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else -#include <console/console.h> -#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) -#endif - static int tpm_send_receive(const uint8_t *request, uint32_t request_length, uint8_t *response, @@ -37,12 +29,12 @@ static int tpm_send_receive(const uint8_t *request, { size_t len = *response_length; if (tis_sendrecv(request, request_length, response, &len)) - return VB2_ERROR_UNKNOWN; + return TPM_E_COMMUNICATION_ERROR; /* check 64->32bit overflow and (re)check response buffer overflow */ if (len > *response_length) - return VB2_ERROR_UNKNOWN; + return TPM_E_RESPONSE_TOO_LARGE; *response_length = len; - return VB2_SUCCESS; + return TPM_SUCCESS; } /* Sets the size field of a TPM command. */ @@ -82,7 +74,7 @@ static uint32_t tlcl_send_receive_no_retry(const uint8_t* request, response, &response_length); if (0 != result) { /* Communication with TPM failed, so response is garbage */ - VBDEBUG("TPM: command 0x%x send/receive failed: 0x%x\n", + printk(BIOS_DEBUG, "TPM: command 0x%x send/receive failed: 0x%x\n", tpm_command_code(request), result); return result; } @@ -93,7 +85,7 @@ static uint32_t tlcl_send_receive_no_retry(const uint8_t* request, * (and possibly expected length from the response header). See * crosbug.com/17017 */ - VBDEBUG("TPM: command 0x%x returned 0x%x\n", + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", tpm_command_code(request), result); return result; @@ -102,8 +94,9 @@ return result; /* Sends a TPM command and gets a response. Returns 0 if success or the TPM * error code if error. Waits for the self test to complete if needed. */ -uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, - int max_length) { +static uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, + int max_length) +{ uint32_t result = tlcl_send_receive_no_retry(request, response, max_length); /* If the command fails because the self test has not completed, try it @@ -115,7 +108,7 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, #if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) /* Retry only once */ result = tlcl_send_receive_no_retry(request, response, - max_length); + max_length); #else /* This needs serious testing. The TPM specification says: "iii. * The caller MUST wait for the actions of TPM_ContinueSelfTest @@ -124,7 +117,7 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, * actions have completed other than trying again? */ do { result = tlcl_send_receive_no_retry(request, response, - max_length); + max_length); } while (result == TPM_E_DOING_SELFTEST); #endif } @@ -141,32 +134,32 @@ static uint32_t send(const uint8_t* command) { uint32_t tlcl_lib_init(void) { if (tis_init()) - return VB2_ERROR_UNKNOWN; + return TPM_E_INVALID_POSTINIT; if (tis_open()) - return VB2_ERROR_UNKNOWN; - return VB2_SUCCESS; + return TPM_E_INVALID_POSTINIT; + return TPM_SUCCESS; } uint32_t tlcl_startup(void) { - VBDEBUG("TPM: Startup\n"); + printk(BIOS_DEBUG, "TPM: Startup\n"); return send(tpm_startup_cmd.buffer); } uint32_t tlcl_resume(void) { - VBDEBUG("TPM: Resume\n"); - return send(tpm_resume_cmd.buffer); + printk(BIOS_DEBUG, "TPM: Resume\n"); + return send(tpm_resume_cmd.buffer); } uint32_t tlcl_self_test_full(void) { - VBDEBUG("TPM: Self test full\n"); + printk(BIOS_DEBUG, "TPM: Self test full\n"); return send(tpm_selftestfull_cmd.buffer); } uint32_t tlcl_continue_self_test(void) { uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - VBDEBUG("TPM: Continue self test\n"); + printk(BIOS_DEBUG, "TPM: Continue self test\n"); /* Call the No Retry version of SendReceive to avoid recursion. */ return tlcl_send_receive_no_retry(tpm_continueselftest_cmd.buffer, response, sizeof(response)); @@ -175,7 +168,7 @@ uint32_t tlcl_continue_self_test(void) uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) { struct s_tpm_nv_definespace_cmd cmd; - VBDEBUG("TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size); + printk(BIOS_DEBUG, "TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size); memcpy(&cmd, &tpm_nv_definespace_cmd, sizeof(cmd)); to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.perm, perm); @@ -190,7 +183,7 @@ uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) const int total_length = kTpmRequestHeaderLength + kWriteInfoLength + length; - VBDEBUG("TPM: tlcl_write(0x%x, %d)\n", index, length); + printk(BIOS_DEBUG, "TPM: tlcl_write(0x%x, %d)\n", index, length); memcpy(&cmd, &tpm_nv_write_cmd, sizeof(cmd)); assert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); set_tpm_command_size(cmd.buffer, total_length); @@ -209,7 +202,7 @@ uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) uint32_t result_length; uint32_t result; - VBDEBUG("TPM: tlcl_read(0x%x, %d)\n", index, length); + printk(BIOS_DEBUG, "TPM: tlcl_read(0x%x, %d)\n", index, length); memcpy(&cmd, &tpm_nv_read_cmd, sizeof(cmd)); to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.length, length); @@ -227,39 +220,39 @@ uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) uint32_t tlcl_assert_physical_presence(void) { - VBDEBUG("TPM: Asserting physical presence\n"); + printk(BIOS_DEBUG, "TPM: Asserting physical presence\n"); return send(tpm_ppassert_cmd.buffer); } uint32_t tlcl_physical_presence_cmd_enable(void) { - VBDEBUG("TPM: Enable the physical presence command\n"); + printk(BIOS_DEBUG, "TPM: Enable the physical presence command\n"); return send(tpm_ppenable_cmd.buffer); } uint32_t tlcl_finalize_physical_presence(void) { - VBDEBUG("TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n"); + printk(BIOS_DEBUG, "TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n"); return send(tpm_finalizepp_cmd.buffer); } uint32_t tlcl_set_nv_locked(void) { - VBDEBUG("TPM: Set NV locked\n"); + printk(BIOS_DEBUG, "TPM: Set NV locked\n"); return tlcl_define_space(TPM_NV_INDEX_LOCK, 0, 0); } uint32_t tlcl_force_clear(void) { - VBDEBUG("TPM: Force clear\n"); + printk(BIOS_DEBUG, "TPM: Force clear\n"); return send(tpm_forceclear_cmd.buffer); } uint32_t tlcl_set_enable(void) { - VBDEBUG("TPM: Enabling TPM\n"); + printk(BIOS_DEBUG, "TPM: Enabling TPM\n"); return send(tpm_physicalenable_cmd.buffer); } uint32_t tlcl_set_deactivated(uint8_t flag) { struct s_tpm_physicalsetdeactivated_cmd cmd; - VBDEBUG("TPM: SetDeactivated(%d)\n", flag); + printk(BIOS_DEBUG, "TPM: SetDeactivated(%d)\n", flag); memcpy(&cmd, &tpm_physicalsetdeactivated_cmd, sizeof(cmd)); *(cmd.buffer + cmd.deactivated) = flag; return send(cmd.buffer); @@ -292,7 +285,7 @@ uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, *deactivated = pflags.deactivated; if (nvlocked) *nvlocked = pflags.nvLocked; - VBDEBUG("TPM: flags disable=%d, deactivated=%d, nvlocked=%d\n", + printk(BIOS_DEBUG, "TPM: flags disable=%d, deactivated=%d, nvlocked=%d\n", pflags.disable, pflags.deactivated, pflags.nvLocked); } return result; @@ -301,7 +294,7 @@ uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, uint32_t tlcl_set_global_lock(void) { uint32_t x; - VBDEBUG("TPM: Set global lock\n"); + printk(BIOS_DEBUG, "TPM: Set global lock\n"); return tlcl_write(TPM_NV_INDEX0, (uint8_t*) &x, 0); }

1 0

Patch merged into coreboot/master: amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines
by gerrit＠coreboot.org 22 Jul '15

22 Jul '15

the following patch was just integrated into master: commit df5446196cd81c4a714f45f92fb379c795c1edb5 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Jul 17 07:47:41 2015 -0500 amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines Moves the K8 CPU_ADDR_BITS definition from socket to model. Previously socket_F was not setting CPU_ADDR_BITS correctly. Tested on Sun Ultra 40 M2 with two 2nd-gen Opterons w/ 2x4x2GiB DIMMs. Most if not all K8-based chips support 40-bit physical addresses, with possible exception of IA32-only K8-based Athlon XP-M chips. Probably irrelevant, unless your machine has enough memory (at least 60 to 64GiB before MMIO hoisting) to exceed the CPU_ADDR_BITS default of 36 from src/cpu/x86/Kconfig. Change-Id: I01a2a59fa902280171840c36ca2e631476d3d603 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10963 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10963 for details. -gerrit

1 0

New patch to review for coreboot: ddr3 spd: account fine timebase
by Patrick Rudolph 22 Jul '15

22 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11027 -gerrit commit 610ae59fcdc00ecfadb6bf3612262e0920d5dc60 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Jul 15 10:03:30 2015 +0200 ddr3 spd: account fine timebase SPD revision 1.1 adds optional fine timebase adjustments. Check SPD revision and apply the correction values. Change-Id: I3576821af5e78d2e9ea4d583a59dcc90cef6995f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index e1bb873..ee13de7 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -113,7 +113,9 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width; u8 reg8; u32 mtb; /* medium time base */ + u32 ftb; /* fine time base */ unsigned int val, param; + char *comp; ret = SPD_STATUS_OK; @@ -239,12 +241,6 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width * dimm->ranks) / dimm->width; - /* Fine Timebase (FTB) Dividend/Divisor */ - /* Dividend */ - ftb_dividend = (spd[9] >> 4) & 0x0f; - /* Divisor */ - ftb_divisor = spd[9] & 0x0f; - /* Medium Timebase = * Medium Timebase (MTB) Dividend / * Medium Timebase (MTB) Divisor */ @@ -277,6 +273,30 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* Minimum Four Activate Window Delay Time (tFAWmin) */ dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + /* Dividend */ + ftb_dividend = (spd[9] >> 4) & 0x0f; + /* Divisor */ + ftb_divisor = spd[9] & 0x0f; + + /* SPD Revision 1.1 */ + if (((spd[1] & 0xf0) == 0x10) && ((spd[1] & 0x0f) > 0) && + ftb_dividend && ftb_divisor) { + comp = (char *) &spd[34]; + /* Fine Timebase (FTB) 1/256 ps Dividend/Divisor */ + ftb = (ftb_dividend << 8) / ftb_divisor; + + /* SDRAM Minimum Cycle Time (tCKmin) correction */ + dimm->tCK += (comp[0] * ftb) / 1000; + /* Minimum CAS Latency Time (tAAmin) correction */ + dimm->tAA += (comp[1] * ftb) / 1000; + /* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */ + dimm->tRCD += (comp[2] * ftb) / 1000; + /* Minimum Row Precharge Delay Time (tRPmin) correction */ + dimm->tRP += (comp[3] * ftb) / 1000; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) correction */ + dimm->tRC += (comp[4] * ftb) / 1000; + } + /* SDRAM Optional Features */ reg8 = spd[30]; printram(" Optional features :");

1 0

Patch set updated for coreboot: tlcl: remove vboot code
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11019 -gerrit commit d40a72da6409aa9300232596cd37909c5ae92e25 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jul 20 16:43:32 2015 -0700 tlcl: remove vboot code This change removes vboot specific code from tlcl library. BUG=none BRANCH=tot TEST=built for veyron_jerry Change-Id: Id5b4edfcb2d5339071ccd094e4dd8ebdb8929061 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- 3rdparty/blobs | 2 +- src/include/tpm_lite/tlcl.h | 6 ---- src/lib/mocked_tlcl.c | 47 +++++++++++++----------------- src/lib/tlcl.c | 69 ++++++++++++++++++++------------------------- 4 files changed, 52 insertions(+), 72 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 61d663e..612cd24 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 61d663e39bc96530900c3232ccea7365ab9dad0b +Subproject commit 612cd24575ab8bb77260e22f3665f46b77794ffe diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h index 7724592..5bbd303 100644 --- a/src/include/tpm_lite/tlcl.h +++ b/src/include/tpm_lite/tlcl.h @@ -23,12 +23,6 @@ */ uint32_t tlcl_lib_init(void); -/** - * Perform a raw TPM request/response transaction. - */ -uint32_t tlcl_send_receive(const uint8_t *request, uint8_t *response, - int max_length); - /* Commands */ /** diff --git a/src/lib/mocked_tlcl.c b/src/lib/mocked_tlcl.c index c5c12bf..7234080 100644 --- a/src/lib/mocked_tlcl.c +++ b/src/lib/mocked_tlcl.c @@ -17,120 +17,113 @@ * Foundation, Inc. */ -#include <tpm_lite/tlcl.h> - -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else #include <console/console.h> -#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) -#endif +#include <tpm_lite/tlcl.h> uint32_t tlcl_lib_init(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_startup(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_resume(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_self_test_full(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_continue_self_test(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_assert_physical_presence(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_physical_presence_cmd_enable(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_finalize_physical_presence(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_nv_locked(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_force_clear(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_enable(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_deactivated(uint8_t flag) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_get_permanent_flags(TPM_PERMANENT_FLAGS* pflags) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, uint8_t *nvlocked) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_set_global_lock(void) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } uint32_t tlcl_extend(int pcr_num, const uint8_t* in_digest, uint8_t* out_digest) { - VBDEBUG("MOCK_TPM: %s\n", __func__); + printk(BIOS_DEBUG, "MOCK_TPM: %s\n", __func__); return TPM_E_NO_DEVICE; } diff --git a/src/lib/tlcl.c b/src/lib/tlcl.c index ccf4e80..7407fce 100644 --- a/src/lib/tlcl.c +++ b/src/lib/tlcl.c @@ -15,21 +15,13 @@ */ #include <assert.h> +#include <console/console.h> #include <string.h> #include <tpm_lite/tlcl.h> #include <tpm.h> -#include <vb2_api.h> #include "tlcl_internal.h" #include "tlcl_structures.h" -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else -#include <console/console.h> -#define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) -#endif - static int tpm_send_receive(const uint8_t *request, uint32_t request_length, uint8_t *response, @@ -37,12 +29,12 @@ static int tpm_send_receive(const uint8_t *request, { size_t len = *response_length; if (tis_sendrecv(request, request_length, response, &len)) - return VB2_ERROR_UNKNOWN; + return TPM_E_COMMUNICATION_ERROR; /* check 64->32bit overflow and (re)check response buffer overflow */ if (len > *response_length) - return VB2_ERROR_UNKNOWN; + return TPM_E_RESPONSE_TOO_LARGE; *response_length = len; - return VB2_SUCCESS; + return TPM_SUCCESS; } /* Sets the size field of a TPM command. */ @@ -82,7 +74,7 @@ static uint32_t tlcl_send_receive_no_retry(const uint8_t* request, response, &response_length); if (0 != result) { /* Communication with TPM failed, so response is garbage */ - VBDEBUG("TPM: command 0x%x send/receive failed: 0x%x\n", + printk(BIOS_DEBUG, "TPM: command 0x%x send/receive failed: 0x%x\n", tpm_command_code(request), result); return result; } @@ -93,7 +85,7 @@ static uint32_t tlcl_send_receive_no_retry(const uint8_t* request, * (and possibly expected length from the response header). See * crosbug.com/17017 */ - VBDEBUG("TPM: command 0x%x returned 0x%x\n", + printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n", tpm_command_code(request), result); return result; @@ -102,8 +94,9 @@ return result; /* Sends a TPM command and gets a response. Returns 0 if success or the TPM * error code if error. Waits for the self test to complete if needed. */ -uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, - int max_length) { +static uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, + int max_length) +{ uint32_t result = tlcl_send_receive_no_retry(request, response, max_length); /* If the command fails because the self test has not completed, try it @@ -115,7 +108,7 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, #if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) /* Retry only once */ result = tlcl_send_receive_no_retry(request, response, - max_length); + max_length); #else /* This needs serious testing. The TPM specification says: "iii. * The caller MUST wait for the actions of TPM_ContinueSelfTest @@ -124,7 +117,7 @@ uint32_t tlcl_send_receive(const uint8_t* request, uint8_t* response, * actions have completed other than trying again? */ do { result = tlcl_send_receive_no_retry(request, response, - max_length); + max_length); } while (result == TPM_E_DOING_SELFTEST); #endif } @@ -141,32 +134,32 @@ static uint32_t send(const uint8_t* command) { uint32_t tlcl_lib_init(void) { if (tis_init()) - return VB2_ERROR_UNKNOWN; + return TPM_E_INVALID_POSTINIT; if (tis_open()) - return VB2_ERROR_UNKNOWN; - return VB2_SUCCESS; + return TPM_E_INVALID_POSTINIT; + return TPM_SUCCESS; } uint32_t tlcl_startup(void) { - VBDEBUG("TPM: Startup\n"); + printk(BIOS_DEBUG, "TPM: Startup\n"); return send(tpm_startup_cmd.buffer); } uint32_t tlcl_resume(void) { - VBDEBUG("TPM: Resume\n"); - return send(tpm_resume_cmd.buffer); + printk(BIOS_DEBUG, "TPM: Resume\n"); + return send(tpm_resume_cmd.buffer); } uint32_t tlcl_self_test_full(void) { - VBDEBUG("TPM: Self test full\n"); + printk(BIOS_DEBUG, "TPM: Self test full\n"); return send(tpm_selftestfull_cmd.buffer); } uint32_t tlcl_continue_self_test(void) { uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - VBDEBUG("TPM: Continue self test\n"); + printk(BIOS_DEBUG, "TPM: Continue self test\n"); /* Call the No Retry version of SendReceive to avoid recursion. */ return tlcl_send_receive_no_retry(tpm_continueselftest_cmd.buffer, response, sizeof(response)); @@ -175,7 +168,7 @@ uint32_t tlcl_continue_self_test(void) uint32_t tlcl_define_space(uint32_t index, uint32_t perm, uint32_t size) { struct s_tpm_nv_definespace_cmd cmd; - VBDEBUG("TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size); + printk(BIOS_DEBUG, "TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size); memcpy(&cmd, &tpm_nv_definespace_cmd, sizeof(cmd)); to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_definespace_cmd.perm, perm); @@ -190,7 +183,7 @@ uint32_t tlcl_write(uint32_t index, const void* data, uint32_t length) const int total_length = kTpmRequestHeaderLength + kWriteInfoLength + length; - VBDEBUG("TPM: tlcl_write(0x%x, %d)\n", index, length); + printk(BIOS_DEBUG, "TPM: tlcl_write(0x%x, %d)\n", index, length); memcpy(&cmd, &tpm_nv_write_cmd, sizeof(cmd)); assert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); set_tpm_command_size(cmd.buffer, total_length); @@ -209,7 +202,7 @@ uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) uint32_t result_length; uint32_t result; - VBDEBUG("TPM: tlcl_read(0x%x, %d)\n", index, length); + printk(BIOS_DEBUG, "TPM: tlcl_read(0x%x, %d)\n", index, length); memcpy(&cmd, &tpm_nv_read_cmd, sizeof(cmd)); to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.index, index); to_tpm_uint32(cmd.buffer + tpm_nv_read_cmd.length, length); @@ -227,39 +220,39 @@ uint32_t tlcl_read(uint32_t index, void* data, uint32_t length) uint32_t tlcl_assert_physical_presence(void) { - VBDEBUG("TPM: Asserting physical presence\n"); + printk(BIOS_DEBUG, "TPM: Asserting physical presence\n"); return send(tpm_ppassert_cmd.buffer); } uint32_t tlcl_physical_presence_cmd_enable(void) { - VBDEBUG("TPM: Enable the physical presence command\n"); + printk(BIOS_DEBUG, "TPM: Enable the physical presence command\n"); return send(tpm_ppenable_cmd.buffer); } uint32_t tlcl_finalize_physical_presence(void) { - VBDEBUG("TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n"); + printk(BIOS_DEBUG, "TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n"); return send(tpm_finalizepp_cmd.buffer); } uint32_t tlcl_set_nv_locked(void) { - VBDEBUG("TPM: Set NV locked\n"); + printk(BIOS_DEBUG, "TPM: Set NV locked\n"); return tlcl_define_space(TPM_NV_INDEX_LOCK, 0, 0); } uint32_t tlcl_force_clear(void) { - VBDEBUG("TPM: Force clear\n"); + printk(BIOS_DEBUG, "TPM: Force clear\n"); return send(tpm_forceclear_cmd.buffer); } uint32_t tlcl_set_enable(void) { - VBDEBUG("TPM: Enabling TPM\n"); + printk(BIOS_DEBUG, "TPM: Enabling TPM\n"); return send(tpm_physicalenable_cmd.buffer); } uint32_t tlcl_set_deactivated(uint8_t flag) { struct s_tpm_physicalsetdeactivated_cmd cmd; - VBDEBUG("TPM: SetDeactivated(%d)\n", flag); + printk(BIOS_DEBUG, "TPM: SetDeactivated(%d)\n", flag); memcpy(&cmd, &tpm_physicalsetdeactivated_cmd, sizeof(cmd)); *(cmd.buffer + cmd.deactivated) = flag; return send(cmd.buffer); @@ -292,7 +285,7 @@ uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, *deactivated = pflags.deactivated; if (nvlocked) *nvlocked = pflags.nvLocked; - VBDEBUG("TPM: flags disable=%d, deactivated=%d, nvlocked=%d\n", + printk(BIOS_DEBUG, "TPM: flags disable=%d, deactivated=%d, nvlocked=%d\n", pflags.disable, pflags.deactivated, pflags.nvLocked); } return result; @@ -301,7 +294,7 @@ uint32_t tlcl_get_flags(uint8_t* disable, uint8_t* deactivated, uint32_t tlcl_set_global_lock(void) { uint32_t x; - VBDEBUG("TPM: Set global lock\n"); + printk(BIOS_DEBUG, "TPM: Set global lock\n"); return tlcl_write(TPM_NV_INDEX0, (uint8_t*) &x, 0); }

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Patch merged into coreboot/master: riscv: Link in libgcc
by gerrit＠coreboot.org 22 Jul '15

22 Jul '15

the following patch was just integrated into master: commit 3332f33009c41f36b6db9d691eb3ea506ea2e4e4 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Jul 18 00:25:12 2015 +0200 riscv: Link in libgcc The new toolchain depends on it. Change-Id: I9070925eeb3f63a6c31e7474ffb9cba15884703d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10976 for details. -gerrit

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Patch merged into coreboot/master: winent/mb6047: move power_on_after_fail out of RTC century byte
by gerrit＠coreboot.org 22 Jul '15

22 Jul '15

the following patch was just integrated into master: commit d4c700806cdb339bafe743dcd006adf70c141e32 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 13 10:39:44 2015 -0500 winent/mb6047: move power_on_after_fail out of RTC century byte Change-Id: I3cf6a579f4e62a59828e81aa63c3a1a020a15ea6 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/10906 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10906 for details. -gerrit

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Patch merged into coreboot/master: lib/hexdump: Add xxd hint
by gerrit＠coreboot.org 22 Jul '15

22 Jul '15

the following patch was just integrated into master: commit 1b0ab813036b45a3d760112f831d41772b81f882 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 14 14:50:42 2015 -0700 lib/hexdump: Add xxd hint For people new to Linux, add the xxd hint to compare output with output from Linux. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: Ia46aeed056b12abbadf8205b044944385d9410e1 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/10207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10207 for details. -gerrit

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coreboot-gerrit July 2015