coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: t210: Enable WRAP to INCR burst type conversion in MSELECT
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11040 -gerrit commit c37c82989ebd398a8c974b0fde2bb9fd54a17c6a Author: Yen Lin <yelin(a)nvidia.com> Date: Thu May 7 12:28:43 2015 -0700 t210: Enable WRAP to INCR burst type conversion in MSELECT Enable WRAP to INCR burst type conversion in MSELECT. MSELECT CONFIG register can only be accessed by CPU. So do it in ramstage when CPU is started. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: Iee05531c45e566f47af24870be6068247c2d9a00 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 21d9e4d3a8827f7bba57c03ca36b702aaba1ce20 Original-Change-Id: I6a241455b28f24b8756ad09bf7605a2e7e52af57 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282418 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/include/soc/addressmap.h | 1 + src/soc/nvidia/tegra210/ramstage.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 66888c6..c3af00c 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -35,6 +35,7 @@ enum { TEGRA_ARM_PERIPHBASE = 0x50040000, TEGRA_GICD_BASE = 0x50041000, TEGRA_GICC_BASE = 0x50042000, + TEGRA_MSELECT_CONFIG = 0x50060000, TEGRA_ARM_DISPLAYA = 0x54200000, TEGRA_ARM_DISPLAYB = 0x54240000, TEGRA_DSIA_BASE = 0x54300000, diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 7838c69..f37c817 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -31,8 +31,30 @@ void arm64_arch_timer_init(void) set_cntfrq(freq); } +static void mselect_enable_wrap(void) +{ + uint32_t reg; + +#define ERR_RESP_EN_SLAVE1 (0x1 << 24) +#define ERR_RESP_EN_SLAVE2 (0x1 << 25) +#define WRAP_TO_INCR_SLAVE0 (0x1 << 27) +#define WRAP_TO_INCR_SLAVE1 (0x1 << 28) +#define WRAP_TO_INCR_SLAVE2 (0x1 << 29) + + reg = read32((void *)TEGRA_MSELECT_CONFIG); + /* Disable error mechanism */ + reg &= ~(ERR_RESP_EN_SLAVE1 | ERR_RESP_EN_SLAVE2); + /* Enable WRAP type conversion */ + reg |= (WRAP_TO_INCR_SLAVE0 | WRAP_TO_INCR_SLAVE1 | + WRAP_TO_INCR_SLAVE2); + write32((void *)TEGRA_MSELECT_CONFIG, reg); +} + void arm64_soc_init(void) { + /* Enable WRAP to INCR burst type conversion in MSELECT */ + mselect_enable_wrap(); + trustzone_region_init(); tegra210_mmu_init();

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New patch to review for coreboot: t210: implement MBIST workaround
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11039 -gerrit commit e92b69e151717fc148b58f2b8e773a84d6bf331b Author: Yen Lin <yelin(a)nvidia.com> Date: Wed May 6 18:08:22 2015 -0700 t210: implement MBIST workaround MBIST has left some registers in non-suggested states. This CL restores CAR CE's, SLCG overrides & PLLD settings. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I1ddb19dd9fb6d8fb4d36e67eedeb847c6fd9f774 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 37a1c90c6deb351b2ae2caa03e5076553126744b Original-Change-Id: I613b4ef622d64305d436cb8379a5170b0fe1c9af Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282417 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/bootblock.c | 104 ++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index a6aa584..0469320 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -22,6 +22,7 @@ #include <arch/stages.h> #include <bootblock_common.h> #include <console/console.h> +#include <delay.h> #include <program_loading.h> #include <soc/addressmap.h> #include <soc/clock.h> @@ -58,11 +59,113 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void) /* Empty default implementation. */ } +/* + * Define operations for the workaround: + * OP_SET : [reg] = val; + * OP_OR : [reg] |= val; + * OP_AND : [reg] &= val; + * OP_UDELAY : udelay(val); + */ +typedef enum { + OP_SET, + OP_OR, + OP_AND, + OP_UDELAY, /* use val field as usec delay */ +} WAR_OP; + +struct workaround_op { + WAR_OP op; + u32 reg; + u32 val; +}; + +/* + * An array defines the sequence to perform the workaround + */ +static struct workaround_op workaround_sequence[] = { + {OP_OR, 0x60006410, (1 << 15)}, /* CLK_SOURCE_SOR1: */ + {OP_AND, 0x60006410, ~(1 << 14)}, /* CLK_SEL1=1, CLK_SEL0=0 */ + {OP_OR, 0x600060d0, 0x40800000}, /* PLLD_BASE */ + {OP_SET, 0x600062ac, 0x40}, /* clear APE reset */ + {OP_SET, 0x60006294, 0x40000}, /* clear VIC reset */ + {OP_SET, 0x60006304, 0x18000000}, /* clear HOST1X & DISP1 reset */ + {OP_UDELAY, 0, 2}, + {OP_OR, 0x702d10a0, 0x400}, /* I2S0: I2S_CTRL.MASTER=1 */ + {OP_AND, 0x702d1088, ~1}, /* I2S0: I2S_CG.SLCG_ENABLE=0 */ + {OP_OR, 0x702d11a0, 0x400}, /* I2S1: I2S_CTRL.MASTER=1 */ + {OP_AND, 0x702d1188, ~1}, /* I2S1: I2S_CG.SLCG_ENABLE=0 */ + {OP_OR, 0x702d12a0, 0x400}, /* I2S2: I2S_CTRL.MASTER=1 */ + {OP_AND, 0x702d1288, ~1}, /* I2S2: I2S_CG.SLCG_ENABLE=0 */ + {OP_OR, 0x702d13a0, 0x400}, /* I2S3: I2S_CTRL.MASTER=1 */ + {OP_AND, 0x702d1388, ~1}, /* I2S3: I2S_CG.SLCG_ENABLE=0 */ + {OP_OR, 0x702d14a0, 0x400}, /* I2S4: I2S_CTRL.MASTER=1 */ + {OP_AND, 0x702d1488, ~1}, /* I2S4: I2S_CG.SLCG_ENABLE=0 */ + {OP_OR, 0x54200cf8, 4}, /* DC_COM_DSC_TOP_CTL[DSC_SLCG_OVERRIDE]=1 */ + {OP_SET, 0x543400c8, 0xffffffff}, /* NV_PVIC_THI_SLCG_OVERRIDE_LOW_A = 0xFFFF_FFFF */ + {OP_UDELAY, 0, 2}, + {OP_SET, 0x600062a8, 0x40}, /* set APE reset */ + {OP_SET, 0x60006300, 0x18000000}, /* set HOST1X & DISP1 reset */ + {OP_SET, 0x60006290, 0x40000}, /* set VIC reset */ + {OP_SET, 0x60006014, 0x020000c1}, /* CLK_ENB_H */ + {OP_SET, 0x60006010, 0x80400130}, /* CLK_ENB_L */ + {OP_SET, 0x60006018, 0x01f00200}, /* CLK_ENB_U */ + {OP_SET, 0x60006360, 0x80400808}, /* CLK_ENB_V */ + {OP_SET, 0x60006364, 0x402000fc}, /* CLK_ENB_W */ + {OP_SET, 0x60006280, 0x23000780}, /* CLK_ENB_X */ + {OP_SET, 0x60006298, 0x00000340}, /* CLK_ENB_Y */ + {OP_SET, 0x600060f8, 0x00000000}, /* LVL2_CLK_GATE_OVRA */ + {OP_SET, 0x600060fc, 0x00000000}, /* LVL2_CLK_GATE_OVRB */ + {OP_SET, 0x600063a0, 0x00000000}, /* LVL2_CLK_GATE_OVRC */ + {OP_SET, 0x600063a4, 0x01000000}, /* LVL2_CLK_GATE_OVRD, QSPI_CLK_OVR_ON=1 */ + {OP_SET, 0x60006554, 0x00000000}, /* LVL2_CLK_GATE_OVRE */ + {OP_AND, 0x600060d0, 0x1f7fffff}, /* PLLD_BASE: 31,30,29,23 = 0 */ + {OP_AND, 0x60006410, 0xffff3fff}, /* CLK_SOURCE_SOR1 15,14 = 0 */ + {OP_AND, 0x60006148, ~(7 << 29)}, /* CLK_SOURCE_VI: */ + {OP_OR, 0x60006148, (4 << 29)}, /* SRC=PLLP_OUT0 (4) */ + {OP_AND, 0x60006180, ~(7 << 29)}, /* CLK_SOURCE_HOST1X: */ + {OP_OR, 0x60006180, (4 << 29)}, /* SRC=PLLP_OUT0 (4) */ + {OP_AND, 0x600066a0, ~(7 << 29)}, /* CLK_SOURCE_NVENC: */ + {OP_OR, 0x600066a0, (4 << 29)} /* SRC=PLLP_OUT0 (4) */ +}; + +/* + * This workaround is to restore CAR CE's, SLCG overrides & PLLD settings + */ +static void mbist_workaround(void) +{ + int i; + u32 val; + struct workaround_op *wa_op; + + for (i = 0; i < ARRAY_SIZE(workaround_sequence); ++i) { + wa_op = &workaround_sequence[i]; + switch (wa_op->op) { + case OP_SET: + val = wa_op->val; + break; + case OP_OR: + val = read32((void *)wa_op->reg) | wa_op->val; + break; + case OP_AND: + val = read32((void *)wa_op->reg) & wa_op->val; + break; + case OP_UDELAY: + udelay(wa_op->val); + /* fall thru */ + default: + continue; + } + write32((void *)wa_op->reg, val); + } +} + void main(void) { // enable JTAG at the earliest stage enable_jtag(); + mbist_workaround(); + clock_early_uart(); /* Configure mselect clock. */ @@ -90,6 +193,7 @@ void main(void) pmc_print_rst_status(); + bootblock_mainboard_init(); printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n");

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New patch to review for coreboot: t210: change memlayout.ld
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11038 -gerrit commit 30df376f5859fefed9edd44b82a796d98953b4e4 Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 21 12:48:12 2015 -0700 t210: change memlayout.ld MBIST workaround needs more space in bootblock. bootblock +=4KB; romstage -= 4KB BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I8338d0a134185a425af36e302dcf0ed1520b7e21 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 388523bf4fa25ff3ecf9607ff36ce7c6109485ed Original-Change-Id: Ib08f2ff438f9d96a19b44af1b3e13260966f98f1 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287286 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index dc25775..c140e01 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -37,9 +37,9 @@ SECTIONS VBOOT2_WORK(0x4000B000, 16K) STACK(0x4000F000, 2K) TIMESTAMP(0x4000F800, 2K) - BOOTBLOCK(0x40010000, 24K) - VERSTAGE(0x40016000, 64K) - ROMSTAGE(0x40026000, 104K) + BOOTBLOCK(0x40010000, 28K) + VERSTAGE(0x40017000, 64K) + ROMSTAGE(0x40027000, 100K) SRAM_END(0x40040000) DRAM_START(0x80000000)

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New patch to review for coreboot: t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11037 -gerrit commit 8a22bea2b2c24197fb9c05e0feb9a12a2e52c322 Author: Yen Lin <yelin(a)nvidia.com> Date: Thu Jul 16 10:23:34 2015 -0700 t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0 Like in cold boot path, need to set CAR2PMC_CPU_ACK_WIDTH to 0 in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: Iffd7fa4d0266e2ec482ec17e5203ceff8afe748f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 052b649b1e6a4e34d621d710ee43aec7149ab8a8 Original-Change-Id: Icdf9879469485fb37b820b30c9663eda528ac013 Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286600 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Tom Warren <twarren(a)nvidia.com> --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 168c95a..dc61cba 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -146,6 +146,13 @@ enum { CLK_ENB_CSITE = 0x1 << 9 }; +static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr = + (void *)(CLK_RST_BASE + 0x388); +enum { + CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0, + CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT +}; + static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); enum { CLK_ENB_CPUG = 0x1 << 0, @@ -787,6 +794,9 @@ void lp0_resume(void) /* Disable PLLX since it isn't used in the kernel as CPU clk source. */ clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr); + /* Set CAR2PMC_CPU_ACK_WIDTH to 0 */ + clrbits32(CAR2PMC_CPU_ACK_WIDTH_MASK, clk_rst_cpu_softrst_ctrl2_ptr); + /* Clear PMC_SCRATCH190 */ clrbits32(1, pmc_scratch190_ptr);

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New patch to review for coreboot: Enable VIRTUAL_DEV_SWITCH
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11036 -gerrit commit 9d160815eb8f2788f0aeea7229a969c15456c10f Author: Jonathan Dixon <joth(a)google.com> Date: Tue Jul 21 12:04:05 2015 -0700 Enable VIRTUAL_DEV_SWITCH BUG=chrome-os-partner:43022 TEST=None BRANCH=None Change-Id: I41c904603e7213da1c8d8e0945b572f6ba844031 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d91722317ffc55a4848e8e3bdac8412218fe1dc4 Original-Change-Id: I1ed4c7aaa35158815f8f7a94eafb77db55a381d0 Original-Signed-off-by: joth(a)chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/287300 Original-Reviewed-by: Jason Simmons <jsimmons(a)chromium.org> Original-Reviewed-by: Karl Townsend <karlt(a)chromium.org> --- src/mainboard/google/veyron_rialto/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 1886db9..42ecb97 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SPI_FLASH select SPI_FLASH_GIGADEVICE select SPI_FLASH_WINBOND + select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string

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New patch to review for coreboot: glados: Fix the write protect GPIO exported in ACPI
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11035 -gerrit commit 2d134e899f7d3dd77759d39ca386c10b05e80e31 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 17:39:25 2015 -0700 glados: Fix the write protect GPIO exported in ACPI Update the write protect GPIO reported in ACPI to be 71 which is GPP_C23. Also update the controller id to INT344B:00 which will point at the sunrisepoint device in /sys/class/gpio. BUG=chrome-os-partner:42560 BRANCH=none TEST=verify crossystem output with and without WP enabled Change-Id: I625859bd8ac371a5c0cae18697dccf216c26a8b6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8fc5cb6b72dacd6aefe69fe8204f4e0d209ed8a4 Original-Change-Id: I04892e75f9bfe739c44eb40e7c6a969c33e157ca Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286842 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/acpi/chromeos.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl index 2d8146c..8edbff3 100644 --- a/src/mainboard/google/glados/acpi/chromeos.asl +++ b/src/mainboard/google/glados/acpi/chromeos.asl @@ -18,6 +18,6 @@ */ Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button - Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect + Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, // no recovery button + Package () { 0x0003, 1, 71, "INT344B:00" }, // firmware write protect })

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New patch to review for coreboot: glados: Add SPD manufacturer and part number
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11034 -gerrit commit 6a1d33ed5d786993e242b2d66a386cc39e9309d5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 16:59:20 2015 -0700 glados: Add SPD manufacturer and part number The FSP memory info hob does not return this data so we need to supply it from the SPD included with the mainboard. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=execute "mosys memory spd print all" on glados Change-Id: Idfb71d36d1f8163d0daceb68675b10194db7cde7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7feece45900e5166864927047ad3ab7b997f8258 Original-Change-Id: Id2bc544ac5faf53f0f676fe132fea1db5640a401 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286877 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/romstage.c | 24 ++++++++++++++++-------- src/mainboard/google/glados/spd/spd.h | 1 + 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index afcad8c..4d9aaf4 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -21,6 +21,7 @@ #include <cbfs.h> #include <console/console.h> +#include <memory_info.h> #include <string.h> #include <ec/google/chromeec/ec.h> #include <soc/pei_data.h> @@ -45,14 +46,6 @@ void mainboard_memory_init_params(struct romstage_params *params, (UINT32)(params->pei_data->spd_data[0][0]); memory_params->MemorySpdPtr10 = (UINT32)(params->pei_data->spd_data[1][0]); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", - memory_params->MemorySpdPtr00); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", - memory_params->MemorySpdPtr01); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", - memory_params->MemorySpdPtr10); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", - memory_params->MemorySpdPtr11); } memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], sizeof(params->pei_data->dq_map[0])); @@ -69,3 +62,18 @@ void mainboard_memory_init_params(struct romstage_params *params, memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; } + +void mainboard_add_dimm_info(struct romstage_params *params, + struct memory_info *mem_info, + int channel, int dimm, int index) +{ + /* Set the manufacturer */ + memcpy(&mem_info->dimm[index].mod_id, + &params->pei_data->spd_data[channel][dimm][SPD_MANU_OFF], + sizeof(mem_info->dimm[index].mod_id)); + + /* Set the module part number */ + memcpy(mem_info->dimm[index].module_part_number, + &params->pei_data->spd_data[channel][dimm][SPD_PART_OFF], + sizeof(mem_info->dimm[index].module_part_number)); +} diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index abb964e..f1b733f 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -32,5 +32,6 @@ #define SPD_BUS_DEV_WIDTH 8 #define SPD_PART_OFF 128 #define SPD_PART_LEN 18 +#define SPD_MANU_OFF 148 #endif

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New patch to review for coreboot: intel: common: Let mainboard supplement FSP memory info
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11033 -gerrit commit c03328b438edf37fe80b26d008ce362487304890 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 16:48:55 2015 -0700 intel: common: Let mainboard supplement FSP memory info Since the FSP memory info HOB does not return all the data that we need about a DIMM add a weak function that will allow the mainboard to supplement the generated memory_info structure. Ideally this would not be necessary but until FSP returns the module part number we need this. BUG=chrome-os-partner:42975, chrome-os-partner:42561 BRANCH=none TEST=run "mosys memory spd print all" on glados Change-Id: Ic6d0ee0a31d23efcf7e7d7f18a74e944e09e7b46 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 34ad7f1906ba526e52d38d5a6bce7b88b83f0c13 Original-Change-Id: I8509c5c627c1605894473fdea567e7f7ede08cf9 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286876 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/common/romstage.c | 13 +++++++++++++ src/soc/intel/common/romstage.h | 4 ++++ 2 files changed, 17 insertions(+) diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 99ac890..7a05e17 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -363,6 +363,10 @@ __attribute__((weak)) void mainboard_save_dimm_info( MEMORY_BUS_WIDTH_128; break; } + + /* Add any mainboard specific information */ + mainboard_add_dimm_info(params, mem_info, + channel, dimm, index); index++; } } @@ -371,6 +375,15 @@ __attribute__((weak)) void mainboard_save_dimm_info( printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } +/* Add any mainboard specific information */ +__attribute__((weak)) void mainboard_add_dimm_info( + struct romstage_params *params, + struct memory_info *mem_info, + int channel, int dimm, int index) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + /* Get the memory configuration data */ __attribute__((weak)) int mrc_cache_get_current( const struct mrc_saved_data **cache) diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index c677095..403016e 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -23,6 +23,7 @@ #include <stdint.h> #include <arch/cpu.h> +#include <memory_info.h> #include <fsp_util.h> #include <soc/intel/common/util.h> #include <soc/pei_data.h> @@ -76,6 +77,9 @@ void mainboard_memory_init_params(struct romstage_params *params, void mainboard_pre_console_init(struct romstage_params *params); void mainboard_romstage_entry(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); +void mainboard_add_dimm_info(struct romstage_params *params, + struct memory_info *mem_info, + int channel, int dimm, int index); void raminit(struct romstage_params *params); void report_memory_config(void); void report_platform_info(void);

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New patch to review for coreboot: intel/common: Add SMBIOS memory width
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11032 -gerrit commit 8aa773b6797f8104f6cd2b0d0135ffcc03d00cea Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jun 26 11:15:42 2015 -0700 intel/common: Add SMBIOS memory width Add SMBIOS symbols to define the memory width. Update the Intel common code to display the memory width and provide the memory width to SMBIOS. Also display the memory frequency, size and bus width in decimal. BRANCH=none BUG=None TEST=None Change-Id: I67b814d79fdbbf6ce65ac6b4a8282ab15fb91369 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0e59c7260afd180f3adcbeda7cef1b9eca3ed846 Original-Change-Id: Ibd26812c2aad4deaab62111b1e018be69c4faa7b Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282115 Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/smbios.h | 42 +++++++++++++++++++++++++++++++++++++++++ src/soc/intel/common/romstage.c | 34 +++++++++++++++++++++++++++++++-- 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/src/include/smbios.h b/src/include/smbios.h index 66d2b2f..b654c23 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -77,6 +77,48 @@ const char *smbios_mainboard_family(void); #define MEMORY_TYPE_DETAIL_UNBUFFERED (1 << 14) typedef enum { + MEMORY_BUS_WIDTH_8 = 0, + MEMORY_BUS_WIDTH_16 = 1, + MEMORY_BUS_WIDTH_32 = 2, + MEMORY_BUS_WIDTH_64 = 3, + MEMORY_BUS_WIDTH_128 = 4, + MEMORY_BUS_WIDTH_256 = 5, + MEMORY_BUS_WIDTH_512 = 6, + MEMORY_BUS_WIDTH_1024 = 7, + MEMORY_BUS_WIDTH_MAX = 7, +} smbios_memory_bus_width; + +typedef enum { + MEMORY_DEVICE_OTHER = 0x01, + MEMORY_DEVICE_UNKNOWN = 0x02, + MEMORY_DEVICE_DRAM = 0x03, + MEMORY_DEVICE_EDRAM = 0x04, + MEMORY_DEVICE_VRAM = 0x05, + MEMORY_DEVICE_SRAM = 0x06, + MEMORY_DEVICE_RAM = 0x07, + MEMORY_DEVICE_ROM = 0x08, + MEMORY_DEVICE_FLASH = 0x09, + MEMORY_DEVICE_EEPROM = 0x0A, + MEMORY_DEVICE_FEPROM = 0x0B, + MEMORY_DEVICE_EPROM = 0x0C, + MEMORY_DEVICE_CDRAM = 0x0D, + MEMORY_DEVICE_3DRAM = 0x0E, + MEMORY_DEVICE_SDRAM = 0x0F, + MEMORY_DEVICE_SGRAM = 0x10, + MEMORY_DEVICE_RDRAM = 0x11, + MEMORY_DEVICE_DDR = 0x12, + MEMORY_DEVICE_DDR2 = 0x13, + MEMORY_DEVICE_DDR2_FB_DIMM = 0x14, + MEMORY_DEVICE_DDR3 = 0x18, + MEMORY_DEVICE_DBD2 = 0x19, + MEMORY_DEVICE_DDR4 = 0x1A, + MEMORY_DEVICE_LPDDR = 0x1B, + MEMORY_DEVICE_LPDDR2 = 0x1C, + MEMORY_DEVICE_LPDDR3 = 0x1D, + MEMORY_DEVICE_LPDDR4 = 0x1E, +} smbios_memory_device_type; + +typedef enum { MEMORY_FORMFACTOR_OTHER = 0x01, MEMORY_FORMFACTOR_UNKNOWN = 0x02, MEMORY_FORMFACTOR_SIMM = 0x03, diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 370d973..99ac890 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -34,6 +34,7 @@ #include <memory_info.h> #include <reset.h> #include <romstage_handoff.h> +#include <smbios.h> #include <soc/intel/common/mrc_cache.h> #include <soc/intel/common/util.h> #include <soc/pei_wrapper.h> @@ -273,8 +274,10 @@ __attribute__((weak)) void mainboard_save_dimm_info( memory_info_hob->Revision); printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", memory_info_hob->MemoryType); - printk(BIOS_DEBUG, " 0x%04x: MemoryFrequencyInMHz\n", + printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", memory_info_hob->MemoryFrequencyInMHz); + printk(BIOS_DEBUG, " %d: DataWidth in bits\n", + memory_info_hob->DataWidth); printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", memory_info_hob->ErrorCorrectionType); printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", @@ -293,7 +296,7 @@ __attribute__((weak)) void mainboard_save_dimm_info( printk(BIOS_DEBUG, " DIMM %d\n", dimm); printk(BIOS_DEBUG, " 0x%02x: DimmId\n", dimm_info->DimmId); - printk(BIOS_DEBUG, " 0x%02x: SizeInMb\n", + printk(BIOS_DEBUG, " %d: SizeInMb\n", dimm_info->SizeInMb); } } @@ -333,6 +336,33 @@ __attribute__((weak)) void mainboard_save_dimm_info( channel_info->ChannelId; mem_info->dimm[index].dimm_num = dimm_info->DimmId; + switch (memory_info_hob->DataWidth) { + default: + case 8: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_8; + break; + + case 16: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_16; + break; + + case 32: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_32; + break; + + case 64: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_64; + break; + + case 128: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_128; + break; + } index++; } }

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New patch to review for coreboot: glados: Set the write protect GPIO
by Patrick Georgi 22 Jul '15

22 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11031 -gerrit commit c059cf7ced23a6d2105c0e9183e7f52880613e6e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 20 15:50:42 2015 -0700 glados: Set the write protect GPIO The write protect gpio is not added to the gpio map so the structure is not valid for vboot to consume. BUG=chrome-os-partner:42560 BRANCH=none TEST=build and boot on glados, check basic crossytem output CQ-DEPEND=CL:286911 Change-Id: I228d75049b919449072e395699c822203a08f1c6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d15438c4bf56d92189f2f501a62b55b5d00ba461 Original-Change-Id: I3290c4b96e1cc675c618a983915b778f11175020 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286930 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/chromeos.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index f1ff43b..70d78e0 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -40,6 +40,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->count = GPIO_COUNT; gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", get_recovery_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",

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coreboot-gerrit July 2015