the following patch was just integrated into master:
commit 67b9430b367a9f9a884043f14365a55b7ef3c45c
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Thu Jun 18 01:14:01 2015 -0700
cpu: port amd/agesa to 64bit
Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Signed-off-by: Scott Duplichan <scott(a)notabs.org>
Reviewed-on: http://review.coreboot.org/10579
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See http://review.coreboot.org/10579 for details.
-gerrit
the following patch was just integrated into master:
commit 29e6548ac2b720bdccf8367d2a663f128351df38
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Thu Jun 18 01:18:09 2015 -0700
Port Fam14 northbridge code to 64bit
Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Signed-off-by: Scott Duplichan <scott(a)notabs.org>
Reviewed-on: http://review.coreboot.org/10583
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See http://review.coreboot.org/10583 for details.
-gerrit
the following patch was just integrated into master:
commit f226a4d41db5ab314200206e7cb8731f022a14a6
Author: York Yang <york.yang(a)intel.com>
Date: Tue Jul 7 11:09:02 2015 -0700
intel/fsp_baytrail: Support Baytrail FSP Gold4 release
Baytrail FSP Gold4 release added 5 PCD options. Update UPD_DATA_REGION
structure to include these new PCD options and initialized the setting
when given in devicetree.cb.
Change-Id: Ic343e79479464972455e42f9352b3bb116c6f80f
Signed-off-by: York Yang <york.yang(a)intel.com>
Reviewed-on: http://review.coreboot.org/10838
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless(a)gmail.com>
See http://review.coreboot.org/10838 for details.
-gerrit
the following patch was just integrated into master:
commit d9c7a7b4dadc088c49a5668b13bb74fc6eea8079
Author: Tom Warren <twarren(a)nvidia.com>
Date: Fri Jul 17 08:19:18 2015 -0700
t132: Correct dma_busy function
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA
operation is complete. However, in case of ONCE mode, use STA_BSY bit
to determine if DMA operation on the channel is complete.
This change was propogated from T210, commit ID fe48f094
BUG=None
BRANCH=None
TEST=Ryu/Rush build OK.
Change-Id: I13073cc12ed0a6390d55b00c725d1cc7d0797e23
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: aab62d5148b57fd1e05c1e838eafe8fdee431ef8
Original-Change-Id: I7388e9fd73d591de50962aaefc5ab902f560fc6f
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286468
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11017
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/11017 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11017
-gerrit
commit b8930575f7a924aa1a340ae791d5664790935fe5
Author: Tom Warren <twarren(a)nvidia.com>
Date: Fri Jul 17 08:19:18 2015 -0700
t132: Correct dma_busy function
In case of continuous mode, use STA_ACTIVITY bit to determine if DMA
operation is complete. However, in case of ONCE mode, use STA_BSY bit
to determine if DMA operation on the channel is complete.
This change was propogated from T210, commit ID fe48f094
BUG=None
BRANCH=None
TEST=Ryu/Rush build OK.
Change-Id: I13073cc12ed0a6390d55b00c725d1cc7d0797e23
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: aab62d5148b57fd1e05c1e838eafe8fdee431ef8
Original-Change-Id: I7388e9fd73d591de50962aaefc5ab902f560fc6f
Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286468
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/soc/nvidia/tegra132/dma.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/soc/nvidia/tegra132/dma.c b/src/soc/nvidia/tegra132/dma.c
index 9f04e97..fb98692 100644
--- a/src/soc/nvidia/tegra132/dma.c
+++ b/src/soc/nvidia/tegra132/dma.c
@@ -69,9 +69,21 @@ int dma_busy(struct apb_dma_channel * const channel)
* In continuous mode, the BSY_n bit in APB_DMA_STATUS and
* BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long
* as the channel is enabled. So for this function we'll use the
- * DMA_ACTIVITY bit.
+ * DMA_ACTIVITY bit in case of continuous mode.
+ *
+ * However, for ONCE mode, the BSY_n bit in APB_DMA_STATUS will be used
+ * to determine end of dma operation.
*/
- return read32(&channel->regs->sta) & APB_STA_DMA_ACTIVITY ? 1 : 0;
+ uint32_t bit;
+
+ if (read32(&channel->regs->csr) & APB_CSR_ONCE)
+ /* Once mode */
+ bit = APB_STA_BSY;
+ else
+ /* Continuous mode */
+ bit = APB_STA_DMA_ACTIVITY;
+
+ return read32(&channel->regs->sta) & bit ? 1 : 0;
}
/* claim a DMA channel */
struct apb_dma_channel * const dma_claim(void)
the following patch was just integrated into master:
commit 2b7693d63a4e9c160a611f4e2cf5df29bc81d2b5
Author: Yen Lin <yelin(a)nvidia.com>
Date: Tue Jun 2 17:40:31 2015 -0700
t210: Add tegra_lp0_resume code
BUG=chrome-os-partner:40741
BRANCH=None
TEST=tested on Smaug; able to suspend/resume
Change-Id: I3e796bee4b1bedfd4cce0a37549108d5271658a6
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 207ca26cb2c157c0dcf476c4d4973b4d4ec67cc7
Original-Change-Id: I8565d4cf1632d6d3023aa55b2bff824a092f2c3b
Original-Signed-off-by: Yen Lin <yelin(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277025
Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11018
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/11018 for details.
-gerrit
the following patch was just integrated into master:
commit bf697566da9a59a37d1bf3dfa1839fd5aee33f56
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Jul 16 13:59:57 2015 -0700
libpayload: lz4: Add output overrun check to incompressible case
The LZ4 decompressor currently doesn't check for output overruns before
writing data in the case where a block had been incompressible (and
included verbatim in the compression stream). This is extremely unlikely
with the default 4MB blocks, but still a nice thing to fix. We'll still
output as much data as we can before returning an error to support
partial decompression use cases.
This matches the behavior already in place for normal, LZ4-compressed
blocks where the decompression function is already (supposed to be)
doing complete bounds checking (although it is not guaranteed to output
all valid bytes before aborting on an output overrun, and you should try
to provide a few dozen bytes of extra buffer space beyond the parts
you're interested in on partial decompression).
BRANCH=None
BUG=chrome-os-partner:32184
TEST=None
Change-Id: I5e40c8cec8947ec0ec8f6d8c8fa2574cfb4dc958
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 636985334c9b3b93a12d4066d2829f1f999c9315
Original-Change-Id: Iecf44650aade60b9fa1b13e57da752fb482a3f3f
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286240
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/11016 for details.
-gerrit
the following patch was just integrated into master:
commit 7fea2707efcdeb5559c333c96aad5b6632dd0fae
Author: Jimmy Zhang <jimmzhang(a)nvidia.com>
Date: Mon Jul 13 14:10:18 2015 -0700
t210: Correct device MMIO range
Address region from 0x0 to 0x00ffffff is used for IROM_LOVEC and
can not be accessed by Bootloader.
Issue found in CL: 283104 is captured by this patch.
BUG=None
BRANCH=None
TEST=Compiles successfully and reboot test does not crash in firmware
Here are memory mapping table before and after this CL for evt2 board:
Before:
Mapping address range [0000000000000000:0000000040000000) as cacheable | read-write | secure | device
Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal
Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device
Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal
Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal
Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal
After:
Mapping address range [0000000001000000:0000000040000000) as cacheable | read-write | secure | device
Mapping address range [0000000040000000:0000000040040000) as cacheable | read-write | non-secure | normal
Mapping address range [0000000040040000:0000000080000000) as cacheable | read-write | secure | device
Mapping address range [0000000080000000:00000000feb00000) as cacheable | read-write | non-secure | normal
Mapping address range [00000000fec00000:0000000100000000) as cacheable | read-write | secure | normal
Mapping address range [0000000100000000:0000000140000000) as cacheable | read-write | non-secure | normal
Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Change-Id: I07d38a8994c37bf945a68fb95a156c13f435ded2
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 3eee44944c2c83cc3530bfac0d71b86d3265f5b2
Original-Change-Id: I2b827064807ed715625af627db1826c3a01121ec
Original-Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285260
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11015
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/11015 for details.
-gerrit
the following patch was just integrated into master:
commit 87d492fbceeb8178a9bc5d00897944ff186656a0
Author: Furquan Shaikh <furquan(a)google.com>
Date: Thu Jul 16 12:25:01 2015 -0700
arm64: Set LOG_LEVEL=0 for BL31 if coreboot does not use serial
Even if DEBUG=0, BL31 puts NOTICE(..) messages on serial console. Set
LOG_LEVEL=0 if coreboot does not use serial.
BUG=None
BRANCH=None
TEST=Compiles successfully and no console output from bl31 for
production images.
Change-Id: Ie77bcac3e2a0d314545b6811327c413536c77fb9
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: e8e3bcbf6249c80850a87dd66f34d3ff36158641
Original-Change-Id: I1415a3816cd2fa9dd05bcbd36ac0abc3f2759960
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286150
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11014
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/11014 for details.
-gerrit