coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: google/cyan: Configure EC_IN_RW signal as gpio input
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit b61ed3550beb662b2a28e966878c4e717062e8f9 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sat Jul 18 16:04:21 2015 -0700 google/cyan: Configure EC_IN_RW signal as gpio input BUG=chrome-os-partner:42881 BRANCH=None TEST=Using ctrl-d in recovery mode to switch to dev mode works. Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9 Original-Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5 Original-Reviewed-on: https://chromium-review.googlesource.com/286612 Original-Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/11013 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11013 for details. -gerrit

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Patch set updated for coreboot: google/cyan: Configure EC_IN_RW signal as gpio input
by Patrick Georgi 21 Jul '15

21 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11013 -gerrit commit 76115d9f05e7c04ad69eab2d3ca3ad741687a192 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sat Jul 18 16:04:21 2015 -0700 google/cyan: Configure EC_IN_RW signal as gpio input BUG=chrome-os-partner:42881 BRANCH=None TEST=Using ctrl-d in recovery mode to switch to dev mode works. Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9 Original-Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5 Original-Reviewed-on: https://chromium-review.googlesource.com/286612 Original-Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> --- src/mainboard/google/cyan/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c index 3cd319d..3030477 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/gpio.c @@ -131,7 +131,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_NC, /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */ GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ Native_M1, /* 79 MF_SMB_ALERTB */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */

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Patch merged into coreboot/master: mec: Correct the access mode for short payloads
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit f4e9eb9aba875768cbd80241e3770659bdafd643 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Sat Jul 18 11:46:37 2015 -0700 mec: Correct the access mode for short payloads If the Host Command payload is less than 4 bytes and is word aligned then the payload was not transferred at all. EC reads the old packet and CRC mismatch occurs. In this issue, the HC command packet consisting of EC_CMD_REBOOT_EC as command and EC_REBOOT_COLD as payload encountered the same problem as above. Hence select byte access mode for shorter payloads. BRANCH=None BUG=chrome-os-partner:42396 TEST=System should boot after chromeos-firmwareupdate Change-Id: I22bdb739108d31b592c20247be69c198d617d359 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8a43d2636b1bbfbac0384e1ea5e8853a7bd87a7f Original-Change-Id: I5572093436f4f4a0fc337efa943753ab4642d8e4 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Signed-off-by: Icarus Sparry <icarus.w.sparry(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286537 Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/11012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11012 for details. -gerrit

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Patch merged into coreboot/master: skylake: add global reset cause registers to power state
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 76d16715ec067abcadecbbd79b51e2711b8ec57c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 17 16:52:10 2015 -0500 skylake: add global reset cause registers to power state Log the global reset causes in the power state structure. While working in there pack the struct and use width-specific types as this struct crosses the romstate <-> ramstage boundary. Lastly, remove hsio version as it wasn't being written or read. After global reset induced: PM1_STS: 0000 PM1_EN: 0000 PM1_CNT: 00000000 TCO_STS: 0000 0000 GPE0_STS: 00000000 00000000 00000000 00000000 GPE0_EN: 00000000 00000000 00000000 00000000 GEN_PMCON: d8010200 00003808 GBLRST_CAUSE: 00000000 00040004 Previous Sleep State: S0 BUG=None BRANCH=None TEST=Induced global reset on glados using ETR3 register and write to cf9. Change-Id: I97b93de336e74c0e02199241376e74340612f0a7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47 Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286640 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11011 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11011 for details. -gerrit

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Patch merged into coreboot/master: intel/cyan: Fix crossystem "wpsw_cur" status
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit d68c35dab4708566c760faa183eddf67bf5e2854 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Jul 17 17:04:25 2015 -0700 intel/cyan: Fix crossystem "wpsw_cur" status The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community were in two ranges: 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error. The original offset was 0x16 whereas it should be 0x13 BUG=chrome-os-partner:42798 BRANCH=None TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917 Original-Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286534 Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/11010 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11010 for details. -gerrit

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Patch set updated for coreboot: intel/cyan: Fix crossystem "wpsw_cur" status
by Patrick Georgi 21 Jul '15

21 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11010 -gerrit commit 7e104df149155d290b937c09d2a46aa475d28d01 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Jul 17 17:04:25 2015 -0700 intel/cyan: Fix crossystem "wpsw_cur" status The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community were in two ranges: 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error. The original offset was 0x16 whereas it should be 0x13 BUG=chrome-os-partner:42798 BRANCH=None TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917 Original-Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286534 Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> --- src/mainboard/google/cyan/acpi/chromeos.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl index 4ba3857..4e5cd54 100644 --- a/src/mainboard/google/cyan/acpi/chromeos.asl +++ b/src/mainboard/google/cyan/acpi/chromeos.asl @@ -33,5 +33,5 @@ Name(OIPG, Package() { /* No physical recovery button */ Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10016, "Braswell" }, + Package () { 0x0003, 1, 0x10013, "Braswell" }, })

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Patch merged into coreboot/master: Kunimitsu: Add comment and separate routines
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 26dd3582c843864bb1b0432a8206f8ef96b4195a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jul 17 11:13:57 2015 -0700 Kunimitsu: Add comment and separate routines Document the lid open state and separate the routines with a single blank line. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: I244f20c03bc7530ad8d140fba41dd97c12c079e1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 57313253fdef3f2d3f0e16b8ab8aa91202d45b16 Original-Change-Id: I7b3bd9cf16e915d214eb2de0017a8d91a934b112 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286267 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/11009 Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11009 for details. -gerrit

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Patch merged into coreboot/master: Kunimitsu: Remove address from copyright notice
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit b993d2f1477a8e3d7c7f9c4b4e2f05773b4d098f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jul 17 11:07:54 2015 -0700 Kunimitsu: Remove address from copyright notice Remove the address from the copyright notices. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: Ibe8196841d9e76c9ee3a3dbae802ecc63dc7904c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cc12d2658324a375d02748098f0a2f4b5d1b5615 Original-Change-Id: I81a71e4ad9b8a66ad0e9a93cbeb512d90eb35906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286266 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: http://review.coreboot.org/11008 Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11008 for details. -gerrit

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Patch merged into coreboot/master: skylake: take into account deep s3 in power failure check
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit e94c40b254a5019e7e25be4d2399ad31f30dd271 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 16 17:55:54 2015 -0500 skylake: take into account deep s3 in power failure check If a resume from S3 is occuring one needs to take into account deep S3 in order to check the proper power failure bits. When deep S3 is enabled the suspend well will be turned off. Therefore don't look for that bit when determining a power failure. BUG=chrome-os-partner:42847 BRANCH=None TEST=Suspend and resumed with deep s3 enabled and disabled. Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2 Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286271 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11007 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11007 for details. -gerrit

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Patch merged into coreboot/master: skylake: read out and report full width of gen_pmcon registers
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit a3d36bd9693b78bc6ec2a30bef3413fa038d1a04 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 16 17:49:33 2015 -0500 skylake: read out and report full width of gen_pmcon registers GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and save the full 32 bits for completeness. BUG=chrome-os-partner:42847 BRANCH=None TEST=Built and booted. Noted output on terminal. Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0 Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286270 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11006 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11006 for details. -gerrit

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coreboot-gerrit July 2015