coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: Cyan: Tune charger current limit in performance states table.
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit d66bc210ae483fee09580cf6fd72e246782e00b6 Author: li feng <li1.feng(a)intel.com> Date: Fri Jul 10 14:05:50 2015 -0700 Cyan: Tune charger current limit in performance states table. Charger performance states table defines charger current limit for each p state. Modify charger current control values for SANYO battery used in Cyan. BUG=None BRANCH=None TEST=System is charging battery, in shell window, issue command "echo 0 > /sys/class/thermal/cooling_device4/cur_state", "echo 1 > /sys/class/thermal/cooling_device4/cur_state", "echo 2 > /sys/class/thermal/cooling_device4/cur_state", "echo 3 > /sys/class/thermal/cooling_device4/cur_state", or "echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC console show different charging current value. Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09 Original-Signed-off-by: li feng <li1.feng(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285605 Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Divya Jyothi <divya.jyothi(a)intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi(a)intel.com> Reviewed-on: http://review.coreboot.org/11004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11004 for details. -gerrit

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Patch set updated for coreboot: Cyan: Tune charger current limit in performance states table.
by Patrick Georgi 21 Jul '15

21 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11004 -gerrit commit 985c685b904256f8bd5ec8b033b709af2c0a1acc Author: li feng <li1.feng(a)intel.com> Date: Fri Jul 10 14:05:50 2015 -0700 Cyan: Tune charger current limit in performance states table. Charger performance states table defines charger current limit for each p state. Modify charger current control values for SANYO battery used in Cyan. BUG=None BRANCH=None TEST=System is charging battery, in shell window, issue command "echo 0 > /sys/class/thermal/cooling_device4/cur_state", "echo 1 > /sys/class/thermal/cooling_device4/cur_state", "echo 2 > /sys/class/thermal/cooling_device4/cur_state", "echo 3 > /sys/class/thermal/cooling_device4/cur_state", or "echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC console show different charging current value. Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09 Original-Signed-off-by: li feng <li1.feng(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285605 Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Divya Jyothi <divya.jyothi(a)intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi(a)intel.com> --- src/mainboard/google/cyan/acpi/dptf.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 4b85449..5b0da39 100755 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -39,10 +39,10 @@ /* Charger performance states, board-specific values from charger and EC */ Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ + Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ })

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Patch merged into coreboot/master: Glados: Update Serial IO modes in devicetree
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit f82758a8762ffb1df8fafed5769dfbbd63cc216e Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Fri Jul 10 17:09:37 2015 +0530 Glados: Update Serial IO modes in devicetree This patch updates the Serial IO modes for UART2 to PCI mode in devicetree for glados board. Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit legacy UART will stop working after devicetree change. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for glados and tested LPSS logs on glados. CQ-DEPEND=CL:284881 CL:284882 CL:284883 Change-Id: I433979c852c80848c006ef089b43d75a17e761c5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189 Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284826 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11002 for details. -gerrit

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Patch merged into coreboot/master: kunimitsu: Update Serial IO modes in devicetree
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 75154b801f8c31298125d4fc0a3ee069058dc0b6 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Thu Jul 9 18:00:40 2015 +0530 kunimitsu: Update Serial IO modes in devicetree This patch updates the Serial IO modes for UART 1 and 2 in devicetree for kunimitsu boards. UART1 are disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu. Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627 Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284825 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11001 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11001 for details. -gerrit

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Patch merged into coreboot/master: Sklrvp: Update Serial IO modes in devicetree
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit baf4e3e92d02f9a1976acf4efcd4baec86c56c49 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Thu Jul 9 17:59:58 2015 +0530 Sklrvp: Update Serial IO modes in devicetree This patch updates the Serial IO modes for UART 1 and 2 in devicetree for sklrvp boards. UART1 is disabled and UART2 is in PCI mode. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3. Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284824 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11000 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: support 32bit uart8250_mem driver in romstage
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 46ca690ec0bf3237c3a3aeaf209e9465ab3086b7 Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Mon May 18 21:25:52 2015 +0530 intel/skylake: support 32bit uart8250_mem driver in romstage This patch adds 32bit uart8250_mem functionality in romstage console for arch/x86. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp; verified romstage logs on RVP3 board. Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765 Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271800 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/10999 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10999 for details. -gerrit

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Patch merged into coreboot/master: console: Add UART8250MEM 32bit support
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit a73408d608d963c989debc08953672b0e03a7fdb Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Wed Jul 8 14:23:06 2015 +0530 console: Add UART8250MEM 32bit support This patch adds UART8250MEM_32 feature flag to support UART8250 compatible with 32bit access in memory mapped mode. [pg: rebuilt to reuse the existing UART8250 8bit access driver which reduces code duplication.] Change-Id: I310e70dfab81dcca575e9931e0ccf93af70efa40 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0c3b2c628b854e8334540ff5158c2587dbfabf95 Original-Change-Id: I07ee256f25e48480372af9a9255bf487c331e51d Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy(a)intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/271759 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/10998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10998 for details. -gerrit

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Patch merged into coreboot/master: google/glados: add new board
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 406313d46d00c74dcfc80d4721bbd774d8b83911 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 20 22:01:32 2015 +0200 google/glados: add new board Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10997 for details. -gerrit

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Patch set updated for coreboot: nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h
by Jonathan A. Kollasch 21 Jul '15

21 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10984 -gerrit commit 97f056d7bf87b73f1e794aab6c3268ceac49c38e Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 20 09:51:34 2015 -0500 nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/asus/kfsn4-dre/romstage.c | 9 --------- src/southbridge/nvidia/ck804/early_setup.c | 14 ++++++++++++++ src/southbridge/nvidia/ck804/early_setup_car.c | 14 +++++++++++++- src/southbridge/nvidia/mcp55/early_setup_car.c | 10 ++++++++++ 4 files changed, 37 insertions(+), 10 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index aa72021..cf36a72 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -67,15 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -/* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in ck804_early_setup_x(). - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#define CK804_SKIP_PCI_REG_78_INIT 1 - #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index c0a8766..9c0a783 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -152,10 +152,24 @@ static void ck804_early_setup(void) RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, #endif +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, +#endif RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, #if CONFIG_CK804_NUM > 1 + /* + * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * non-primary chain too??? + */ RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 8065d20..87fdbdd 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -142,7 +142,15 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, CK804_MB_SETUP #endif -#ifndef CK804_SKIP_PCI_REG_78_INIT +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, #endif RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, @@ -239,6 +247,10 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + /* + * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * non-primary chains too??? + */ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 4970a4c..d919610 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -242,7 +242,17 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, +#endif #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,

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Patch merged into coreboot/master: intel/common: remove printk in pre_console_init()
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 43bf00e594345412bd00d3e01001c4daf3c3b537 Author: rsatapat <rishavnath.satapathy(a)intel.com> Date: Mon Jul 6 21:03:02 2015 +0530 intel/common: remove printk in pre_console_init() printk called before console init causes sluggish execution because of Rx timeout. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu. Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be Original-Signed-off-by: rsatapat <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284823 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/10996 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10996 for details. -gerrit

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coreboot-gerrit July 2015