coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

Patch set updated for coreboot: intel/common: remove printk in pre_console_init()
by Patrick Georgi 21 Jul '15

21 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10996 -gerrit commit 8af9115871047ea46e1644106db4a44b2a91dd0d Author: rsatapat <rishavnath.satapathy(a)intel.com> Date: Mon Jul 6 21:03:02 2015 +0530 intel/common: remove printk in pre_console_init() printk called before console init causes sluggish execution because of Rx timeout. BRANCH=None BUG=chrome-os-partner:40857 TEST=Built for sklrvp and tested LPSS logs on RVP3 and Kunimitsu. Change-Id: I61d5c0f5a4e93695bcba90b7ac7d4f68e2d625be Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 77c58702c8279c6d9c6ae1c946bf1b76df20714d Original-Change-Id: Ib85029456059248cc2c88aaccba4fa12cc5a76be Original-Signed-off-by: rsatapat <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284823 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/common/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 919de83..370d973 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -231,7 +231,6 @@ __attribute__((weak)) void mainboard_check_ec_image( __attribute__((weak)) void mainboard_pre_console_init( struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Board initialization before and after RAM is enabled */

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Patch merged into coreboot/master: Skylake: Initialize GPIOs for UART2
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 1b9635de6613548449cd2689d212cd6f01dbfd54 Author: rsatapat <rishavnath.satapathy(a)intel.com> Date: Wed Jun 24 20:49:16 2015 +0530 Skylake: Initialize GPIOs for UART2 FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10995 for details. -gerrit

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Patch set updated for coreboot: Skylake: Initialize GPIOs for UART2
by Patrick Georgi 21 Jul '15

21 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10995 -gerrit commit 94c821313ce227ca79a53ddc528dc087babf697b Author: rsatapat <rishavnath.satapathy(a)intel.com> Date: Wed Jun 24 20:49:16 2015 +0530 Skylake: Initialize GPIOs for UART2 FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit. BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2 Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat <rishavnath.satapathy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/skylake/include/soc/gpio.h | 12 ++++++ src/soc/intel/skylake/romstage/uart.c | 64 +++++++++++++++++++++++++++++++- 2 files changed, 74 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index efc666f..03ed119 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -257,6 +257,18 @@ typedef struct { .owner = GPIO_OWNER_GPIO, \ .conf1 = GPIO_SENSE_DISABLE } +/* Number of pins used by SerialIo controllers */ +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 + +/* Below defines are based on GPIO_CONFIG structure fields */ +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 + +/* GPIO Pad Mode */ +#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) +#define N_PCH_GPIO_PAD_MODE 10 + struct gpio_config { u8 gpio; u32 conf0; diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 8aa1053..c53643a 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -25,6 +25,9 @@ #include <soc/pcr.h> #include <soc/romstage.h> #include <soc/serialio.h> +#include <gpio.h> + +static void uartgpioinit(u8 hwflowcontrol); void pch_uart_init(void) { @@ -32,7 +35,7 @@ void pch_uart_init(void) u32 tmp; u8 *base = (u8 *)CONFIG_TTYS0_BASE; - /* Set configured UART base address */ + /* Set configured UART2 base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); /* Enable memory access and bus master */ @@ -40,7 +43,7 @@ void pch_uart_init(void) tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config32(dev, PCI_COMMAND, tmp); - /* Take UART out of reset */ + /* Take UART2 out of reset */ tmp = read32(base + SIO_REG_PPR_RESETS); tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | SIO_REG_PPR_RESETS_IDMA; @@ -56,4 +59,61 @@ void pch_uart_init(void) /* Put UART2 in byte access mode for 16550 compatibility */ pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); + + /* Configure GPIO for UART2 in native mode*/ + uartgpioinit(FALSE); +} + +/* + * GPIO modes + */ +typedef struct { + GPIO_PAD pad; + GPIO_PAD_MODE mode; +} GPIO_PAD_NATIVE_FUNCTION; + +/* + * GPP_C Community for UART2 GPIO + * pin order RXD/TXD/RTSB/CTSB + */ +static const GPIO_PAD_NATIVE_FUNCTION uartgpio[] = { + {GPIO_LP_GPP_C20, GpioPadModeNative1}, + {GPIO_LP_GPP_C21, GpioPadModeNative1}, + {GPIO_LP_GPP_C22, GpioPadModeNative1}, + {GPIO_LP_GPP_C23, GpioPadModeNative1} +}; + +/* + * GPIO config registers + */ +static const GPIO_GROUP_INFO gpio_group_info = { + PID_GPIOCOM1, + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, + V_PCH_GPIO_GPP_C_PAD_MAX, + R_PCH_PCR_GPIO_GPP_C_SMI_STS, + R_PCH_PCR_GPIO_GPP_C_SMI_EN +}; + +static void uartgpioinit(u8 hwflowcontrol) +{ + u32 index, pinsused, dw0reg, dw0regmask, padcfgreg, padnumber; + + if (hwflowcontrol) + pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER; + else + pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL; + + for (index = 0; index < pinsused; index++) { + padnumber = GPIO_GET_PAD_NUMBER(uartgpio[index].pad); + padcfgreg = 0x8 * padnumber + gpio_group_info.padcfgoffset; + dw0regmask = (uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) + >> GPIO_CONF_PAD_MODE_BIT_POS; + dw0regmask = (GpioHardwareDefault == dw0regmask) ? + 0x0 : B_PCH_GPIO_PAD_MODE; + dw0reg = (((uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) >> + (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); + + pcr_andthenor32(gpio_group_info.community, padcfgreg, + ~(u32)dw0regmask, (u32)dw0reg); + } }

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Patch merged into coreboot/master: Skylake: Only support UART2 as debug port, clean up the rest
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 5c56ce13f4a81970ed8c9a2987c2ea55376da52d Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Wed Jul 15 16:02:25 2015 +0530 Skylake: Only support UART2 as debug port, clean up the rest On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10994 for details. -gerrit

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Patch merged into coreboot/master: intel fsp: remove CHIPSET_RESERVED_MEM_BYTES
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit bbbfbf2e0fe3c1af135a955505b6a2fd73681a8e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 16:55:28 2015 -0500 intel fsp: remove CHIPSET_RESERVED_MEM_BYTES FSP 1.1 platforms should be conforming to the spec. In order to ensure following specification remove the crutch that allows FSP to no conform. BUG=chrome-os-partner:41961 BRANCH=None TEST=Built. Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285187 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/10993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10993 for details. -gerrit

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Patch merged into coreboot/master: cyan/strago: Disable wwan
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 367ddc91fffafac2c5c78df62bf34305ae11778c Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Tue Jun 23 19:23:25 2015 -0700 cyan/strago: Disable wwan Disabling the wwan gpio line since wwan is not used. BRANCH=none BUG=none TEST=wwan should not connect to network on cyan/strago. Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144 Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285304 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10992 for details. -gerrit

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Patch merged into coreboot/master: Braswell: Remove GOP from normal boot mode.
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 9b71b0e0001aa8fe2b5513a1d7f2d8488b0be782 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Mon Jul 13 16:12:31 2015 -0700 Braswell: Remove GOP from normal boot mode. Removing GOP initialization in normal mode since we don't need to show splash screen in normal mode. GOP will get initialized in dev and recovery mode. BRANCH=none BUG=None TEST=Splash screen will come only in dev or recovery mode. Change-Id: Ia5e12cf45d723f2f14c447e29b78119552d5e1ea Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 79d1c877343704ea51143b922d9ac9209be4d4b5 Original-Change-Id: Id5ca99757427206413483d07b4f422b4c0abfa5d Original-Signed-off-by: Abhay <abhay.kumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285300 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10990 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10990 for details. -gerrit

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Patch merged into coreboot/master: skylake: re-enable PCIe L1 sub states
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 27d153cabc899ab94ea28d3c7ce5ca56ecefb7ce Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 13:50:34 2015 -0500 skylake: re-enable PCIe L1 sub states All boards should have their L1 sub states working now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/10989 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10989 for details. -gerrit

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Patch set updated for coreboot: skylake: re-enable PCIe L1 sub states
by Patrick Georgi 21 Jul '15

21 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10989 -gerrit commit fe8bdcd1335589c3c148171c2fafc4752eef3b93 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 13:50:34 2015 -0500 skylake: re-enable PCIe L1 sub states All boards should have their L1 sub states working now so re-enable the defaults. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built and booted glados into OS. PCIe devices show up still. Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36 Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285170 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24fd961..207816d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,8 +31,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM - # External devices not working on glados - #select PCIEXP_L1_SUB_STATE + select PCIEXP_L1_SUB_STATE select PLATFORM_USES_FSP1_1 select REG_SCRIPT select RELOCATABLE_MODULES

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Patch set updated for coreboot: amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines
by Jonathan A. Kollasch 21 Jul '15

21 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10963 -gerrit commit 48334886d02be22ee3640c8bd4563bf13f4e3dad Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Jul 17 07:47:41 2015 -0500 amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines Moves the K8 CPU_ADDR_BITS definition from socket to model. Previously socket_F was not setting CPU_ADDR_BITS correctly. Tested on Sun Ultra 40 M2 with two 2nd-gen Opterons w/ 2x4x2GiB DIMMs. Most if not all K8-based chips support 40-bit physical addresses, with possible exception of IA32-only K8-based Athlon XP-M chips. Probably irrelevant, unless your machine has enough memory (at least 60 to 64GiB before MMIO hoisting) to exceed the CPU_ADDR_BITS default of 36 from src/cpu/x86/Kconfig. Change-Id: I01a2a59fa902280171840c36ca2e631476d3d603 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/model_fxx/Kconfig | 4 ++++ src/cpu/amd/socket_754/Kconfig | 4 ---- src/cpu/amd/socket_940/Kconfig | 4 ---- src/cpu/amd/socket_S1G1/Kconfig | 4 ---- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 9ee2bf7..1172d29 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -12,6 +12,10 @@ config CPU_AMD_MODEL_FXX select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX +config CPU_ADDR_BITS + int + default 40 + config UDELAY_IO bool default n diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index aeda421..ec3ab70 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -8,10 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000 diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index a8eef61..47b455b 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -9,10 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 01d84a1..3338677 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -19,10 +19,6 @@ config DIMM_SUPPORT hex default 0x0204 -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000

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coreboot-gerrit July 2015