coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

Patch merged into coreboot/master: Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit f077de66ffdbbd191f09ae8a4d6f08d0313be90f Author: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Date: Mon Jul 6 16:42:56 2015 +0530 Sklrvp: Select PCIEXP_L1_SUB_STATE config symbol This patch selects the config symbol PCIEXP_L1_SUB_STATE to enable L1 substate for PCIe. BRANCH=None BUG=chrome-os-partner:42331 TEST=Build for sklrvp; boot and check "dmesg | grep iwl" shows "L1 enabled and LTR enabled" Change-Id: I97552c7700649a9f5d8646a03027c5c5e0b477b4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3115816fbdd11c7f8ff418e0b5c86b8650c8b83 Original-Change-Id: Iaf307cb2d623cc1ce97b01d15a6b42569fd0c0c4 Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284775 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/10988 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/10988 for details. -gerrit

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Patch merged into coreboot/master: skylake: honor pcie root port settings already in chip.h
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 02b3243dd39291425c325a1e2df6618c5a45d934 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 13 14:03:41 2015 -0500 skylake: honor pcie root port settings already in chip.h For some unkonwn reason the pcie root port settings weren't being honored in the device tree. Fix that omission. BUG=chrome-os-partner:41861 BRANCH=None TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree settings were being honored. Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257 Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285027 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/10987 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10987 for details. -gerrit

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Patch merged into coreboot/master: skylake: Show SPI controller if enabled in devicetree.cb
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 356cabbe35dd2e1c05f9e76c6f079b08e1c97ed8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 13 09:34:37 2015 -0700 skylake: Show SPI controller if enabled in devicetree.cb Unhide the SPI controller PCI device if it is enabled in devicetree.cb so flashrom can do its job. BUG=chrome-os-partner:37711 BRANCH=none TEST=run flashrom -r on glados Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245 Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/284948 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10986 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10986 for details. -gerrit

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Patch merged into coreboot/master: cyan: Enable EC software sync
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 0893e29755db3e94ee41af7ebf8a007a83c6ac50 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Tue Jul 7 08:22:11 2015 -0700 cyan: Enable EC software sync BUG=chrome-os-partner:40526 BRANCH=None TEST=Verify that system boots when used with coreboot and EC versions that also have Software Sync enabled. Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00 Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0 Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283573 Original-Commit-Queue: Divya Jyothi <divya.jyothi(a)intel.com> Original-Tested-by: Divya Jyothi <divya.jyothi(a)intel.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/10985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10985 for details. -gerrit

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Patch merged into coreboot/master: Revert "northbridge/amd/pi: Add support for memory settings"
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit 477d3284f755acbdcda9a2eebd86cd220b651635 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Jul 21 17:15:25 2015 +0200 Revert "northbridge/amd/pi: Add support for memory settings" This is breaking the build right now. Reapply once the correct headers are in place. This reverts commit 406effd59075cab212c5bf9c1a12759c8fad50a4. Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f Reviewed-on: http://review.coreboot.org/11020 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11020 for details. -gerrit

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Patch set updated for coreboot: Revert "northbridge/amd/pi: Add support for memory settings"
by Marc Jones 21 Jul '15

21 Jul '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11020 -gerrit commit 75f7248486677e4d9362baa1169fe56db9ac406d Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Jul 21 17:15:25 2015 +0200 Revert "northbridge/amd/pi: Add support for memory settings" This is breaking the build right now. Reapply once the correct headers are in place. This reverts commit 406effd59075cab212c5bf9c1a12759c8fad50a4. Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f --- src/northbridge/amd/pi/agesawrapper.c | 15 --------------- src/northbridge/amd/pi/def_callouts.c | 3 --- 2 files changed, 18 deletions(-) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index e716f9b..255b31d 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -26,9 +26,6 @@ #include <heapManager.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <PlatformMemoryConfiguration.h> - -extern const PSO_ENTRY PlatformMemoryConfiguration[]; VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -139,18 +136,6 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - /* - * A PlatformMemoryConfiguration[] table must be added in the - * mainboard folder to any boards that need the memory configuation - * settings altered from the standard settings. Examples of boards - * requiring this change might be boards with soldered down memory, - * or boards that use a non-standard memory clock routing scheme - * There are PlatformMemoryConfiguration[] tables in many existing - * mainboards that can be used as an example. - */ - if (PlatformMemoryConfiguration[0] != PSO_END) - PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration; - // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 389742c..8a4472c 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -27,9 +27,6 @@ #include "agesawrapper.h" #include "BiosCallOuts.h" #include "dimmSpd.h" -#include <PlatformMemoryConfiguration.h> - -const PSO_ENTRY __attribute__((weak)) PlatformMemoryConfiguration[] = { PSO_END }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {

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New patch to review for coreboot: Revert "northbridge/amd/pi: Add support for memory settings"
by Marc Jones 21 Jul '15

21 Jul '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11020 -gerrit commit 53e37a68fa77ae408d8ed4b7be7bd53e75b98a6f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Jul 21 17:15:25 2015 +0200 Revert "northbridge/amd/pi: Add support for memory settings" This is breaking the build right now. Reapply one the correct headers are in place. This reverts commit 406effd59075cab212c5bf9c1a12759c8fad50a4. Change-Id: I34b8717820ed58b462d4e7793711ee98fb8b882f --- src/northbridge/amd/pi/agesawrapper.c | 15 --------------- src/northbridge/amd/pi/def_callouts.c | 3 --- 2 files changed, 18 deletions(-) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index e716f9b..255b31d 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -26,9 +26,6 @@ #include <heapManager.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <PlatformMemoryConfiguration.h> - -extern const PSO_ENTRY PlatformMemoryConfiguration[]; VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -139,18 +136,6 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - /* - * A PlatformMemoryConfiguration[] table must be added in the - * mainboard folder to any boards that need the memory configuation - * settings altered from the standard settings. Examples of boards - * requiring this change might be boards with soldered down memory, - * or boards that use a non-standard memory clock routing scheme - * There are PlatformMemoryConfiguration[] tables in many existing - * mainboards that can be used as an example. - */ - if (PlatformMemoryConfiguration[0] != PSO_END) - PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration; - // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 389742c..8a4472c 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -27,9 +27,6 @@ #include "agesawrapper.h" #include "BiosCallOuts.h" #include "dimmSpd.h" -#include <PlatformMemoryConfiguration.h> - -const PSO_ENTRY __attribute__((weak)) PlatformMemoryConfiguration[] = { PSO_END }; AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {

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Patch set updated for coreboot: amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines
by Jonathan A. Kollasch 21 Jul '15

21 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10963 -gerrit commit 603160efa573763e7258f58f2906fd02e90dfdf3 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Fri Jul 17 07:47:41 2015 -0500 amd/model_fxx: set CPU_ADDR_BITS to 40 on all K8 machines Moves the K8 CPU_ADDR_BITS definition from socket to model. Previously socket_F was not setting CPU_ADDR_BITS correctly. Tested on Sun Ultra 40 M2 with two 2nd-gen Opterons w/ 2x4x2GiB DIMMs. Most if not all K8-based chips support 40-bit physical addresses, with possible exception of IA32-only K8-based Athlon XP-M chips. Probably irrelevant, unless your machine has enough memory (at least 60 to 64GiB before MMIO hoisting) to exceed the CPU_ADDR_BITS default of 36 from src/cpu/x86/Kconfig. Change-Id: I01a2a59fa902280171840c36ca2e631476d3d603 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/model_fxx/Kconfig | 4 ++++ src/cpu/amd/socket_754/Kconfig | 4 ---- src/cpu/amd/socket_940/Kconfig | 4 ---- src/cpu/amd/socket_S1G1/Kconfig | 4 ---- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 9ee2bf7..1172d29 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -12,6 +12,10 @@ config CPU_AMD_MODEL_FXX select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX +config CPU_ADDR_BITS + int + default 40 + config UDELAY_IO bool default n diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index aeda421..ec3ab70 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -8,10 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000 diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index a8eef61..47b455b 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -9,10 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 01d84a1..3338677 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -19,10 +19,6 @@ config DIMM_SUPPORT hex default 0x0204 -config CPU_ADDR_BITS - int - default 40 - config DCACHE_RAM_BASE hex default 0xc8000

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Patch set updated for coreboot: nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h
by Jonathan A. Kollasch 21 Jul '15

21 Jul '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10984 -gerrit commit 504faa64b6cdc7d881838eb984f42fe31adb8b31 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Mon Jul 20 09:51:34 2015 -0500 nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/asus/kfsn4-dre/romstage.c | 9 --------- src/southbridge/nvidia/ck804/early_setup.c | 14 ++++++++++++++ src/southbridge/nvidia/ck804/early_setup_car.c | 14 +++++++++++++- src/southbridge/nvidia/mcp55/early_setup_car.c | 10 ++++++++++ 4 files changed, 37 insertions(+), 10 deletions(-) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index aa72021..cf36a72 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -67,15 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -/* - * Avoid crash (complete with severe memory corruption!) during initial CAR boot - * in ck804_early_setup_x(). - * Interestingly once the system is fully booted into Linux this can be set, but - * not before! Apparently something isn't initialized but the amount of effort - * required to fix this is non-negligible and of unknown real-world benefit - */ -#define CK804_SKIP_PCI_REG_78_INIT 1 - #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index c0a8766..9c0a783 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -152,10 +152,24 @@ static void ck804_early_setup(void) RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 9, 0, 0x74), 0xffffffc0, 0x00000000, #endif +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x19000000, +#endif RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000100, #if CONFIG_CK804_NUM > 1 + /* + * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * non-primary chain too??? + */ RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1, 0, 0xe8), 0xffffff00, 0x000000ff, diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 8065d20..87fdbdd 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -142,7 +142,15 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, CK804_MB_SETUP #endif -#ifndef CK804_SKIP_PCI_REG_78_INIT +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in ck804_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x19000000, #endif RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000100, @@ -239,6 +247,10 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x4c), 0xfe00ffff, 0x00440000, RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x74), 0xffffffc0, 0x00000000, + /* + * Avoid touching 0x78 for CONFIG_NORTHBRIDGE_AMD_AMDFAM10 for + * non-primary chains too??? + */ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xc0ffffff, 0x20000000, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe0), 0xfffffeff, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe8), 0xffffff00, 0x000000ff, diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 4970a4c..d919610 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -242,7 +242,17 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + /* + * Avoid crash (complete with severe memory corruption!) during initial CAR boot + * in mcp55_early_setup_x() on Fam10h systems by not touching 0x78. + * Interestingly once the system is fully booted into Linux this can be set, but + * not before! Apparently something isn't initialized but the amount of effort + * required to fix this is non-negligible and of unknown real-world benefit + */ +#else RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, +#endif #if CONFIG_MCP55_USE_AZA RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,

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Patch merged into coreboot/master: amd/hudson: Fix makefile FWM location check
by gerrit＠coreboot.org 21 Jul '15

21 Jul '15

the following patch was just integrated into master: commit f92a1891510e8087ee5df4f04ee7163957f89e77 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Sun Jul 19 15:41:15 2015 -0600 amd/hudson: Fix makefile FWM location check Fix typo. Use the correct math helper int-lt. Change-Id: Ia5e722020c75595dfcfb853ea8238fb8391f9a04 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/10980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10980 for details. -gerrit

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coreboot-gerrit July 2015