coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: arm, arm64, mips: Add rough static stack size checks with -Wstack-usage
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9729 -gerrit commit c7522b27c109f143201831337cdb03fe6081b72a Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Dec 19 16:11:14 2014 -0800 arm, arm64, mips: Add rough static stack size checks with -Wstack-usage We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/include/arch/memlayout.h | 4 +++- src/arch/arm64/include/arch/memlayout.h | 4 +++- src/arch/mips/include/arch/memlayout.h | 4 +++- src/drivers/spi/spi_flash.c | 4 ++++ src/lib/gpio.c | 4 +++- src/vendorcode/google/chromeos/vboot2/verstage.c | 2 +- toolchain.inc | 18 ++++++++++++++++++ 7 files changed, 35 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index b28e0cf..86f5585 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -35,7 +35,9 @@ "TTB subtable region must be evenly divisible by table size!"); /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) \ + REGION(stack, addr, size, 8) \ + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); #define DMA_COHERENT(addr, size) \ REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \ diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index 522f1ab..30db848 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -27,7 +27,9 @@ /* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks * in BSS, so this is only used for the SRAM stages. */ #ifdef __PRE_RAM__ -#define STACK(addr, size) REGION(stack, addr, size, 16) +#define STACK(addr, size) \ + REGION(stack, addr, size, 16) \ + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); #else #define STACK(addr, size) REGION(preram_stack, addr, size, 16) #endif diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index 9493173..946fcf3 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -24,7 +24,9 @@ /* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */ /* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) \ + REGION(stack, addr, size, 8) \ + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 91fd5d3..690b277 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -95,6 +95,9 @@ static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, return ret; } +/* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstack-usage=" int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) { @@ -111,6 +114,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, return ret; } +#pragma GCC diagnostic pop static int spi_flash_cmd_read_array(struct spi_slave *spi, u8 *cmd, size_t cmd_len, u32 offset, diff --git a/src/lib/gpio.c b/src/lib/gpio.c index b185cc2..72bd7ec 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -17,6 +17,7 @@ * Foundation, Inc. */ +#include <assert.h> #include <base3.h> #include <console/console.h> #include <delay.h> @@ -53,7 +54,8 @@ int gpio_base3_value(gpio_t gpio[], int num_gpio) int temp; int index; int result = 0; - char value[num_gpio]; + char value[32]; + assert(num_gpio <= 32); /* Enable internal pull up */ for (index = 0; index < num_gpio; ++index) diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c index 2a2a956..7803d39 100644 --- a/src/vendorcode/google/chromeos/vboot2/verstage.c +++ b/src/vendorcode/google/chromeos/vboot2/verstage.c @@ -119,7 +119,7 @@ static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) { uint64_t load_ts; uint32_t expected_size; - MAYBE_STATIC uint8_t block[TODO_BLOCK_SIZE]; + uint8_t block[TODO_BLOCK_SIZE]; size_t block_size = sizeof(block); size_t offset; int rv; diff --git a/toolchain.inc b/toolchain.inc index 89bc55c..eea0560 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -74,6 +74,24 @@ CFLAGS_riscv += -ffunction-sections -fdata-sections CFLAGS_x86_64 += -mcmodel=large -mno-red-zone +# Some boards only provide 2K stacks, so storing lots of data there leads to +# problems. Since C rules don't allow us to statically determine the maximum +# stack use, we use 1.5K as heuristic, assuming that we typically have lots +# of tiny stack frames and the odd large one. +# +# Store larger buffers in BSS, use MAYBE_STATIC to share code with __PRE_RAM__ +# on x86. +# Since GCCs detection of dynamic array bounds unfortunately seems to be +# very basic, you'll sometimes have to use a static upper bound for the +# size and an assert() to make sure it's honored (see gpio_base3_value() +# for an example). +# (If you absolutely need a larger stack frame and are 100% sure it cannot +# cause problems, you can whitelist it with #pragma diagnostic.) +CFLAGS_arm += -Wstack-usage=1536 +CFLAGS_arm64 += -Wstack-usage=1536 +CFLAGS_mips += -Wstack-usage=1536 +CFLAGS_riscv += -Wstack-usage=1536 + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \

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Patch merged into coreboot/master: glados: Support reading memory strap GPIOs to select SPD
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit d8d686663c3a9bd8cbcfb2b7a0d81ce4af678779 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 22 09:21:29 2015 -0700 glados: Support reading memory strap GPIOs to select SPD Add some board specific code to enable the memory configuration GPIOs in GPIO input mode and read them to determine which memory type is on the board. Also add the other memory types that are not yet present in the glados mainboard directory. This should be replaced with the real gpio infrastructure once it is ready. BUG=chrome-os-partner:43069 BRANCH=none TEST=build and boot on glados Change-Id: I7a9ce10e92ad6681528572e87b6cfee29880841a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d81e969c5950fd89bb745d1403abddb08a942f83 Original-Change-Id: Iffb0bd5c176f2adbdd9302d9bff5b7bde725d671 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287436 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11046 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11046 for details. -gerrit

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Patch merged into coreboot/master: skylake: Fix building without serial console
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit 31be8e403f65a3e086168bf088355ba71368531c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 22 09:24:23 2015 -0700 skylake: Fix building without serial console In order to build without CONFIG_CONSOLE_SERIAL the Skylake SOC Kconfig should not be enabling serial console by default. Also fix other compile issues when serial console is disabled. BUG=chrome-os-partner:40857 BRANCH=none TEST=build glados without serial console enabled Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55 Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287438 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11043 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11043 for details. -gerrit

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Patch merged into coreboot/master: glados: Enable internal pullup for EC_IN_RW
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit efa615734e26b65f411f754bbcbbae1202cd7cbf Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 22 09:22:13 2015 -0700 glados: Enable internal pullup for EC_IN_RW Enable 20K internal pullup for the EC_IN_RW GPIO. BUG=chrome-os-partner:42285 BRANCH=none TEST=build and boot on glados Change-Id: I499164fb5050d350510072d2a06eb97fb7f9fcb1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e2de7d4800797a1585165a34dd39af3d635b1f55 Original-Change-Id: I7af1b78482197701aa452998106c2c3476fcc330 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/287437 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11045 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11045 for details. -gerrit

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Patch merged into coreboot/master: glados: Add ACPI configs for speaker amps and codec
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit 1051bb40427ef1c9384cd5755ff245dc7378aca1 Author: Ben Zhang <benzh(a)chromium.org> Date: Fri Jun 26 17:17:53 2015 -0700 glados: Add ACPI configs for speaker amps and codec The audio codec nau8825 and two ssm4567 speaker amps are instantiated via ACPI. BUG=chrome-os-partner:41280 BRANCH=none TEST=The devices are instantiated. Speaker/headphone playback works on glados. Change-Id: I1297c2435b3051dd749ad7de324b64ba1504cf09 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 59e5eb2682a2fc2cb58068dfcb6dd2415d43b286 Original-Change-Id: Ib7ec8c868251601f67cdf365cd3e935d256c8ac5 Original-Signed-off-by: Ben Zhang <benzh(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/282364 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11044 for details. -gerrit

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Patch merged into coreboot/master: rockchip: rk3288: extend jerry backlight vcc_led delay time
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit 05389de33b41d2a684ab311bdd0369af1b3f4fff Author: huang lin <hl(a)rock-chips.com> Date: Wed Jul 22 10:49:11 2015 +0800 rockchip: rk3288: extend jerry backlight vcc_led delay time some jerry panels need more delay time between the vcc_led and bl_en, so we extend the delay time from 20ms to 120ms. BUG=chrome-os-partner:42997 TEST=Boot from jerry, and do not flicker again BRANCH=none Change-Id: Ifcf84578038eb5c2e5a0dfae936ee63cef671968 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0b00b6bd108f0aae461085d00819eca08ec892b3 Original-Change-Id: I74999601b41ccac22493cc9cd0bf52cd4dbb8c26 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287373 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11042 for details. -gerrit

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Patch set updated for coreboot: rockchip: rk3288: extend jerry backlight vcc_led delay time
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11042 -gerrit commit f9e30663069dde7db06851986fa3438a65c23dba Author: huang lin <hl(a)rock-chips.com> Date: Wed Jul 22 10:49:11 2015 +0800 rockchip: rk3288: extend jerry backlight vcc_led delay time some jerry panels need more delay time between the vcc_led and bl_en, so we extend the delay time from 20ms to 120ms. BUG=chrome-os-partner:42997 TEST=Boot from jerry, and do not flicker again BRANCH=none Change-Id: Ifcf84578038eb5c2e5a0dfae936ee63cef671968 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0b00b6bd108f0aae461085d00819eca08ec892b3 Original-Change-Id: I74999601b41ccac22493cc9cd0bf52cd4dbb8c26 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287373 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_jerry/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c index 7412243..2a945c4 100644 --- a/src/mainboard/google/veyron_jerry/mainboard.c +++ b/src/mainboard/google/veyron_jerry/mainboard.c @@ -158,7 +158,7 @@ void mainboard_power_on_backlight(void) break; default: gpio_output(GPIO(2, B, 4), 1); /* BL_PWR_EN */ - mdelay(20); + mdelay(120); gpio_output(GPIO(7, A, 0), 1); /* LCD_BL */ mdelay(10); gpio_output(GPIO_BACKLIGHT, 1); /* BL_EN */

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Patch merged into coreboot/master: tegra210: Fix parameter order of write32()
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit 5bd030d37a93719819636479037bf9c999845db9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 14 12:07:56 2015 -0700 tegra210: Fix parameter order of write32() The correct function prototype is void write32(void *addr, uint32_t val) BUG=chrome-os-partner:38073 BRANCH=none TEST=build lp0 code and see it succeed. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Change-Id: Icadc9e2d142e5a222509e894f43b0c8a70eed031 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b46635d9d3ee1ca364e7ad6d6dd7ea9efa9dedbc Original-Change-Id: Id2b6847af80dfddcb3b7133a663becb78ed477ba Original-Reviewed-on: https://chromium-review.googlesource.com/285544 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Original-Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11049 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11049 for details. -gerrit

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Patch merged into coreboot/master: tegra lp0: fix checkpatch errors
by gerrit＠coreboot.org 24 Jul '15

24 Jul '15

the following patch was just integrated into master: commit 775f833c559b59737a0c69c669f5d754cc820d05 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 14 12:00:28 2015 -0700 tegra lp0: fix checkpatch errors The checkpatch.pl scripts complains about the placing of the inline keyword: ERROR: inline keyword should sit between storage class and type Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> BUG=chrome-os-partner:38073 BRANCH=none TEST=repo upload works ;) Change-Id: Ibd2b8a437eda2fc720f8fc32c5821bae3be41d12 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d20c0d34240966d5ae39c1667d4486b4341e183b Original-Change-Id: I36d600c4677c622c334d849bf260323592a8a4fc Original-Reviewed-on: https://chromium-review.googlesource.com/285543 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Original-Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11048 for details. -gerrit

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New patch to review for coreboot: tegra210: Fix parameter order of write32()
by Patrick Georgi 24 Jul '15

24 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11049 -gerrit commit 1ab03d1b2829cad0eb6ff7258376ac171a67639b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Jul 14 12:07:56 2015 -0700 tegra210: Fix parameter order of write32() The correct function prototype is void write32(void *addr, uint32_t val) BUG=chrome-os-partner:38073 BRANCH=none TEST=build lp0 code and see it succeed. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Change-Id: Icadc9e2d142e5a222509e894f43b0c8a70eed031 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b46635d9d3ee1ca364e7ad6d6dd7ea9efa9dedbc Original-Change-Id: Id2b6847af80dfddcb3b7133a663becb78ed477ba Original-Reviewed-on: https://chromium-review.googlesource.com/285544 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Original-Tested-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index cf9c212..fdd25dd 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -413,7 +413,7 @@ static inline uint32_t read32(const void *addr) return *(volatile uint32_t *)addr; } -static inline void write32(uint32_t val, void *addr) +static inline void write32(void *addr, uint32_t val) { *(volatile uint32_t *)addr = val; }

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coreboot-gerrit July 2015