coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/haswell: fix CHROMEOS builds for haswell
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11061 -gerrit commit 08fc2570b87938197baa346c9a74dc8838437aef Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:17:14 2015 +0200 intel/haswell: fix CHROMEOS builds for haswell Compiler complained about potentially uninitialized variable. Fixes google/bolt, google/falco, google/panther, google/slippy BRANCH=none BUG=chromium:513990 TEST=the mentioned boards build with CONFIG_CHROMEOS=y Change-Id: Ia28c833bd6ef8e1f7c820a61b41ce456eba51246 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 4566c355cc6828ab96e8d52bfad6ccbf6be6f7ce Original-Change-Id: I4d9a685373362f8a092b325efee3f816c056c708 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288850 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/northbridge/intel/haswell/mrccache.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 481110f..eb603f6 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -65,6 +65,7 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { size_t region_size = 0; + *mrc_region_ptr = NULL; if (IS_ENABLED(CONFIG_CHROMEOS)) { struct region_device rdev;

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New patch to review for coreboot: BCRD2: Enable PMIC SVID config
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11060 -gerrit commit 50178a69b7a7816af0af41a6e6bf2cf1158ff915 Author: Jenny TC <jenny.tc(a)intel.com> Date: Thu Jun 18 14:55:10 2015 +0530 BCRD2: Enable PMIC SVID config Enable PMIC SVID config for BCRD2 based on board id. UPD parameter is used to select the SVID config and PMIC I2C bus number BRANCH=None BUG=None TEST=Build and boot the system Change-Id: I3c4c06bd25c241abdf46aa14af74eecf77cf77a6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 10bb8d4ad96d1187f6e135ca1535d70ae45ee887 Original-Change-Id: I9191db7bace4f4840e3c32381093c6c0806f7c32 Original-Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282156 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/braswell/chip.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index d70aa9b..7422bc4 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -30,8 +30,9 @@ #include <fsp_util.h> #include <soc/pci_devs.h> -#define SVID_CONFIG1 1 -#define SVID_CONFIG3 3 +#define SVID_CONFIG1 1 +#define SVID_CONFIG3 3 +#define SVID_PMIC_CONFIG 8 struct soc_intel_braswell_config { uint8_t enable_xdp_tap;

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Patch set updated for coreboot: arm, arm64, mips: Add rough static stack size checks with -Wstack-usage
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9729 -gerrit commit a358fe0c3d7795430e96c6fd7d6b21e0fb280fa2 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Dec 19 16:11:14 2014 -0800 arm, arm64, mips: Add rough static stack size checks with -Wstack-usage We've seen an increasing need to reduce stack sizes more and more for space reasons, and it's always guesswork because no one has a good idea how little is too litte. We now have boards with 3K and 2K stacks, and old pieces of common code often allocate large temporary buffers that would lead to very dangerous and hard to detect bugs when someone eventually tries to use them on one of those. This patch tries improve this situation at least a bit by declaring 2K as the minimum stack size all of coreboot code should work with. It checks all function frames with -Wstack-usage=1536 to make sure we don't allocate more than 1.5K in a single buffer. This is of course not a perfect test, but it should catch the most common situation of declaring a single, large buffer in some close-to-leaf function (with the assumption that 0.5K is hopefully enough for all the "normal" functions above that). Change one example where we were a bit overzealous and put a 1K buffer into BSS back to stack allocation, since it actually conforms to this new assumption and frees up another kilobyte of that highly sought-after verstage space. Not touching x86 with any of this since it's lack of __PRE_RAM__ BSS often requires it to allocate way more on the stack than would usually be considered sane. BRANCH=veyron BUG=None TEST=Compiled Cosmos, Daisy, Falco, Blaze, Pit, Storm, Urara and Pinky, made sure they still build as well as before and don't show any stack usage warnings. Change-Id: Idc53d33bd8487bbef49d3ecd751914b0308006ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8e5931066575e256dfc2295c3dab7f0e1b65417f Original-Change-Id: I30bd9c2c77e0e0623df89b9e5bb43ed29506be98 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236978 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/include/arch/memlayout.h | 4 +++- src/arch/arm64/include/arch/memlayout.h | 4 +++- src/arch/mips/include/arch/memlayout.h | 4 +++- src/drivers/spi/spi_flash.c | 4 ++++ src/lib/gpio.c | 4 +++- src/vendorcode/google/chromeos/vboot2/verstage.c | 2 +- toolchain.inc | 18 ++++++++++++++++++ 7 files changed, 35 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h index b28e0cf..86f5585 100644 --- a/src/arch/arm/include/arch/memlayout.h +++ b/src/arch/arm/include/arch/memlayout.h @@ -35,7 +35,9 @@ "TTB subtable region must be evenly divisible by table size!"); /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) \ + REGION(stack, addr, size, 8) \ + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); #define DMA_COHERENT(addr, size) \ REGION(dma_coherent, addr, size, SUPERPAGE_SIZE) \ diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index 522f1ab..30db848 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -27,7 +27,9 @@ /* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks * in BSS, so this is only used for the SRAM stages. */ #ifdef __PRE_RAM__ -#define STACK(addr, size) REGION(stack, addr, size, 16) +#define STACK(addr, size) \ + REGION(stack, addr, size, 16) \ + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); #else #define STACK(addr, size) REGION(preram_stack, addr, size, 16) #endif diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index 9493173..946fcf3 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -24,7 +24,9 @@ /* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */ /* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) \ + REGION(stack, addr, size, 8) \ + _ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc"); #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 91fd5d3..690b277 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -95,6 +95,9 @@ static int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, return ret; } +/* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstack-usage=" int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) { @@ -111,6 +114,7 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, return ret; } +#pragma GCC diagnostic pop static int spi_flash_cmd_read_array(struct spi_slave *spi, u8 *cmd, size_t cmd_len, u32 offset, diff --git a/src/lib/gpio.c b/src/lib/gpio.c index b185cc2..72bd7ec 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -17,6 +17,7 @@ * Foundation, Inc. */ +#include <assert.h> #include <base3.h> #include <console/console.h> #include <delay.h> @@ -53,7 +54,8 @@ int gpio_base3_value(gpio_t gpio[], int num_gpio) int temp; int index; int result = 0; - char value[num_gpio]; + char value[32]; + assert(num_gpio <= 32); /* Enable internal pull up */ for (index = 0; index < num_gpio; ++index) diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c index 2a2a956..7803d39 100644 --- a/src/vendorcode/google/chromeos/vboot2/verstage.c +++ b/src/vendorcode/google/chromeos/vboot2/verstage.c @@ -119,7 +119,7 @@ static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) { uint64_t load_ts; uint32_t expected_size; - MAYBE_STATIC uint8_t block[TODO_BLOCK_SIZE]; + uint8_t block[TODO_BLOCK_SIZE]; size_t block_size = sizeof(block); size_t offset; int rv; diff --git a/toolchain.inc b/toolchain.inc index 89bc55c..eea0560 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -74,6 +74,24 @@ CFLAGS_riscv += -ffunction-sections -fdata-sections CFLAGS_x86_64 += -mcmodel=large -mno-red-zone +# Some boards only provide 2K stacks, so storing lots of data there leads to +# problems. Since C rules don't allow us to statically determine the maximum +# stack use, we use 1.5K as heuristic, assuming that we typically have lots +# of tiny stack frames and the odd large one. +# +# Store larger buffers in BSS, use MAYBE_STATIC to share code with __PRE_RAM__ +# on x86. +# Since GCCs detection of dynamic array bounds unfortunately seems to be +# very basic, you'll sometimes have to use a static upper bound for the +# size and an assert() to make sure it's honored (see gpio_base3_value() +# for an example). +# (If you absolutely need a larger stack frame and are 100% sure it cannot +# cause problems, you can whitelist it with #pragma diagnostic.) +CFLAGS_arm += -Wstack-usage=1536 +CFLAGS_arm64 += -Wstack-usage=1536 +CFLAGS_mips += -Wstack-usage=1536 +CFLAGS_riscv += -Wstack-usage=1536 + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \

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Patch set updated for coreboot: veyron: update mickey sdram-lpddr3-samsung-2GB.inc
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11051 -gerrit commit 109d0d887284cb891bb285550fd7b5fca50469f2 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Jul 23 11:51:51 2015 +0800 veyron: update mickey sdram-lpddr3-samsung-2GB.inc Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This resolves an issue that was observed on some Mickey boards with the Samsung 2GB LPDDR3 and is believed to be caused by inferior routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.) BUG=chrome-os-partner:41905 TEST=Boot from mickey BRANCH=None Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286333 --- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc index 0f15ba5..cc39f62 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -65,7 +65,8 @@ .mr[0] = 0x0, .mr[1] = 0xC3, .mr[2] = 0x6, - .mr[3] = 0x1 + /* 60Ohms instead of 34.3 due to bad PCB routing on Mickey. */ + .mr[3] = 0x4 }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6,

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Patch set updated for coreboot: Revert "smaug: Do not gate XUSB partitions"
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11050 -gerrit commit 5a13db126413ba3cbebc62d2c3d2aa887fa5481d Author: Andrew Bresticker <abrestic(a)chromium.org> Date: Mon Jul 20 10:34:06 2015 -0700 Revert "smaug: Do not gate XUSB partitions" The PLLU and UTMIPLL power-up sequences have been fixed in the kernel. It's no longer necessary for the XUSB partitions to be ungated at boot. This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7. BUG=chrome-os-partner:41244 TEST=Build and boot on Smaug; xHCI still works. BRANCH=none CQ-DEPEND=CL:282765 Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1 Original-Signed-off-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286810 Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Mark Kuo <mkuo(a)nvidia.com> Original-Reviewed-by: Mark Kuo <mkuo(a)nvidia.com> --- src/mainboard/google/smaug/mainboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c index 1a197b4..1cf4d32 100644 --- a/src/mainboard/google/smaug/mainboard.c +++ b/src/mainboard/google/smaug/mainboard.c @@ -178,6 +178,9 @@ static void powergate_unused_partitions(void) static const uint32_t partitions[] = { POWER_PARTID_PCX, POWER_PARTID_SAX, + POWER_PARTID_XUSBA, + POWER_PARTID_XUSBB, + POWER_PARTID_XUSBC, POWER_PARTID_NVDEC, POWER_PARTID_NVJPG, POWER_PARTID_DFD,

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Patch set updated for coreboot: skylake: Rework microcode include path
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11053 -gerrit commit 752094346588905c8b2fed97717d8c6ab5dd36be Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 13 10:44:05 2015 -0700 skylake: Rework microcode include path Remove the microcode include path config options and include the mainboard blob directory by default. BUG=chrome-os-partner:42109 BRANCH=none TEST=emerge-glados coreboot CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922 Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448 Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285150 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 9 --------- src/soc/intel/skylake/microcode/Makefile.inc | 3 --- src/soc/intel/skylake/microcode/microcode_blob.c | 2 +- src/soc/intel/skylake/microcode/microcode_blob.h | 21 --------------------- 4 files changed, 1 insertion(+), 34 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d3c541d..d21fe3a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -96,11 +96,6 @@ config DCACHE_RAM_SIZE The size of the cache-as-ram region required during bootblock and/or romstage. -config EXTRA_MICROCODE_INCLUDE_PATH - string "Include path for extra microcode patches." - help - The path to any extra microcode patches from other sources. - config HAVE_IFD_BIN bool "Use Intel Firmware Descriptor from existing binary" default n @@ -166,10 +161,6 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" -config MICROCODE_INCLUDE_PATH - string - default "src/soc/intel/skylake/microcode" - config MMCONF_BASE_ADDRESS hex "MMIO Base Address" default 0xe0000000 diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index 2356b84..a5e8981 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,9 +1,6 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c -# Include path for addition microcode sources. -INCLUDES += -I$(CONFIG_EXTRA_MICROCODE_INCLUDE_PATH) - # This section overrides the default build process for the microcode to place # it at a known location in the CBFS. This only needs to be enabled if FSP is # being used. diff --git a/src/soc/intel/skylake/microcode/microcode_blob.c b/src/soc/intel/skylake/microcode/microcode_blob.c index 511c899..48c1aa2 100644 --- a/src/soc/intel/skylake/microcode/microcode_blob.c +++ b/src/soc/intel/skylake/microcode/microcode_blob.c @@ -19,6 +19,6 @@ */ unsigned int microcode[] = { -#include "microcode_blob.h" +#include <microcode/microcode_blob.h> }; diff --git a/src/soc/intel/skylake/microcode/microcode_blob.h b/src/soc/intel/skylake/microcode/microcode_blob.h deleted file mode 100644 index 82a8664..0000000 --- a/src/soc/intel/skylake/microcode/microcode_blob.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include "MC0406E2_00000017_00000018.h"

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Patch set updated for coreboot: Skylake: Fix Microcode reload in bootblock cpu init
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11052 -gerrit commit 25f184202154ec484205cd9db37704b1e754a097 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jul 7 18:18:15 2015 +0530 Skylake: Fix Microcode reload in bootblock cpu init For Skylake Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in the bootblock cpu init. Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286054 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/bootblock/cpu.c | 20 +++++++++++++++++++- src/soc/intel/skylake/include/soc/msr.h | 2 +- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index d4506e5..3c893f6 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -180,9 +180,27 @@ static void check_for_clean_reset(void) static void bootblock_cpu_init(void) { + const struct microcode *patch; + u32 current_rev; + msr_t msr; + /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); check_for_clean_reset(); enable_rom_caching(); - intel_update_microcode_from_cbfs(); + + patch = intel_microcode_find(); + + current_rev = read_microcode_rev(); + + /* If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during early cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + if (msr.lo & PRMRR_SUPPORTED && current_rev != patch->rev - 1) { + intel_update_microcode_from_cbfs(); + } } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index b857dbe..3903757 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -105,6 +105,6 @@ /* MTRRcap_MSR bits */ #define SMRR_SUPPORTED (1<<11) -#define EMRR_SUPPORTED (1<<12) +#define PRMRR_SUPPORTED (1<<12) #endif

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Patch set updated for coreboot: Add SoC specific microcode update check in ramstage
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11055 -gerrit commit 5de053a4aabec73b43b522170c87525f61480e1c Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:31:51 2015 +0530 Add SoC specific microcode update check in ramstage Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid relading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++ src/include/cpu/intel/microcode.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 3492bfd..1ee1299 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,6 +28,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> +#include <rules.h> #if !defined(__PRE_RAM__) #include <cbfs.h> @@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; +#if ENV_RAMSTAGE + /*SoC specific check to update microcode*/ + if (soc_ucode_update_required(current_rev, m->rev) < 0) { + printk(BIOS_DEBUG, "Skip microcode update\n"); + return; + } +#endif + msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); @@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } + +#if ENV_RAMSTAGE +__attribute__((weak)) int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id) +{ + return 0; +} +#endif diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index d2fa1b7..d951a63 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -29,6 +29,10 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); + +/* SoC specific check to determine if microcode update is really + * required, return value of < 0 will skip microcode update. */ +int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id); #endif #endif

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Patch set updated for coreboot: skylake: remove the redundant fspNotify in chip final.
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11054 -gerrit commit 5529cb4db663092bffd878c4acc95f61556ed96a Author: robbie zhang <robbie.zhang(a)intel.com> Date: Thu Jul 23 17:31:56 2015 -0700 skylake: remove the redundant fspNotify in chip final. The fspNotify(EnumInitPhaseAfterPciEnumeration) is already registered in fsp_util.c as a generic callback, this is some code left from early development. Also I don't see a need for the chip_final function, although we could keep it as a placeholder but i decided to remove it. BUG=chrome-os-partner:42979 BRANCH=None TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3. Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7 Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287991 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/chip.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f1a104c..b1b66fc 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -38,17 +38,8 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_bus_default_ops, }; -static void chip_final(device_t dev) -{ - /* Notify FSP done device setup */ - printk(BIOS_DEBUG, - "Calling FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - fsp_notify(EnumInitPhaseAfterPciEnumeration); -} - static struct device_operations cpu_bus_ops = { .init = &soc_init_cpus, - .final = &chip_final, }; static void soc_enable(device_t dev)

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Patch set updated for coreboot: skylake: Update microcode reload in ramstage.
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11056 -gerrit commit ad42b92809ff811e0387049b6f8018e6e0fdc83b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:40:53 2015 +0530 skylake: Update microcode reload in ramstage. For Skylake, Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootclock and ramstage (MP init). Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:287513 Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287674 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index cd88c10..97b928d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -574,3 +574,19 @@ void soc_init_cpus(device_t dev) if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) restore_default_smm_area(smm_save_area); } + +int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id) +{ + msr_t msr; + /* If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + if ((msr.lo & PRMRR_SUPPORTED) && currrent_patch_id == new_patch_id - 1) { + return -1; + } + return 0; +}

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coreboot-gerrit July 2015