coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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1048 discussions

Patch merged into coreboot/master: Revert "smaug: Do not gate XUSB partitions"
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 3bc4373797d34fe90efb2c8263a864f74879e613 Author: Andrew Bresticker <abrestic(a)chromium.org> Date: Mon Jul 20 10:34:06 2015 -0700 Revert "smaug: Do not gate XUSB partitions" The PLLU and UTMIPLL power-up sequences have been fixed in the kernel. It's no longer necessary for the XUSB partitions to be ungated at boot. This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7. BUG=chrome-os-partner:41244 TEST=Build and boot on Smaug; xHCI still works. BRANCH=none CQ-DEPEND=CL:282765 Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1 Original-Signed-off-by: Andrew Bresticker <abrestic(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286810 Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Mark Kuo <mkuo(a)nvidia.com> Original-Reviewed-by: Mark Kuo <mkuo(a)nvidia.com> Reviewed-on: http://review.coreboot.org/11050 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11050 for details. -gerrit

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Patch merged into coreboot/master: intel/braswell: fix build
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 5468e94df1f1f017a936a2a619e57741ecfbd132 Author: Jenny TC <jenny.tc(a)intel.com> Date: Thu Jun 18 14:02:00 2015 +0530 intel/braswell: fix build Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained additions to braswell's chip.h which were lost during merging. BRANCH=None BUG=None TEST=google/strago builds Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912 Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e Original-Original-Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155 Original-Reviewed-on: https://chromium-review.googlesource.com/288880 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11065 for details. -gerrit

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Patch merged into coreboot/master: BCRD2: Enable PMIC SVID config
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 153ae105e5c928982b50d1599e626ae6ff494824 Author: Jenny TC <jenny.tc(a)intel.com> Date: Thu Jun 18 14:55:10 2015 +0530 BCRD2: Enable PMIC SVID config Enable PMIC SVID config for BCRD2 based on board id. UPD parameter is used to select the SVID config and PMIC I2C bus number BRANCH=None BUG=None TEST=Build and boot the system Change-Id: I3c4c06bd25c241abdf46aa14af74eecf77cf77a6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 10bb8d4ad96d1187f6e135ca1535d70ae45ee887 Original-Change-Id: I9191db7bace4f4840e3c32381093c6c0806f7c32 Original-Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282156 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11060 for details. -gerrit

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Patch merged into coreboot/master: google/stout: Implement functions required by CHROMEOS
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 556538af85fc1d6387e8af86fae67e26b0524d63 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:18:15 2015 +0200 google/stout: Implement functions required by CHROMEOS BRANCH=none BUG=chromium:513990 TEST=google/stout builds Change-Id: I00de7524297e4471a9f7d6afd0d2b991d29020e9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: b85c54af7d4def45f014ee1d9b79df0b649f90f7 Original-Change-Id: I0870dd11c97cecc932a135f73be8234a88c0622b Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288860 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11064 for details. -gerrit

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Patch merged into coreboot/master: google/parrot: Implement functions required by CHROMEOS
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit c3f72751f8c692f9c763aadf22409937c938f426 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:18:15 2015 +0200 google/parrot: Implement functions required by CHROMEOS BRANCH=none BUG=chromium:513990 TEST=google/parrot builds Change-Id: I5e354d6160e554f1c41e84eac6102e84de34b81d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: d5a6253e6f19815736a6b433f6c58e3be2e5841b Original-Change-Id: I3a3bf9ead333d56472f856c9efefff239fb70586 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288852 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11063 for details. -gerrit

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Patch merged into coreboot/master: google/butterfly: Implement functions required by CHROMEOS
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 5e0a2e2d33433b564d121a20e5ab7726c74713ec Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:18:15 2015 +0200 google/butterfly: Implement functions required by CHROMEOS BRANCH=none BUG=chromium:513990 TEST=google/butterfly builds Change-Id: Ia678ca4b0778ee4a2e55ba44a5d89ac6dd691b35 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 0d82ea2090fae9c66f41ee05cc20a9b22d3641c0 Original-Change-Id: I2fea10c17b769ca76b9d0b80978b4c512ed8c680 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288851 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11062 for details. -gerrit

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Patch merged into coreboot/master: intel/haswell: fix CHROMEOS builds for haswell
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 7a625da84fee2659e38b17d7170823538911f044 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:17:14 2015 +0200 intel/haswell: fix CHROMEOS builds for haswell Compiler complained about potentially uninitialized variable. Fixes google/bolt, google/falco, google/panther, google/slippy BRANCH=none BUG=chromium:513990 TEST=the mentioned boards build with CONFIG_CHROMEOS=y Change-Id: Ia28c833bd6ef8e1f7c820a61b41ce456eba51246 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 4566c355cc6828ab96e8d52bfad6ccbf6be6f7ce Original-Change-Id: I4d9a685373362f8a092b325efee3f816c056c708 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288850 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-on: http://review.coreboot.org/11061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11061 for details. -gerrit

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Patch merged into coreboot/master: skylake: remove the redundant fspNotify in chip final.
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit bf0902eb83cad554e7bb4993dcfae648d68e821f Author: robbie zhang <robbie.zhang(a)intel.com> Date: Thu Jul 23 17:31:56 2015 -0700 skylake: remove the redundant fspNotify in chip final. The fspNotify(EnumInitPhaseAfterPciEnumeration) is already registered in fsp_util.c as a generic callback, this is some code left from early development. Also I don't see a need for the chip_final function, although we could keep it as a placeholder but i decided to remove it. BUG=chrome-os-partner:42979 BRANCH=None TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3. Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7 Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287991 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11054 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11054 for details. -gerrit

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Patch merged into coreboot/master: skylake: Rework microcode include path
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit b10f42bb0a25c7e84c1edb72f87b172f762b2816 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 13 10:44:05 2015 -0700 skylake: Rework microcode include path Remove the microcode include path config options and include the mainboard blob directory by default. BUG=chrome-os-partner:42109 BRANCH=none TEST=emerge-glados coreboot CQ-DEPEND=CL:*221987, CL:*222225, CL:*222195, CL:285922 Change-Id: Ie959c7e8413afbfdafdbc87c80b6fbebaee5fea1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce988b08ef1d81b08994d689f3fe273d2fc2f448 Original-Change-Id: I12d0d60df0d8c366d4478ceae88eba9fb058e4b8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/285150 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11053 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11053 for details. -gerrit

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New patch to review for coreboot: skylake: clean-up pei_data
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11072 -gerrit commit 617bf858a52a289a350609deee146e195c15dc5e Author: robbie zhang <robbie.zhang(a)intel.com> Date: Mon Jul 27 14:40:23 2015 -0700 skylake: clean-up pei_data Remove the items that are obviously broadwell left or become no-need with fsp. BUG=chrome-os-partner:43186 BRANCH=None TEST=build and boot on sklrvp3. Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010 Original-Reviewed-on: https://chromium-review.googlesource.com/288833 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang(a)intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/mainboard/google/glados/pei_data.c | 3 - src/mainboard/intel/kunimitsu/pei_data.c | 3 - src/mainboard/intel/sklrvp/pei_data.c | 3 - src/soc/intel/skylake/include/soc/iomap.h | 6 -- src/soc/intel/skylake/include/soc/pei_data.h | 96 ------------------------- src/soc/intel/skylake/include/soc/pei_wrapper.h | 19 ----- src/soc/intel/skylake/pei_data.c | 9 --- 7 files changed, 139 deletions(-) diff --git a/src/mainboard/google/glados/pei_data.c b/src/mainboard/google/glados/pei_data.c index 677ea32..55d7f08 100644 --- a/src/mainboard/google/glados/pei_data.c +++ b/src/mainboard/google/glados/pei_data.c @@ -43,9 +43,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; pei_data->ec_present = 1; - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index e8d7562..af9462f 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -43,9 +43,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; pei_data->ec_present = 1; - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/intel/sklrvp/pei_data.c b/src/mainboard/intel/sklrvp/pei_data.c index 6c42f28..b5302b9 100644 --- a/src/mainboard/intel/sklrvp/pei_data.c +++ b/src/mainboard/intel/sklrvp/pei_data.c @@ -45,9 +45,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; pei_data->ec_present = 1; - /* One installed DIMM per channel */ - pei_data->dimm_channel0_disabled = 2; - pei_data->dimm_channel1_disabled = 2; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 920b6f6..c478daf 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -60,10 +60,4 @@ #define SMBUS_BASE_ADDRESS 0x0400 #define SMBUS_BASE_SIZE 0x10 -/* Temporary addresses used in romstage */ -#define EARLY_GTT_BAR 0xe0000000 -#define EARLY_XHCI_BAR 0xd7000000 -#define EARLY_UART_BAR CONFIG_TTYS0_BASE -#define EARLY_TEMP_MMIO 0xfed08000 - #endif diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h index 2328436..2773051 100644 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ b/src/soc/intel/skylake/include/soc/pei_data.h @@ -38,108 +38,12 @@ typedef void ABI_X86(*tx_byte_func)(unsigned char byte); -enum board_type { - BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */ - BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */ - BOARD_TYPE_USER1, /* SV mobile */ - BOARD_TYPE_USER2, /* SV desktop */ - BOARD_TYPE_USER3, /* SV server */ - BOARD_TYPE_ULT, /* ULT */ - BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */ - BOARD_TYPE_UNKNOWN, -}; - -#define MAX_USB2_PORTS 14 -#define MAX_USB3_PORTS 6 -#define USB_OC_PIN_SKIP 8 - -enum usb2_port_location { - USB_PORT_BACK_PANEL = 0, - USB_PORT_FRONT_PANEL, - USB_PORT_DOCK, - USB_PORT_MINI_PCIE, - USB_PORT_FLEX, - USB_PORT_INTERNAL, - USB_PORT_SKIP, - USB_PORT_NGFF_DEVICE_DOWN, -}; - -struct usb2_port_setting { - /* - * Usb Port Length: - * [16:4] = length in inches in octal format - * [3:0] = decimal point - */ - uint16_t length; - uint8_t enable; - uint8_t oc_pin; - uint8_t location; -} __attribute__((packed)); - -struct usb3_port_setting { - uint8_t enable; - uint8_t oc_pin; - /* - * Set to 0 if trace length is > 5 inches - * Set to 1 if trace length is <= 5 inches - */ - uint8_t fixed_eq; -} __attribute__((packed)); - struct pei_data { uint32_t pei_version; - enum board_type board_type; int boot_mode; int ec_present; - /* Base addresses */ - uint32_t pciexbar; - uint16_t smbusbar; - uint32_t xhcibar; - uint32_t gttbar; - uint32_t pmbase; - uint32_t temp_mmio_base; - uint32_t tseg_size; - - /* - * 0 = leave channel enabled - * 1 = disable dimm 0 on channel - * 2 = disable dimm 1 on channel - * 3 = disable dimm 0+1 on channel - */ - int dimm_channel0_disabled; - int dimm_channel1_disabled; - /* Set to 0 for memory down */ - uint8_t spd_addresses[4]; - /* Enable 2x Refresh Mode */ - int ddr_refresh_2x; - /* DQ pins are interleaved on board */ - int dq_pins_interleaved; - /* Limit DDR3 frequency */ - int max_ddr3_freq; - /* Disable self refresh */ - int disable_self_refresh; - /* Disable cmd power/CKEPD */ - int disable_cmd_pwr; - - /* USB port configuration */ - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; - - /* - * USB3 board specific PHY tuning - */ - - /* Valid range: 0x69 - 0x80 */ - uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS]; - /* Valid range: 0x80 - 0x9c */ - uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS]; - /* Valid range: 0x39 - 0x80 */ - uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS]; - /* Valid range: 0x3d - 0x4a */ - uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS]; - /* Console output function */ tx_byte_func tx_byte; diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/soc/intel/skylake/include/soc/pei_wrapper.h index 7d37c10..7f48722 100644 --- a/src/soc/intel/skylake/include/soc/pei_wrapper.h +++ b/src/soc/intel/skylake/include/soc/pei_wrapper.h @@ -25,25 +25,6 @@ typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); -static inline void pei_data_usb2_port(struct pei_data *pei_data, int port, - uint16_t length, uint8_t enable, - uint8_t oc_pin, uint8_t location) -{ - pei_data->usb2_ports[port].length = length; - pei_data->usb2_ports[port].enable = enable; - pei_data->usb2_ports[port].oc_pin = oc_pin; - pei_data->usb2_ports[port].location = location; -} - -static inline void pei_data_usb3_port(struct pei_data *pei_data, int port, - uint8_t enable, uint8_t oc_pin, - uint8_t fixed_eq) -{ - pei_data->usb3_ports[port].enable = enable; - pei_data->usb3_ports[port].oc_pin = oc_pin; - pei_data->usb3_ports[port].fixed_eq = fixed_eq; -} - void soc_fill_pei_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c index b943224..47198a7 100644 --- a/src/soc/intel/skylake/pei_data.c +++ b/src/soc/intel/skylake/pei_data.c @@ -35,14 +35,5 @@ static void ABI_X86 send_to_console(unsigned char b) void soc_fill_pei_data(struct pei_data *pei_data) { pei_data->pei_version = PEI_VERSION; - pei_data->board_type = BOARD_TYPE_ULT; - pei_data->pciexbar = MCFG_BASE_ADDRESS; - pei_data->smbusbar = SMBUS_BASE_ADDRESS; - pei_data->xhcibar = EARLY_XHCI_BAR; - pei_data->gttbar = EARLY_GTT_BAR; - pei_data->pmbase = ACPI_BASE_ADDRESS; - pei_data->tseg_size = smm_region_size(); - pei_data->temp_mmio_base = EARLY_TEMP_MMIO; pei_data->tx_byte = &send_to_console; - pei_data->ddr_refresh_2x = 1; }

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coreboot-gerrit July 2015