coreboot-gerrit July 2015

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New patch to review for coreboot: Straighten up AMDs API
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11076 -gerrit commit fdbfe2f257a630aaa56c9a5c040d38e2e681bea7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 29 23:54:38 2015 -0700 Straighten up AMDs API There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. Change-Id: Idebf36c45367ec4dcd21cbe53a6c534857ab5dd7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/amd/dinar/rd890_cfg.c | 2 +- src/mainboard/amd/dinar/sb700_cfg.c | 2 +- src/northbridge/amd/cimx/rd890/amd.h | 2 +- src/vendorcode/amd/agesa/common/Porting.h | 24 ++++++++++++++---------- src/vendorcode/amd/cimx/sb700/SBTYPE.h | 2 +- src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 4 +++- src/vendorcode/amd/cimx/sb900/AmdSbLib.h | 4 ++-- src/vendorcode/amd/cimx/sb900/SbDef.h | 2 +- src/vendorcode/amd/cimx/sb900/SbMain.c | 2 +- src/vendorcode/amd/cimx/sb900/SbSubFun.h | 5 +++-- 10 files changed, 28 insertions(+), 21 deletions(-) diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index c90f9f0..13f18ec 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 53e93ce..2ce47ce 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -135,7 +135,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) #ifndef __PRE_RAM__ /* ramstage cimx config here */ if (!sb_config->StdHeader.pCallBack) { - sb_config->StdHeader.pCallBack = sb700_callout_entry; + sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } //sb_config-> diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index 5e69ac4..ade5a31 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -41,7 +41,7 @@ #define OUT #define IMAGE_SIGNATURE 'DMA$' -typedef UINTN AGESA_STATUS; +typedef UINT32 AGESA_STATUS; #define AGESA_SUCCESS ((AGESA_STATUS) 0x0) diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h index fc65cfc..3607c4a 100644 --- a/src/vendorcode/amd/agesa/common/Porting.h +++ b/src/vendorcode/amd/agesa/common/Porting.h @@ -216,6 +216,7 @@ #elif defined __GNUC__ + #include <stdint.h> #define IN #define OUT #define STATIC static @@ -228,17 +229,20 @@ #define CALLCONV #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + // Create the universal 32, 16, and 8-bit data types typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; + typedef uintptr_t UINTN; + typedef int64_t INT64; + typedef uint64_t UINT64; + typedef int32_t INT32; + typedef uint32_t UINT32; + typedef int16_t INT16; + typedef uint16_t UINT16; + typedef int8_t INT8; + typedef uint8_t UINT8; + typedef int8_t CHAR8; + typedef unsigned short CHAR16; typedef void VOID; //typedef unsigned long size_t; diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h index faeae5d..3dc571f 100644 --- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -32,7 +32,7 @@ #pragma pack(push,1) -typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig); typedef void (*SMM_SERVICE_ROUTINE) (void); typedef struct _STDCFG{ diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h index 9e50bf9..a50cda4 100644 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h +++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h @@ -46,6 +46,8 @@ #ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ #define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ +#include <cpu/amd/common/cbtypes.h> + //AMDSBLIB Routines /** @@ -105,7 +107,7 @@ AGESA_STATUS AmdSbDispatcher (IN void *pConfig); * @param[in] Length - Data length * */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /* SB800 CIMx and AGESA V5 can share lib functions */ diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h index cf9589b..47a7048 100644 --- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h +++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h @@ -69,10 +69,10 @@ unsigned char getEfuseByte (IN unsigned char Index); AGESA_STATUS AmdSbDispatcher (IN void *pConfig); /**< AmdSbCopyMem - Reserved */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /**< GetRomSigPtr - Reserved */ -void* GetRomSigPtr (IN unsigned int* RomSigPtr); +void* GetRomSigPtr (IN UINTN * RomSigPtr); /**< RWXhciIndReg - Reserved */ void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask); diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h index 91fec4a..b600627 100644 --- a/src/vendorcode/amd/cimx/sb900/SbDef.h +++ b/src/vendorcode/amd/cimx/sb900/SbDef.h @@ -71,7 +71,7 @@ void MemoryCopy ( IN unsigned char *Dest, IN unsigned char *Source, - IN unsigned int Size + IN unsigned long Size ); //AMD Library Routines (PCILIB.C) diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c index 958e44b..7c9dbbd 100644 --- a/src/vendorcode/amd/cimx/sb900/SbMain.c +++ b/src/vendorcode/amd/cimx/sb900/SbMain.c @@ -278,7 +278,7 @@ sbSmmAcpiOn ( UINTN CallBackToOEM ( IN UINT32 Func, - IN UINT32 Data, + IN UINTN Data, IN AMDSBCFG* pConfig ) { diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h index 447f5c9..68574a7 100644 --- a/src/vendorcode/amd/cimx/sb900/SbSubFun.h +++ b/src/vendorcode/amd/cimx/sb900/SbSubFun.h @@ -40,6 +40,7 @@ ; ;*********************************************************************************/ +#include <cpu/amd/common/cbtypes.h> // Southbridge SBMAIN Routines /** @@ -127,7 +128,7 @@ void sbSmmAcpiOn (IN AMDSBCFG* pConfig); * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig); +UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig); // Southbridge SBPOR Routines @@ -605,4 +606,4 @@ void TurnOffCG2 (OUT void); */ void BackUpCG2 (OUT void); -void XhciA12Fix (OUT void); \ No newline at end of file +void XhciA12Fix (OUT void);

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Patch set updated for coreboot: cpu/amd: Fix cbtypes.h to match UINTN convention
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10601 -gerrit commit d8025bf25d4fc5472db1bd6c3f82566260009433 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 19 16:42:58 2015 -0700 cpu/amd: Fix cbtypes.h to match UINTN convention UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/include/cpu/amd/common/cbtypes.h | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index 346f1a3..6a47e00 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -20,16 +20,20 @@ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ -typedef signed long long __int64; +/* Map coreboot stdint types to AGESA types. */ + +#include <stdint.h> + +typedef int64_t __int64; typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; +typedef uintptr_t UINTN; +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef int32_t INT32; +typedef uint64_t UINT64; +typedef uint8_t BOOLEAN; #define DMSG_SB_TRACE 0x02 #define TRACE(Arguments)

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Patch merged into coreboot/master: Add cscope/ctags generation for the current project
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit 9c1b33e74bbb0a6ebcfa66bad80cdaad83a5fdf4 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jul 29 14:55:18 2015 -0700 Add cscope/ctags generation for the current project Use the dependency files to generate ctags or cscope data for the current project instead of the entire coreboot tree. This isn't completely working for every platform at this point - while it finds all of the code in the coreboot/src tree, it doesn't find the code in 3rdparty right now. Change-Id: Ie8aabcf46c8a69f718940c9e0fd7e7b05c9ce1fb Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/11074 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/11074 for details. -gerrit

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Patch merged into coreboot/master: gigabyte/ga-b75m-d3h: Update device tree
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit d6cc617e171ddcaf83a8b6025d79025e13ba0cbb Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Jul 13 15:27:01 2015 +1000 gigabyte/ga-b75m-d3h: Update device tree This patch resolves the outstanding issues with PCI device enumeration and getting the board to boot into GNU/Linux with VGA rom. Previously the board would not boot to GNU/Linux with video, even if VGA rom was used. Bugs in the devicetree were fixed according to superiotool output. Tested on GA-B75M-D3H with VGA rom. Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64) Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/10895 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/10895 for details. -gerrit

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Patch merged into coreboot/master: vendorcode: 64bit fixes for AMD CIMX SB800
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit df3b8e66b3683f22bfe64924d8af3961735c9e44 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jun 17 16:05:05 2015 -0700 vendorcode: 64bit fixes for AMD CIMX SB800 Make SB800 code compile with x64 compiler These fixes probably apply 1:1 to the other SB components in that directory. Change-Id: I9ff9f27dff5074d2faf41ebc14bfe50871d9c7f7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10573 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/10573 for details. -gerrit

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Patch merged into coreboot/master: vendorcode: Port AMD Agesa for Fam14 to 64bit
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit 3e3f4008f8588a5762ce7b5474b9cf880101f171 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:16:40 2015 -0700 vendorcode: Port AMD Agesa for Fam14 to 64bit Change-Id: Ic6b3c3382a6d3fdc6d716ea899db598910b4fe3e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10581 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/10581 for details. -gerrit

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Patch merged into coreboot/master: SB800: Port to 64bit
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit 12bce3ff93334c14f388eea606a530737c5d9d21 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 01:17:38 2015 -0700 SB800: Port to 64bit Change-Id: I944fb254e9470c80b13c9eef9d6b1177a56e615f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> Reviewed-on: http://review.coreboot.org/10582 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/10582 for details. -gerrit

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Patch set updated for coreboot: cpu/amd: Fix cbtypes.h to match UINTN convention
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10601 -gerrit commit 9b138235a991aa342df433f0252bcecbd9d2f52d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 19 16:42:58 2015 -0700 cpu/amd: Fix cbtypes.h to match UINTN convention UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/include/cpu/amd/common/cbtypes.h | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index 346f1a3..6a47e00 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -20,16 +20,20 @@ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ -typedef signed long long __int64; +/* Map coreboot stdint types to AGESA types. */ + +#include <stdint.h> + +typedef int64_t __int64; typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; +typedef uintptr_t UINTN; +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef int32_t INT32; +typedef uint64_t UINT64; +typedef uint8_t BOOLEAN; #define DMSG_SB_TRACE 0x02 #define TRACE(Arguments)

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Patch merged into coreboot/master: README: improve description of compiler requirements
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit 221761e0be8fbf5ae5cae827216ae0e92c05c3af Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jul 23 21:08:30 2015 +0200 README: improve description of compiler requirements People run into "building bootblock without the required toolchain" too often. Update documentation so they don't try to use random compilers to build coreboot. Change-Id: I9715b52a4bac9b886cc5627add074c04e06a0828 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11047 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11047 for details. -gerrit

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Patch merged into coreboot/master: amd/bettong: Enable fan control
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit 6bd016cae80f7a5b1442f8254bb8be97c5d6d1ab Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Tue Jun 23 22:43:03 2015 +0800 amd/bettong: Enable fan control 1. Use enable_imc_thermal_zone to enable fan control. 2. The ACPI method ITZE works on Ubuntu 14.04 and Windows 7 but does not work on Windows 8, so I didn't use it. After this issue is fixed, I'll add ACPI_ENABLE_THERMAL_ZONE in bettong/Kconfig. 3. Fan control works on Bettong. I used "APU Validation Toolkit" to test on Windows 8. This tool can put load to APU. The fan's behaviour is just like bettong/fchec.c defined. When the temperature is 40 Celsius, the fan start to run. Change-Id: I0fc22974a7a7cf3f6bdf5f1c66be95219a177e12 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Reviewed-on: http://review.coreboot.org/10721 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/10721 for details. -gerrit

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coreboot-gerrit July 2015