coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

1 participants
1048 discussions

Patch set updated for coreboot: break lots of boards
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10594 -gerrit commit e7acaf3626e0310f59bf29821ea25ac039aae93f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:05:13 2015 -0700 break lots of boards Enable 64bit compilation for AGESA boards :-) Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 282e1ed..45e1d63 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

1 0

Patch set updated for coreboot: acpi: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11088 -gerrit commit 1e6d193c5a07d669022b8ac44598024a32cacd3b Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:28:13 2015 -0700 acpi: 64bit fixes Change-Id: I5d0c95af7d35115b5ac4141489caceef4ee1c8bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/acpi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 134e437..2194c48 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1051,13 +1051,13 @@ void *acpi_find_wakeup_vector(void) return NULL; printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); - rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; + rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; end = (char *)rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { - fadt = (acpi_fadt_t *)rsdt->entry[i]; + fadt = (acpi_fadt_t *)(uintptr_t)rsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) break; fadt = NULL; @@ -1067,7 +1067,7 @@ void *acpi_find_wakeup_vector(void) return NULL; printk(BIOS_DEBUG, "FADT found at %p\n", fadt); - facs = (acpi_facs_t *)fadt->firmware_ctrl; + facs = (acpi_facs_t *)(uintptr_t)fadt->firmware_ctrl; if (facs == NULL) { printk(BIOS_DEBUG, "No FACS found, wake up from S3 not " @@ -1076,7 +1076,7 @@ void *acpi_find_wakeup_vector(void) } printk(BIOS_DEBUG, "FACS found at %p\n", facs); - wake_vec = (void *)facs->firmware_waking_vector; + wake_vec = (void *)(uintptr_t)facs->firmware_waking_vector; printk(BIOS_DEBUG, "OS waking vector is %p\n", wake_vec); return wake_vec; @@ -1090,7 +1090,7 @@ extern int lowmem_backup_size; #define WAKEUP_BASE 0x600 -void (*acpi_do_wakeup)(u32 vector, u32 backup_source, u32 backup_target, +void (*acpi_do_wakeup)(uintptr_t vector, u32 backup_source, u32 backup_target, u32 backup_size) asmlinkage = (void *)WAKEUP_BASE; extern unsigned char __wakeup; @@ -1098,10 +1098,10 @@ extern unsigned int __wakeup_size; void acpi_jump_to_wakeup(void *vector) { - u32 acpi_backup_memory = 0; + uintptr_t acpi_backup_memory = 0; if (HIGH_MEMORY_SAVE && acpi_s3_resume_allowed()) { - acpi_backup_memory = (u32)cbmem_find(CBMEM_ID_RESUME); + acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); if (!acpi_backup_memory) { printk(BIOS_WARNING, "ACPI: Backup memory missing. " @@ -1124,7 +1124,7 @@ void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, + acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } #endif

1 0

Patch set updated for coreboot: smm: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11089 -gerrit commit c0421b0d45edf704100192fe81748eba10ba46c1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:28:44 2015 -0700 smm: 64bit fixes Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/x86/smm/Makefile.inc | 8 ++++++++ src/cpu/x86/smm/smihandler.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 239689e..2e61018 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -61,14 +61,22 @@ $(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs) $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ # Link the SMM stub module with a 0-byte heap. +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_64)) +endif $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ $(obj)/cpu/x86/smm/smmstub.ramstage.manual: $(obj)/cpu/x86/smm/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) +else + cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) +endif # C-based SMM handler. diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 9c282c3..295e5a8 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -109,7 +109,7 @@ static void smi_restore_pci_address(void) outl(pci_orig, 0xcf8); } -static inline void *smm_save_state(u32 base, int arch_offset, int node) +static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) { base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); return (void *)base;

1 0

New patch to review for coreboot: smm: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11089 -gerrit commit d56ff173218832732f63173d970703fb6f010ebf Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:28:44 2015 -0700 smm: 64bit fixes Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/x86/smm/Makefile.inc | 8 ++++++++ src/cpu/x86/smm/smihandler.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 239689e..2e61018 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -61,14 +61,22 @@ $(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs) $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ # Link the SMM stub module with a 0-byte heap. +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_64)) +endif $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ $(obj)/cpu/x86/smm/smmstub.ramstage.manual: $(obj)/cpu/x86/smm/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) +else + cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) +endif # C-based SMM handler. diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 9c282c3..295e5a8 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -109,7 +109,7 @@ static void smi_restore_pci_address(void) outl(pci_orig, 0xcf8); } -static inline void *smm_save_state(u32 base, int arch_offset, int node) +static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) { base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); return (void *)base;

1 0

New patch to review for coreboot: acpi: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11088 -gerrit commit 43be723db639f9f4e3e6c212e78dfc01605a0600 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:28:13 2015 -0700 acpi: 64bit fixes Change-Id: I5d0c95af7d35115b5ac4141489caceef4ee1c8bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/acpi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 134e437..2194c48 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1051,13 +1051,13 @@ void *acpi_find_wakeup_vector(void) return NULL; printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp); - rsdt = (acpi_rsdt_t *) rsdp->rsdt_address; + rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; end = (char *)rsdt + rsdt->header.length; printk(BIOS_DEBUG, "RSDT found at %p ends at %p\n", rsdt, end); for (i = 0; ((char *)&rsdt->entry[i]) < end; i++) { - fadt = (acpi_fadt_t *)rsdt->entry[i]; + fadt = (acpi_fadt_t *)(uintptr_t)rsdt->entry[i]; if (strncmp((char *)fadt, "FACP", 4) == 0) break; fadt = NULL; @@ -1067,7 +1067,7 @@ void *acpi_find_wakeup_vector(void) return NULL; printk(BIOS_DEBUG, "FADT found at %p\n", fadt); - facs = (acpi_facs_t *)fadt->firmware_ctrl; + facs = (acpi_facs_t *)(uintptr_t)fadt->firmware_ctrl; if (facs == NULL) { printk(BIOS_DEBUG, "No FACS found, wake up from S3 not " @@ -1076,7 +1076,7 @@ void *acpi_find_wakeup_vector(void) } printk(BIOS_DEBUG, "FACS found at %p\n", facs); - wake_vec = (void *)facs->firmware_waking_vector; + wake_vec = (void *)(uintptr_t)facs->firmware_waking_vector; printk(BIOS_DEBUG, "OS waking vector is %p\n", wake_vec); return wake_vec; @@ -1090,7 +1090,7 @@ extern int lowmem_backup_size; #define WAKEUP_BASE 0x600 -void (*acpi_do_wakeup)(u32 vector, u32 backup_source, u32 backup_target, +void (*acpi_do_wakeup)(uintptr_t vector, u32 backup_source, u32 backup_target, u32 backup_size) asmlinkage = (void *)WAKEUP_BASE; extern unsigned char __wakeup; @@ -1098,10 +1098,10 @@ extern unsigned int __wakeup_size; void acpi_jump_to_wakeup(void *vector) { - u32 acpi_backup_memory = 0; + uintptr_t acpi_backup_memory = 0; if (HIGH_MEMORY_SAVE && acpi_s3_resume_allowed()) { - acpi_backup_memory = (u32)cbmem_find(CBMEM_ID_RESUME); + acpi_backup_memory = (uintptr_t)cbmem_find(CBMEM_ID_RESUME); if (!acpi_backup_memory) { printk(BIOS_WARNING, "ACPI: Backup memory missing. " @@ -1124,7 +1124,7 @@ void acpi_jump_to_wakeup(void *vector) timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, + acpi_do_wakeup((uintptr_t)vector, acpi_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); } #endif

1 0

New patch to review for coreboot: cpu/amd: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11087 -gerrit commit 0833294d0e0344d4f50470857da5508a6a938c7c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:27:27 2015 -0700 cpu/amd: 64bit fixes Change-Id: I88d4b3df4c30ba6820fa7363b5582c087a871e8c Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/heapmanager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/heapmanager.c b/src/cpu/amd/agesa/heapmanager.c index eeff0a4..e6f1e5f 100644 --- a/src/cpu/amd/agesa/heapmanager.c +++ b/src/cpu/amd/agesa/heapmanager.c @@ -379,7 +379,7 @@ static AGESA_STATUS agesa_LocateBuffer(UINT32 Func, UINT32 Data, VOID *ConfigPtr } -AGESA_STATUS HeapManagerCallout(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS HeapManagerCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr) { if (Func == AGESA_LOCATE_BUFFER) return agesa_LocateBuffer(Func, Data, ConfigPtr);

1 0

New patch to review for coreboot: RD890: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11086 -gerrit commit c5373d8214f40c1e52c543d6e4b8f88577e010a1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:25:33 2015 -0700 RD890: 64bit fixes Change-Id: I326c070398c72a877054969d3a03e6e427edc304 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/northbridge/amd/cimx/rd890/late.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index bc51543..3bdce27 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -86,7 +86,8 @@ static void rd890_enable(device_t dev) /* CIMX configuration defualt initialize */ rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, + (uintptr_t)dev, (VOID*)NbConfigPtr); } /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree * After this call EP are fully operational on particular NB @@ -122,7 +123,7 @@ static void ioapic_init(struct device *dev) void *ioapic_base; pci_write_config32(dev, 0xF8, 0x1); - ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); clear_ioapic(ioapic_base); setup_ioapic(ioapic_base, 1); }

1 0

New patch to review for coreboot: SB700: 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11085 -gerrit commit 85540e19c751745d0a44e638471c4a06e9de54b7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:24:46 2015 -0700 SB700: 64bit fixes Change-Id: Ib4b643441a5b887abf73cc55930ea9b01037f6ea Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/amd/cimx/sb700/late.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index cd36fac..998710d 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -234,7 +234,7 @@ static void sb700_enable(device_t dev) case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { - u32 ioapic_base; + uintptr_t ioapic_base; printk(BIOS_DEBUG, "sm_init().\n"); ioapic_base = IO_APIC_ADDR; clear_ioapic((void *)ioapic_base);

1 0

New patch to review for coreboot: SB900 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11084 -gerrit commit f1914d26303a94e07dda8929e1b342a9fdca4685 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:24:23 2015 -0700 SB900 64bit fixes Change-Id: I5ea0f9338ccdd658b5fbec72aa35b4f80d63d4f9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/amd/cimx/sb900/cfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index ed35a5d..3640966 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = (typeof(sb_config->TempMMIO))NULL; // CIMx Internal Used + sb_config->TempMMIO = (UINTN)NULL; // CIMx Internal Used // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option

1 0

New patch to review for coreboot: More Hudson 64bit fixes
by Stefan Reinauer 31 Jul '15

31 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11083 -gerrit commit c473c5eae8ab145ce424b8e7a23cef0792a07872 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:23:50 2015 -0700 More Hudson 64bit fixes Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/amd/agesa/hudson/hudson.c | 8 ++++---- src/southbridge/amd/agesa/hudson/sata.c | 2 +- src/southbridge/amd/agesa/hudson/smi.h | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index cafd6c6..dd52b3a 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,22 +40,22 @@ void pm_write8(u8 reg, u8 value) { - write8((void *)(PM_MMIO_BASE + reg), value); + write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); } u8 pm_read8(u8 reg) { - return read8((void *)(PM_MMIO_BASE + reg)); + return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); } void pm_write16(u8 reg, u16 value) { - write16((void *)(PM_MMIO_BASE + reg), value); + write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); } u16 pm_read16(u16 reg) { - return read16((void *)(PM_MMIO_BASE + reg)); + return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); } #define PM_REG_USB_ENABLE 0xef diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index 00c2a07..c5dc196 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -41,7 +41,7 @@ static void sata_init(struct device *dev) #define CFG_CAP_SPM (1<<12) volatile u32 *ahci_ptr = - (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); + (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); u32 temp; /* unlock the write-protect */ diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 520c65f..652c886 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -36,22 +36,22 @@ enum smi_lvl { static inline uint32_t smi_read32(uint8_t offset) { - return read32((void *)(SMI_BASE + offset)); + return read32((void *)((uintptr_t)SMI_BASE + offset)); } static inline void smi_write32(uint8_t offset, uint32_t value) { - write32((void *)(SMI_BASE + offset), value); + write32((void *)((uintptr_t)SMI_BASE + offset), value); } static inline uint16_t smi_read16(uint8_t offset) { - return read16((void *)(SMI_BASE + offset)); + return read16((void *)((uintptr_t)SMI_BASE + offset)); } static inline void smi_write16(uint8_t offset, uint16_t value) { - write16((void *)(SMI_BASE + offset), value); + write16((void *)((uintptr_t)SMI_BASE + offset), value); } void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
105
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2015