coreboot-gerrit July 2015

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Patch set updated for coreboot: Port AGESA based northbridge code to 64bit
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11021 -gerrit commit c0c49bdceeeff6281477b52342331806c5d36686 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 21 12:48:17 2015 -0700 Port AGESA based northbridge code to 64bit This is extending http://review.coreboot.org/#/c/10583/ to the remaining AGESA northbridge drivers. Change-Id: I6fa53b36a1420e92cb4aecb0f7b4c71541a94c71 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/northbridge/amd/agesa/family12/northbridge.c | 8 +++++--- src/northbridge/amd/agesa/family15/northbridge.c | 6 ++++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 6 ++++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 6 ++++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 6 ++++-- 5 files changed, 21 insertions(+), 11 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f1305b9..b9156cb 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -531,7 +531,7 @@ static void domain_read_resources(device_t dev) static void domain_set_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); + printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev); unsigned long mmio_basek; u32 pci_tolm; @@ -723,11 +723,13 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d0e05fb..ede11f0 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -493,11 +493,13 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 62486b8..b7218d5 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -468,11 +468,13 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index b043ccc..dee2616 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -468,11 +468,13 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 275ed3d..0d2cdec 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -468,11 +468,13 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 0, + addr + 2, *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, current, 1, + addr + 2, *(UINT16 *)addr - 2); return (unsigned long)current; }

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Patch set updated for coreboot: f10/f12: Remove whitespace from gcccar.inc
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11024 -gerrit commit f877d161b7fe92eb015c76a6baea5e4b27f76ccb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 21 14:04:27 2015 -0700 f10/f12: Remove whitespace from gcccar.inc :'<,'>s,\ *$,, Change-Id: I9fca0e12f02d6fff4644abacecd4a31cea64bbc1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f10/gcccar.inc | 246 +++++++++++++++--------------- src/vendorcode/amd/agesa/f12/gcccar.inc | 258 ++++++++++++++++---------------- 2 files changed, 252 insertions(+), 252 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index b0f4ee6..94d0ccc 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -37,99 +37,99 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized @@ -144,28 +144,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -180,12 +180,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -206,7 +206,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -238,7 +238,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B @@ -249,7 +249,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -277,7 +277,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -310,7 +310,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -333,7 +333,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -357,7 +357,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -419,7 +419,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -581,7 +581,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -885,7 +885,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -1127,7 +1127,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1232,7 +1232,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1300,7 +1300,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1336,20 +1336,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1420,7 +1420,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1576,7 +1576,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 147d16e..b633525 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1,7 +1,7 @@ /* * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + /****************************************************************************** * AMD Generic Encapsulated Software Architecture * @@ -37,99 +37,99 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 0 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized @@ -144,28 +144,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -180,12 +180,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -206,7 +206,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -238,7 +238,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B @@ -249,7 +249,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -277,7 +277,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -310,7 +310,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -333,7 +333,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -357,7 +357,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -413,7 +413,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -575,7 +575,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -879,7 +879,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -1121,7 +1121,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1226,7 +1226,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1294,7 +1294,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1330,20 +1330,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1414,7 +1414,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1570,7 +1570,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address

1 0

Patch set updated for coreboot: f14: Increase AP stack to 8k on 64bit
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11025 -gerrit commit 57bdfde3fabe625605e4c70d62dfcaee4aa67914 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 21 14:37:13 2015 -0700 f14: Increase AP stack to 8k on 64bit This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 2104c27..8f395ce 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ +CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ +#else CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

1 0

Patch set updated for coreboot: break lots of boards
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10594 -gerrit commit 8c957db1cd745ea304ff8ea49326c178375b02d5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:05:13 2015 -0700 break lots of boards Enable 64bit compilation for AGESA boards :-) Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 282e1ed..45e1d63 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

1 0

Patch merged into coreboot/master: Intel Skylake: Whitespace fixes in ACPI
by gerrit＠coreboot.org 30 Jul '15

30 Jul '15

the following patch was just integrated into master: commit 480c07425c25bb1a708dbe61bbb27325c8a18473 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 00:06:15 2015 -0700 Intel Skylake: Whitespace fixes in ACPI Change-Id: If6df9ad35626669be8f7a2bf1fdf564663ba48c8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11077 for details. -gerrit

1 0

Patch set updated for coreboot: cpu/amd: Fix cbtypes.h to match UINTN convention
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10601 -gerrit commit 10b45fb72f258355e4dab69ca8473338fe8d28dc Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 29 23:54:38 2015 -0700 cpu/amd: Fix cbtypes.h to match UINTN convention There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/include/cpu/amd/common/cbtypes.h | 22 +++++++++++++--------- src/mainboard/amd/dinar/rd890_cfg.c | 2 +- src/mainboard/amd/dinar/sb700_cfg.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 2 +- src/mainboard/supermicro/h8scm/rd890_cfg.c | 2 +- src/mainboard/tyan/s8226/rd890_cfg.c | 2 +- src/northbridge/amd/cimx/rd890/amd.h | 2 +- src/vendorcode/amd/agesa/common/Porting.h | 24 ++++++++++++++---------- src/vendorcode/amd/cimx/sb700/SBTYPE.h | 2 +- src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 4 +++- src/vendorcode/amd/cimx/sb900/AmdSbLib.h | 4 ++-- src/vendorcode/amd/cimx/sb900/SbDef.h | 2 +- src/vendorcode/amd/cimx/sb900/SbMain.c | 2 +- src/vendorcode/amd/cimx/sb900/SbSubFun.h | 5 +++-- 14 files changed, 44 insertions(+), 33 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index 346f1a3..54da783 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -20,16 +20,20 @@ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ -typedef signed long long __int64; +/* Map coreboot stdint types to AGESA types. */ + +#include <stdint.h> + +typedef int64_t __int64; typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; +typedef uintptr_t UINTN; +typedef char CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef int32_t INT32; +typedef uint64_t UINT64; +typedef uint8_t BOOLEAN; #define DMSG_SB_TRACE 0x02 #define TRACE(Arguments) diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index c90f9f0..13f18ec 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 53e93ce..2ce47ce 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -135,7 +135,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) #ifndef __PRE_RAM__ /* ramstage cimx config here */ if (!sb_config->StdHeader.pCallBack) { - sb_config->StdHeader.pCallBack = sb700_callout_entry; + sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } //sb_config-> diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.c +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index 5e69ac4..ade5a31 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -41,7 +41,7 @@ #define OUT #define IMAGE_SIGNATURE 'DMA$' -typedef UINTN AGESA_STATUS; +typedef UINT32 AGESA_STATUS; #define AGESA_SUCCESS ((AGESA_STATUS) 0x0) diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h index fc65cfc..44257e3 100644 --- a/src/vendorcode/amd/agesa/common/Porting.h +++ b/src/vendorcode/amd/agesa/common/Porting.h @@ -216,6 +216,7 @@ #elif defined __GNUC__ + #include <stdint.h> #define IN #define OUT #define STATIC static @@ -228,17 +229,20 @@ #define CALLCONV #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + // Create the universal 32, 16, and 8-bit data types typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; + typedef uintptr_t UINTN; + typedef int64_t INT64; + typedef uint64_t UINT64; + typedef int32_t INT32; + typedef uint32_t UINT32; + typedef int16_t INT16; + typedef uint16_t UINT16; + typedef int8_t INT8; + typedef uint8_t UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; typedef void VOID; //typedef unsigned long size_t; diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h index faeae5d..3dc571f 100644 --- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -32,7 +32,7 @@ #pragma pack(push,1) -typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig); typedef void (*SMM_SERVICE_ROUTINE) (void); typedef struct _STDCFG{ diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h index 9e50bf9..a50cda4 100644 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h +++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h @@ -46,6 +46,8 @@ #ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ #define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ +#include <cpu/amd/common/cbtypes.h> + //AMDSBLIB Routines /** @@ -105,7 +107,7 @@ AGESA_STATUS AmdSbDispatcher (IN void *pConfig); * @param[in] Length - Data length * */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /* SB800 CIMx and AGESA V5 can share lib functions */ diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h index cf9589b..47a7048 100644 --- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h +++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h @@ -69,10 +69,10 @@ unsigned char getEfuseByte (IN unsigned char Index); AGESA_STATUS AmdSbDispatcher (IN void *pConfig); /**< AmdSbCopyMem - Reserved */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /**< GetRomSigPtr - Reserved */ -void* GetRomSigPtr (IN unsigned int* RomSigPtr); +void* GetRomSigPtr (IN UINTN * RomSigPtr); /**< RWXhciIndReg - Reserved */ void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask); diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h index 91fec4a..b600627 100644 --- a/src/vendorcode/amd/cimx/sb900/SbDef.h +++ b/src/vendorcode/amd/cimx/sb900/SbDef.h @@ -71,7 +71,7 @@ void MemoryCopy ( IN unsigned char *Dest, IN unsigned char *Source, - IN unsigned int Size + IN unsigned long Size ); //AMD Library Routines (PCILIB.C) diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c index 958e44b..7c9dbbd 100644 --- a/src/vendorcode/amd/cimx/sb900/SbMain.c +++ b/src/vendorcode/amd/cimx/sb900/SbMain.c @@ -278,7 +278,7 @@ sbSmmAcpiOn ( UINTN CallBackToOEM ( IN UINT32 Func, - IN UINT32 Data, + IN UINTN Data, IN AMDSBCFG* pConfig ) { diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h index 447f5c9..68574a7 100644 --- a/src/vendorcode/amd/cimx/sb900/SbSubFun.h +++ b/src/vendorcode/amd/cimx/sb900/SbSubFun.h @@ -40,6 +40,7 @@ ; ;*********************************************************************************/ +#include <cpu/amd/common/cbtypes.h> // Southbridge SBMAIN Routines /** @@ -127,7 +128,7 @@ void sbSmmAcpiOn (IN AMDSBCFG* pConfig); * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig); +UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig); // Southbridge SBPOR Routines @@ -605,4 +606,4 @@ void TurnOffCG2 (OUT void); */ void BackUpCG2 (OUT void); -void XhciA12Fix (OUT void); \ No newline at end of file +void XhciA12Fix (OUT void);

1 0

Patch set updated for coreboot: Intel Skylake: Whitespace fixes in ACPI
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11077 -gerrit commit 480c07425c25bb1a708dbe61bbb27325c8a18473 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 00:06:15 2015 -0700 Intel Skylake: Whitespace fixes in ACPI Change-Id: If6df9ad35626669be8f7a2bf1fdf564663ba48c8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/skylake/acpi/cpu.asl | 2 +- src/soc/intel/skylake/acpi/serialio.asl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl index 5856033..62127ef 100644 --- a/src/soc/intel/skylake/acpi/cpu.asl +++ b/src/soc/intel/skylake/acpi/cpu.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index 203dbef..62b83e0 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -43,7 +43,7 @@ Method (LPD0, 2, Serialized) And (SPCS, 0xFFFFFFFC, SPCS) /* Read back after writing */ - Store (SPCS, Local0) + Store (SPCS, Local0) } /* Put SerialIO device in D3 state */ @@ -688,7 +688,7 @@ Device (PEMC) Method (_RMV, 0x0, NotSerialized) { Return (0) - } + } } }

1 0

New patch to review for coreboot: Intel Skylake: Whitespace fixes in ACPI
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11077 -gerrit commit bef0393db37028d0ad8766ad8735219225142b05 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 00:06:15 2015 -0700 Intel Skylake: Whitespace fixes in ACPI Change-Id: If6df9ad35626669be8f7a2bf1fdf564663ba48c8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/intel/skylake/acpi/cpu.asl | 2 +- src/soc/intel/skylake/acpi/serialio.asl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/acpi/cpu.asl b/src/soc/intel/skylake/acpi/cpu.asl index 5856033..62127ef 100644 --- a/src/soc/intel/skylake/acpi/cpu.asl +++ b/src/soc/intel/skylake/acpi/cpu.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index 203dbef..62b83e0 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -43,7 +43,7 @@ Method (LPD0, 2, Serialized) And (SPCS, 0xFFFFFFFC, SPCS) /* Read back after writing */ - Store (SPCS, Local0) + Store (SPCS, Local0) } /* Put SerialIO device in D3 state */ @@ -688,7 +688,7 @@ Device (PEMC) Method (_RMV, 0x0, NotSerialized) { Return (0) - } + } } }

1 0

Patch set updated for coreboot: cpu/amd: Fix cbtypes.h to match UINTN convention
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10601 -gerrit commit f524b45fc3cd0e1135238bfb5bf6201746a96e15 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jun 19 16:42:58 2015 -0700 cpu/amd: Fix cbtypes.h to match UINTN convention UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/include/cpu/amd/common/cbtypes.h | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index 346f1a3..6a47e00 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -20,16 +20,20 @@ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ -typedef signed long long __int64; +/* Map coreboot stdint types to AGESA types. */ + +#include <stdint.h> + +typedef int64_t __int64; typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; +typedef uintptr_t UINTN; +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef int32_t INT32; +typedef uint64_t UINT64; +typedef uint8_t BOOLEAN; #define DMSG_SB_TRACE 0x02 #define TRACE(Arguments)

1 0

Patch set updated for coreboot: Straighten up AMDs API
by Stefan Reinauer 30 Jul '15

30 Jul '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11076 -gerrit commit 3aea1797133db80571beba3fd7b8a5f94d4b4c25 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 29 23:54:38 2015 -0700 Straighten up AMDs API There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. Change-Id: Idebf36c45367ec4dcd21cbe53a6c534857ab5dd7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/amd/dinar/rd890_cfg.c | 2 +- src/mainboard/amd/dinar/sb700_cfg.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 2 +- src/mainboard/supermicro/h8scm/rd890_cfg.c | 2 +- src/mainboard/tyan/s8226/rd890_cfg.c | 2 +- src/northbridge/amd/cimx/rd890/amd.h | 2 +- src/vendorcode/amd/agesa/common/Porting.h | 24 ++++++++++++++---------- src/vendorcode/amd/cimx/sb700/SBTYPE.h | 2 +- src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 4 +++- src/vendorcode/amd/cimx/sb900/AmdSbLib.h | 4 ++-- src/vendorcode/amd/cimx/sb900/SbDef.h | 2 +- src/vendorcode/amd/cimx/sb900/SbMain.c | 2 +- src/vendorcode/amd/cimx/sb900/SbSubFun.h | 5 +++-- 13 files changed, 31 insertions(+), 24 deletions(-) diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index c90f9f0..13f18ec 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 53e93ce..2ce47ce 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -135,7 +135,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) #ifndef __PRE_RAM__ /* ramstage cimx config here */ if (!sb_config->StdHeader.pCallBack) { - sb_config->StdHeader.pCallBack = sb700_callout_entry; + sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } //sb_config-> diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.c +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index 5e69ac4..ade5a31 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -41,7 +41,7 @@ #define OUT #define IMAGE_SIGNATURE 'DMA$' -typedef UINTN AGESA_STATUS; +typedef UINT32 AGESA_STATUS; #define AGESA_SUCCESS ((AGESA_STATUS) 0x0) diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h index fc65cfc..44257e3 100644 --- a/src/vendorcode/amd/agesa/common/Porting.h +++ b/src/vendorcode/amd/agesa/common/Porting.h @@ -216,6 +216,7 @@ #elif defined __GNUC__ + #include <stdint.h> #define IN #define OUT #define STATIC static @@ -228,17 +229,20 @@ #define CALLCONV #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + // Create the universal 32, 16, and 8-bit data types typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; + typedef uintptr_t UINTN; + typedef int64_t INT64; + typedef uint64_t UINT64; + typedef int32_t INT32; + typedef uint32_t UINT32; + typedef int16_t INT16; + typedef uint16_t UINT16; + typedef int8_t INT8; + typedef uint8_t UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; typedef void VOID; //typedef unsigned long size_t; diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h index faeae5d..3dc571f 100644 --- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -32,7 +32,7 @@ #pragma pack(push,1) -typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig); typedef void (*SMM_SERVICE_ROUTINE) (void); typedef struct _STDCFG{ diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h index 9e50bf9..a50cda4 100644 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h +++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h @@ -46,6 +46,8 @@ #ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ #define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ +#include <cpu/amd/common/cbtypes.h> + //AMDSBLIB Routines /** @@ -105,7 +107,7 @@ AGESA_STATUS AmdSbDispatcher (IN void *pConfig); * @param[in] Length - Data length * */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /* SB800 CIMx and AGESA V5 can share lib functions */ diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h index cf9589b..47a7048 100644 --- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h +++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h @@ -69,10 +69,10 @@ unsigned char getEfuseByte (IN unsigned char Index); AGESA_STATUS AmdSbDispatcher (IN void *pConfig); /**< AmdSbCopyMem - Reserved */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /**< GetRomSigPtr - Reserved */ -void* GetRomSigPtr (IN unsigned int* RomSigPtr); +void* GetRomSigPtr (IN UINTN * RomSigPtr); /**< RWXhciIndReg - Reserved */ void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask); diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h index 91fec4a..b600627 100644 --- a/src/vendorcode/amd/cimx/sb900/SbDef.h +++ b/src/vendorcode/amd/cimx/sb900/SbDef.h @@ -71,7 +71,7 @@ void MemoryCopy ( IN unsigned char *Dest, IN unsigned char *Source, - IN unsigned int Size + IN unsigned long Size ); //AMD Library Routines (PCILIB.C) diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c index 958e44b..7c9dbbd 100644 --- a/src/vendorcode/amd/cimx/sb900/SbMain.c +++ b/src/vendorcode/amd/cimx/sb900/SbMain.c @@ -278,7 +278,7 @@ sbSmmAcpiOn ( UINTN CallBackToOEM ( IN UINT32 Func, - IN UINT32 Data, + IN UINTN Data, IN AMDSBCFG* pConfig ) { diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h index 447f5c9..68574a7 100644 --- a/src/vendorcode/amd/cimx/sb900/SbSubFun.h +++ b/src/vendorcode/amd/cimx/sb900/SbSubFun.h @@ -40,6 +40,7 @@ ; ;*********************************************************************************/ +#include <cpu/amd/common/cbtypes.h> // Southbridge SBMAIN Routines /** @@ -127,7 +128,7 @@ void sbSmmAcpiOn (IN AMDSBCFG* pConfig); * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig); +UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig); // Southbridge SBPOR Routines @@ -605,4 +606,4 @@ void TurnOffCG2 (OUT void); */ void BackUpCG2 (OUT void); -void XhciA12Fix (OUT void); \ No newline at end of file +void XhciA12Fix (OUT void);

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coreboot-gerrit July 2015