coreboot-gerrit July 2015

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Patch set updated for coreboot: Add SoC specific microcode update check in ramstage
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11055 -gerrit commit 67d9f27db19b1fc88d17181193617eb0e0623103 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:31:51 2015 +0530 Add SoC specific microcode update check in ramstage Some Intel SoCs which support SGX feature, report the microcode patch revision one less than the actual revision. This results in the same microcode patch getting loaded again. Add a SoC specific check to avoid reloading the same patch. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:286054 Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287513 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++ src/include/cpu/intel/microcode.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 3492bfd..8791a2e 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,6 +28,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> +#include <rules.h> #if !defined(__PRE_RAM__) #include <cbfs.h> @@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) if (current_rev == m->rev) return; +#if ENV_RAMSTAGE + /*SoC specific check to update microcode*/ + if (soc_skip_ucode_update(current_rev, m->rev)) { + printk(BIOS_DEBUG, "Skip microcode update\n"); + return; + } +#endif + msr.lo = (unsigned long)m + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); @@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void) spin_unlock(&microcode_lock); #endif } + +#if ENV_RAMSTAGE +__attribute__((weak)) int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id) +{ + return 0; +} +#endif diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index d2fa1b7..73b1c42 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -29,6 +29,10 @@ const void *intel_microcode_find(void); * well as ensuring the microcode matches the family and revision (i.e. with * intel_microcode_find()). */ void intel_microcode_load_unlocked(const void *microcode_patch); + +/* SoC specific check to determine if microcode update is really + * required, will skip microcode update if true. */ +int soc_skip_ucode_update(u32 currrent_patch_id, u32 new_patch_id); #endif #endif

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Patch set updated for coreboot: skylake: Update microcode reload in ramstage.
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11056 -gerrit commit 98a1d8c458991b177e7d4eff71feff287a030eab Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 22:40:53 2015 +0530 skylake: Update microcode reload in ramstage. For Skylake, Microcode is being loaded from FIT, Skylake supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootclock and ramstage (MP init). Avoid the microcode reload by checking for PRMRR support. BUG=chrome-os-partner:42046 BRANCH=None TEST=Built for glados and tested on RVP3 CQ-DEPEND=CL:287513 Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/287674 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index cd88c10..980a05a 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -574,3 +574,16 @@ void soc_init_cpus(device_t dev) if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) restore_default_smm_area(smm_save_area); } + +int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) +{ + msr_t msr; + /* If PRMRR/SGX is supported the FIT microcode load will set the msr + * 0x08b with the Patch revision id one less than the id in the + * microcode binary. The PRMRR support is indicated in the MSR + * MTRRCAP[12]. Check for this feature and avoid reloading the + * same microcode during cpu initialization. + */ + msr = rdmsr(MTRRcap_MSR); + return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); +}

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Patch merged into coreboot/master: skylake: clean-up pei_data
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit b759ede57940aef94f648def5ada163ec6fa166d Author: robbie zhang <robbie.zhang(a)intel.com> Date: Mon Jul 27 14:40:23 2015 -0700 skylake: clean-up pei_data Remove the items that are obviously broadwell left or become no-need with fsp. BUG=chrome-os-partner:43186 BRANCH=None TEST=build and boot on sklrvp3. Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010 Original-Reviewed-on: https://chromium-review.googlesource.com/288833 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang(a)intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang(a)intel.com> Reviewed-on: http://review.coreboot.org/11072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11072 for details. -gerrit

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Patch merged into coreboot/master: skylake: align power management names with hardware
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 7f78849fc70879737260739034af4b2a99513e4d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 24 17:10:31 2015 -0500 skylake: align power management names with hardware Some of the field and register names in the power management code were not reflecting current chipset documentation. While in there fix 0-sized array in the power_state structure. Lastly, log the entire STD GPE register for visibility in elog. It reports as an extension of other GPIO wake events. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288296 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11070 for details. -gerrit

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Patch merged into coreboot/master: skylake: provide pcr helper to get a port's register space
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 8dfa660a68be3e5268c78f2a6e6643795beed76f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 23 20:48:06 2015 -0500 skylake: provide pcr helper to get a port's register space In order to aid users of the PCR register space provide pcr_port_regs(). BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0 Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288193 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11068 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11068 for details. -gerrit

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Patch merged into coreboot/master: skylake: prefix the gpio functions with 'gpio_'
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit 4f5efb6c21a9e909384a970bad410d11bdbda7a5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 22 20:57:05 2015 -0500 skylake: prefix the gpio functions with 'gpio_' In order to provide more clarity on what some of the gpio functions are doing add a 'gpio_' prefix to the globally visible functions. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288192 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11067 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11067 for details. -gerrit

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Patch merged into coreboot/master: skylake: remove unused types and definitions in gpio.h
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit ed575681d1706783cc5cf75407490bc6d81a98d1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 22 20:42:51 2015 -0500 skylake: remove unused types and definitions in gpio.h These types and definitions were carried over from a previous platform. However, they are not used. Remove them. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built on glados Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c Original-Signed-off-by: Aaron Durbin <adurbin(a)chormium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288191 Original-Trybot-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11066 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11066 for details. -gerrit

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Patch merged into coreboot/master: t210: lp0_resume: implement MBIST workaround
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit dec2751847a0385bbcbdb14c929b91605e7dc2db Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 21 11:52:12 2015 -0700 t210: lp0_resume: implement MBIST workaround As in cold boot path, implement MBIST workaround in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: I997009ecb0f52fb5a47c62b8daea33e472ec2664 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 4b1f80ea4c1d3782eb9f2c90c2a8d7b2e97ba050 Original-Change-Id: Ib4944401e1df02bf0aab1e78db7e14ef56c7f829 Original-Reviewed-on: https://chromium-review.googlesource.com/287287 Original-Tested-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Yen Lin <yelin(a)nvidia.com> Reviewed-on: http://review.coreboot.org/11071 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11071 for details. -gerrit

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Patch merged into coreboot/master: veyron_rialto: Select PHYSICAL_REC_SWITCH
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit dd7e59892d3125e891271039f931d03c6036ab09 Author: Jonathan Dixon <joth(a)google.com> Date: Wed Jul 22 16:08:34 2015 -0700 veyron_rialto: Select PHYSICAL_REC_SWITCH Copied from Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 BUG=chrome-os-partner:43022 BRANCH=None TEST=Used physical recovery button to enter dev mode on rialto Change-Id: I39fd13fee3b9f272f3dc08a447091e05a3d74741 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: eed0652f84cba963044908bb91aac7b8c1c81fd4 Original-Signed-off-by: Jonathan Dixon <joth(a)chromium.org> Original-Change-Id: I388d8bb0faa93b54540be095e68450192592a093 Original-Reviewed-on: https://chromium-review.googlesource.com/287660 Original-Reviewed-by: Jason Simmons <jsimmons(a)chromium.org> Reviewed-on: http://review.coreboot.org/11069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11069 for details. -gerrit

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Patch merged into coreboot/master: veyron: update mickey sdram-lpddr3-samsung-2GB.inc
by gerrit＠coreboot.org 29 Jul '15

29 Jul '15

the following patch was just integrated into master: commit d4c9346c3f8900b4b534f62bb0c02f727df22e07 Author: jinkun.hong <jinkun.hong(a)rock-chips.com> Date: Thu Jul 23 11:51:51 2015 +0800 veyron: update mickey sdram-lpddr3-samsung-2GB.inc Modify MR3_I/O Configuration, Change 34.3 ohms to 60 ohms. This resolves an issue that was observed on some Mickey boards with the Samsung 2GB LPDDR3 and is believed to be caused by inferior routing on the small PCB. (Elpida 2GB LPDDR3 seems unaffected.) BUG=chrome-os-partner:41905 TEST=Boot from mickey BRANCH=None Change-Id: Ic20d9eceb00658c214fd032a2f213dbe0d51a91b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1305010aee6818910ad1dec26d9d948505ca281e Original-Change-Id: I5517e07fc5716ed4cd58e5502f13ccd61ffb5357 Original-Signed-off-by: jinkun.hong <jinkun.hong(a)rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286333 Reviewed-on: http://review.coreboot.org/11051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11051 for details. -gerrit

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coreboot-gerrit July 2015