coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: t210: lp0_resume: implement MBIST workaround
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11071 -gerrit commit 406563d85bd29960c34b9fe99344398aec660d0f Author: Yen Lin <yelin(a)nvidia.com> Date: Tue Jul 21 11:52:12 2015 -0700 t210: lp0_resume: implement MBIST workaround As in cold boot path, implement MBIST workaround in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: I997009ecb0f52fb5a47c62b8daea33e472ec2664 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 4b1f80ea4c1d3782eb9f2c90c2a8d7b2e97ba050 Original-Change-Id: Ib4944401e1df02bf0aab1e78db7e14ef56c7f829 Original-Reviewed-on: https://chromium-review.googlesource.com/287287 Original-Tested-by: Yen Lin <yelin(a)nvidia.com> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Yen Lin <yelin(a)nvidia.com> --- src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index fdd25dd..5ef03d0 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -194,6 +194,12 @@ enum { CLK_M_DIVISOR_BY_2 = 0x1 << 2 }; +static uint32_t *clk_rst_lvl2_clk_gate_ovra_ptr = (void *)(CLK_RST_BASE + 0xf8); +static uint32_t *clk_rst_lvl2_clk_gate_ovrb_ptr = (void *)(CLK_RST_BASE + 0xfc); +static uint32_t *clk_rst_lvl2_clk_gate_ovrc_ptr = (void *)(CLK_RST_BASE + 0x3a0); +static uint32_t *clk_rst_lvl2_clk_gate_ovrd_ptr = (void *)(CLK_RST_BASE + 0x3a4); +static uint32_t *clk_rst_lvl2_clk_gate_ovre_ptr = (void *)(CLK_RST_BASE + 0x554); + static uint32_t *clk_rst_clk_out_enb_l_ptr = (void *)(CLK_RST_BASE + 0x10); static uint32_t *clk_rst_clk_out_enb_h_ptr = (void *)(CLK_RST_BASE + 0x14); static uint32_t *clk_rst_clk_out_enb_u_ptr = (void *)(CLK_RST_BASE + 0x18); @@ -210,6 +216,14 @@ static uint32_t *clk_rst_clk_enb_w_clr_ptr = (void *)(CLK_RST_BASE + 0x44c); static uint32_t *clk_rst_clk_enb_x_clr_ptr = (void *)(CLK_RST_BASE + 0x288); static uint32_t *clk_rst_clk_enb_y_clr_ptr = (void *)(CLK_RST_BASE + 0x2a0); +#define MBIST_CLK_ENB_L_0 0x80000130 +#define MBIST_CLK_ENB_H_0 0x020000C1 +#define MBIST_CLK_ENB_U_0 0x01F00200 +#define MBIST_CLK_ENB_V_0 0x80400008 +#define MBIST_CLK_ENB_W_0 0x002000FC +#define MBIST_CLK_ENB_X_0 0x23004780 +#define MBIST_CLK_ENB_Y_0 0x00000300 + static uint32_t *clk_rst_clk_enb_v_ptr = (void *)(CLK_RST_BASE + 0x440); enum { CLK_ENB_MSELECT = 0x1 << 3 @@ -368,6 +382,11 @@ enum { TRAINING_E_WRPTR = 0x1 << 3 }; +static uint32_t *fbio_cfg7_ptr = (void *)(EMC_BASE + 0x584); +enum { + CH1_ENABLE = 0x1 << 2 +}; + /* I2C5 registers */ static uint32_t *i2c5_cnfg_ptr = (void *)(I2C5_BASE + 0x0); enum { @@ -685,6 +704,49 @@ static void set_pmacro_training_wrptr(void) write32(pmacro_cfg_pm_global, ENABLE_CFG_BYTES); } +static void mbist_workaround(void) +{ + uint32_t clks_to_be_cleared; + + write32(clk_rst_lvl2_clk_gate_ovra_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovrb_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovrc_ptr, 0); + write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ + write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0; + write32(clk_rst_clk_enb_l_clr_ptr, clks_to_be_cleared); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_h_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_H_0; + write32(clk_rst_clk_enb_h_clr_ptr, clks_to_be_cleared); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_u_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_U_0; + write32(clk_rst_clk_enb_u_clr_ptr, clks_to_be_cleared); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_v_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_V_0; + write32(clk_rst_clk_enb_v_clr_ptr, clks_to_be_cleared); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_w_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_W_0; + write32(clk_rst_clk_enb_w_clr_ptr, clks_to_be_cleared); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_x_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_X_0; + write32(clk_rst_clk_enb_x_clr_ptr, clks_to_be_cleared); + + clks_to_be_cleared = read32(clk_rst_clk_out_enb_y_ptr); + clks_to_be_cleared &= ~MBIST_CLK_ENB_Y_0; + write32(clk_rst_clk_enb_y_clr_ptr, clks_to_be_cleared); + + if (read32(fbio_cfg7_ptr) & CH1_ENABLE) + /* if Dual Channel enable MC1 clock */ + write32(clk_rst_clk_enb_w_set_ptr, CLK_ENB_MC1); +} + static void config_mselect(void) { /* Set MSELECT clock source to PLL_P with 1:4 divider */ @@ -767,6 +829,9 @@ void lp0_resume(void) /* Bad qpop value on cmd pad macros removes clock gating from IB path */ set_pmacro_training_wrptr(); + /* Restore CAR CE's, SLCG overrides */ + mbist_workaround(); + /* * Find out which CPU (slow or fast) to wake up. The default setting * in flow controller is to wake up GCPU

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New patch to review for coreboot: skylake: align power management names with hardware
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11070 -gerrit commit 0994f823237a587c34a9fd783e73622c4207a4ae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 24 17:10:31 2015 -0500 skylake: align power management names with hardware Some of the field and register names in the power management code were not reflecting current chipset documentation. While in there fix 0-sized array in the power_state structure. Lastly, log the entire STD GPE register for visibility in elog. It reports as an extension of other GPIO wake events. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288296 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/elog.c | 8 +++----- src/soc/intel/skylake/include/soc/pm.h | 12 ++++++++---- src/soc/intel/skylake/pmutil.c | 8 +++++--- 3 files changed, 16 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 3ae0890..45f7b71 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -64,14 +64,12 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); - /* GPIO27 */ - if (ps->gpe0_sts[GPE_STD] & GP27_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); - /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); - pch_log_gpio_gpe(ps->gpe0_sts[GPE_94_64], ps->gpe0_en[GPE_94_64], 64); + pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64); + /* Treat the STD as an extension of GPIO to obtain visibility. */ + pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96); } static void pch_log_power_and_resets(struct chipset_power_state *ps) diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 6b75641..0475e20 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -86,10 +86,12 @@ #define GPE0_STS(x) (0x80 + (x * 4)) #define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */ #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */ -#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */ +#define GPE_95_64 2 /* 0x88/0x98 = GPE[95:64] */ #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ #define WADT_STS (1 << 18) -#define GP27_STS (1 << 16) +#define LAN_WAK_STS (1 << 16) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) #define PME_B0_STS (1 << 13) #define ME_SCI_STS (1 << 12) #define PME_STS (1 << 11) @@ -101,7 +103,9 @@ #define HOT_PLUG_STS (1 << 1) #define GPE0_EN(x) (0x90 + (x * 4)) #define WADT_EN (1 << 18) -#define GP27_EN (1 << 16) +#define LAN_WAK_EN (1 << 16) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) #define PME_B0_EN (1 << 13) #define ME_SCI_EN (1 << 12) #define PME_EN (1 << 11) @@ -129,7 +133,7 @@ struct chipset_power_state { uint32_t gpe0_en[4]; uint32_t gen_pmcon_a; uint32_t gen_pmcon_b; - uint32_t gblrst_cause[0]; + uint32_t gblrst_cause[2]; uint32_t prev_sleep_state; } __attribute__ ((packed)); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 85dc1b3..e5d4a2e 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -396,13 +396,15 @@ u32 clear_gpe_status(void) [11] = "PME", [12] = "ME", [13] = "PME_B0", - [16] = "GPIO27", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", [18] = "WADT" }; print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0); print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32); - print_gpe_gpio(reset_gpe(GPE0_STS(GPE_94_64), GPE0_EN(GPE_94_64)), 64); + print_gpe_gpio(reset_gpe(GPE0_STS(GPE_95_64), GPE0_EN(GPE_95_64)), 64); return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)), gpe0_sts_3_bits); } @@ -412,7 +414,7 @@ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); - outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); + outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_95_64)); outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); }

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New patch to review for coreboot: veyron_rialto: Select PHYSICAL_REC_SWITCH
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11069 -gerrit commit 830fb0af9c799fee11d16a3e8b0819091ef31196 Author: Jonathan Dixon <joth(a)google.com> Date: Wed Jul 22 16:08:34 2015 -0700 veyron_rialto: Select PHYSICAL_REC_SWITCH Copied from Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769 BUG=chrome-os-partner:43022 BRANCH=None TEST=Used physical recovery button to enter dev mode on rialto Change-Id: I39fd13fee3b9f272f3dc08a447091e05a3d74741 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: eed0652f84cba963044908bb91aac7b8c1c81fd4 Original-Signed-off-by: Jonathan Dixon <joth(a)chromium.org> Original-Change-Id: I388d8bb0faa93b54540be095e68450192592a093 Original-Reviewed-on: https://chromium-review.googlesource.com/287660 Original-Reviewed-by: Jason Simmons <jsimmons(a)chromium.org> --- src/mainboard/google/veyron_rialto/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 42ecb97..0061bfa 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select PHYSICAL_REC_SWITCH select RAM_CODE_SUPPORT select SOC_ROCKCHIP_RK3288 select SPI_FLASH

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New patch to review for coreboot: skylake: provide pcr helper to get a port's register space
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11068 -gerrit commit a6d75bb195b34253c610266926293f8c9e5b15cd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 23 20:48:06 2015 -0500 skylake: provide pcr helper to get a port's register space In order to aid users of the PCR register space provide pcr_port_regs(). BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0 Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288193 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/include/soc/pcr.h | 5 +++++ src/soc/intel/skylake/pcr.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/skylake/include/soc/pcr.h b/src/soc/intel/skylake/include/soc/pcr.h index 3f8ee2f..c8a4425 100644 --- a/src/soc/intel/skylake/include/soc/pcr.h +++ b/src/soc/intel/skylake/include/soc/pcr.h @@ -85,6 +85,8 @@ #define PID_DMI 0xEF #if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include <stdint.h> + /* All these return 0 on success and < 0 on errror. */ int pcr_read32(u8 pid, u16 offset, u32 *outdata); int pcr_read16(u8 pid, u16 offset, u16 *outdata); @@ -95,6 +97,9 @@ int pcr_write8(u8 pid, u16 offset, u8 indata); int pcr_andthenor32(u8 pid, u16 offset, u32 anddata, u32 ordata); int pcr_andthenor16(u8 pid, u16 offset, u16 anddata, u16 ordata); int pcr_andthenor8(u8 pid, u16 offset, u8 anddata, u8 ordata); + +/* Get the starting address of the port's registers. */ +uint8_t *pcr_port_regs(u8 pid); #endif /* if !defined(__ASSEMBLER__) && !defined(__ACPI__) */ #endif /* _SOC_PCR_H_ */ diff --git a/src/soc/intel/skylake/pcr.c b/src/soc/intel/skylake/pcr.c index 0e97265..7efbb25 100644 --- a/src/soc/intel/skylake/pcr.c +++ b/src/soc/intel/skylake/pcr.c @@ -34,6 +34,11 @@ static inline void *pcr_reg_address(u8 pid, u16 offset) return (void *)reg_addr; } +uint8_t *pcr_port_regs(u8 pid) +{ + return pcr_reg_address(pid, 0); +} + /* * Read PCR register. (This is internal function) * It returns PCR register and size in 1/2/4 bytes.

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New patch to review for coreboot: skylake: prefix the gpio functions with 'gpio_'
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11067 -gerrit commit 53d675a4f0b8326a26e7963fefeeb657b55e3c7c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 22 20:57:05 2015 -0500 skylake: prefix the gpio functions with 'gpio_' In order to provide more clarity on what some of the gpio functions are doing add a 'gpio_' prefix to the globally visible functions. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built glados. Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288192 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/gpio.c | 12 +++++------ src/soc/intel/skylake/include/soc/gpio.h | 34 ++++++++++++++++---------------- src/soc/intel/skylake/pmutil.c | 6 +++--- 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 9f7b409..7967231 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -25,8 +25,8 @@ #include <soc/pm.h> /* Keep the ordering intact GPP_A ~ G, GPD. - * As the gpio/smi functions get_smi_status() and - * enable_gpio_groupsmi() depends on this ordering. + * As the gpio/smi functions gpio_get_smi_status() and + * gpio_enable_groupsmi() depends on this ordering. */ static const GPIO_GROUP_INFO gpio_group_info[] = { /* GPP_A */ @@ -245,7 +245,7 @@ void gpio_set(gpio_t gpio_num, int value) WRITE, &outputvalue); } -void clear_all_smi(void) +void gpio_clear_all_smi(void) { u32 gpiogroupinfolength; u32 gpioindex = 0; @@ -264,7 +264,7 @@ void clear_all_smi(void) } } -void get_smi_status(u32 status[GPIO_COMMUNITY_MAX]) +void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]) { u32 num_of_communities; u32 gpioindex; @@ -285,7 +285,7 @@ void get_smi_status(u32 status[GPIO_COMMUNITY_MAX]) } } -void enable_all_smi(void) +void gpio_enable_all_smi(void) { u32 gpiogroupinfolength; u32 gpioindex = 0; @@ -304,7 +304,7 @@ void enable_all_smi(void) } } -void enable_gpio_groupsmi(gpio_t gpio_num, u32 mask) +void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask) { u32 gpioindex = 0; u32 smien = 0; diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 1d49a45..e8438ff 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -23,6 +23,23 @@ #include <stdint.h> +/* SOC has 8 GPIO communities GPP A~G, GPD */ +#define GPIO_COMMUNITY_MAX 8 + +typedef int gpio_t; + +/* Clear GPIO SMI Status */ +void gpio_clear_all_smi(void); + +/* Get GPIO SMI Status */ +void gpio_get_smi_status(u32 status[GPIO_COMMUNITY_MAX]); + +/* Enable GPIO SMI */ +void gpio_enable_all_smi(void); + +/* Enable GPIO individual Group SMI */ +void gpio_enable_groupsmi(gpio_t gpio_num, u32 mask); + /* * GPP_Ax to GPP_Gx; * where x=24 [between GPIO Community A to F] @@ -123,9 +140,6 @@ typedef struct { #define V_PCH_GPIO_GPP_G_PAD_MAX 8 #define V_PCH_GPIO_GPD_PAD_MAX 12 -/* SOC has 8 GPIO communities GPP A~G, GPD */ -#define GPIO_COMMUNITY_MAX 8 - #define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) #define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ GPIO_GET_GROUP_INDEX((pad >> 16))) @@ -295,20 +309,6 @@ typedef enum { GpioResetResume = 0x7 /* Resume Reset */ } GPIO_RESET_CONFIG; -typedef int gpio_t; - -/* Clear GPIO SMI Status */ -void clear_all_smi(void); - -/* Get GPIO SMI Status */ -void get_smi_status(u32 status[GPIO_COMMUNITY_MAX]); - -/* Enable GPIO SMI */ -void enable_all_smi(void); - -/* Enable GPIO individual Group SMI */ -void enable_gpio_groupsmi(gpio_t gpio_num, u32 mask); - /* * GPIO Electrical Configuration * Set GPIO termination and Pad Tolerance (applicable only for some pads) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index c22a120..85dc1b3 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -219,7 +219,7 @@ void disable_smi(u32 mask) void reset_alt_smi_status(void) { /*Clear GPIO SMI Status*/ - clear_all_smi(); + gpio_clear_all_smi(); } /* Print GPIO SMI status bits */ @@ -237,7 +237,7 @@ static u32 print_alt_smi_status(void) }; printk(BIOS_DEBUG, "ALT_STS: "); - get_smi_status(alt_sts); + gpio_get_smi_status(alt_sts); /* GPP_A to GPP_E GPIO has Status and Enable functionality*/ for (gpio_index = 0; gpio_index < ARRAY_SIZE(gpiowell); gpio_index++) { @@ -262,7 +262,7 @@ u32 clear_alt_smi_status(void) void enable_alt_smi(int gpionum, u32 mask) { /*Set GPIO EN Status*/ - enable_gpio_groupsmi(gpionum, mask); + gpio_enable_groupsmi(gpionum, mask); }

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New patch to review for coreboot: skylake: remove unused types and definitions in gpio.h
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11066 -gerrit commit f974cd033dd7400fa86994ddc7fa82e72b1339dc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jul 22 20:42:51 2015 -0500 skylake: remove unused types and definitions in gpio.h These types and definitions were carried over from a previous platform. However, they are not used. Remove them. BUG=chrome-os-partner:42982 BRANCH=None TEST=Built on glados Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c Original-Signed-off-by: Aaron Durbin <adurbin(a)chormium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288191 Original-Trybot-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/gpio.h | 139 ------------------------------- 1 file changed, 139 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 03ed119..1d49a45 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -23,23 +23,6 @@ #include <stdint.h> -/* PCH-LP GPIOBASE Registers */ -#define GPIO_OWNER(set) (0x00 + ((set) * 4)) -#define GPIO_PIRQ_APIC_EN 0x10 -#define GPIO_BLINK 0x18 -#define GPIO_SER_BLINK 0x1c -#define GPIO_SER_BLINK_CS 0x20 -#define GPIO_SER_BLINK_DATA 0x24 -#define GPIO_ROUTE(set) (0x30 + ((set) * 4)) -#define GPIO_ALT_GPI_SMI_STS 0x50 -#define GPIO_ALT_GPI_SMI_EN 0x54 -#define GPIO_RESET(set) (0x60 + ((set) * 4)) -#define GPIO_GLOBAL_CONFIG 0x7c -#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4)) -#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4)) -#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8)) -#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8)) - /* * GPP_Ax to GPP_Gx; * where x=24 [between GPIO Community A to F] @@ -148,115 +131,6 @@ typedef struct { GPIO_GET_GROUP_INDEX((pad >> 16))) #define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF) -/* conf0 */ -#define GPIO_MODE_NATIVE (0 << 0) -#define GPIO_MODE_GPIO (1 << 0) - -#define GPIO_DIR_OUTPUT (0 << 2) -#define GPIO_DIR_INPUT (1 << 2) - -#define GPIO_NO_INVERT (0 << 3) -#define GPIO_INVERT (1 << 3) - -#define GPIO_IRQ_EDGE (0 << 4) -#define GPIO_IRQ_LEVEL (1 << 4) - -#define GPI_LEVEL (1 << 30) - -#define GPIO_OUT_LOW 0 -#define GPIO_OUT_HIGH 1 -#define GPO_LEVEL_SHIFT 31 -#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_LOW (GPIO_OUT_LOW << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_HIGH (GPIO_OUT_HIGH << GPO_LEVEL_SHIFT) - -/* conf1 */ -#define GPIO_PULL_NONE (0 << 0) -#define GPIO_PULL_DOWN (1 << 0) -#define GPIO_PULL_UP (2 << 0) - -#define GPIO_SENSE_ENABLE (0 << 2) -#define GPIO_SENSE_DISABLE (1 << 2) - -/* owner */ -#define GPIO_OWNER_ACPI 0 -#define GPIO_OWNER_GPIO 1 - -/* route */ -#define GPIO_ROUTE_SCI 0 -#define GPIO_ROUTE_SMI 1 - -/* irqen */ -#define GPIO_IRQ_DISABLE 0 -#define GPIO_IRQ_ENABLE 1 - -/* blink */ -#define GPO_NO_BLINK 0 -#define GPO_BLINK 1 - -/* reset */ -#define GPIO_RESET_PWROK 0 -#define GPIO_RESET_RSMRST 1 - -/* pirq route to io-apic */ - -#define GPIO_PIRQ_APIC_MASK 0 -#define GPIO_PIRQ_APIC_ROUTE 1 - -#define PCH_GPIO_END \ - { .conf0 = GPIO_LIST_END } - -#define PCH_GPIO_NATIVE \ - { .conf0 = GPIO_MODE_NATIVE } - -#define PCH_GPIO_UNUSED \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ - .owner = GPIO_OWNER_GPIO, \ - .conf1 = GPIO_SENSE_DISABLE } - -#define PCH_GPIO_ACPI_SCI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ - .owner = GPIO_OWNER_ACPI, \ - .route = GPIO_ROUTE_SCI } - -#define PCH_GPIO_ACPI_SMI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ - .owner = GPIO_OWNER_ACPI, \ - .route = GPIO_ROUTE_SMI } - -#define PCH_GPIO_INPUT \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ - .owner = GPIO_OWNER_GPIO } - -#define PCH_GPIO_INPUT_INVERT \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ - .owner = GPIO_OWNER_GPIO } - -#define PCH_GPIO_IRQ_EDGE \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ - .owner = GPIO_OWNER_GPIO, \ - .irqen = GPIO_IRQ_ENABLE } - -#define PCH_GPIO_IRQ_LEVEL \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \ - .owner = GPIO_OWNER_GPIO, \ - .irqen = GPIO_IRQ_ENABLE } - -#define PCH_GPIO_PIRQ \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ - .owner = GPIO_OWNER_GPIO, \ - .pirq = GPIO_PIRQ_APIC_ROUTE } - -#define PCH_GPIO_OUT_HIGH \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \ - .owner = GPIO_OWNER_GPIO, \ - .conf1 = GPIO_SENSE_DISABLE } - -#define PCH_GPIO_OUT_LOW \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \ - .owner = GPIO_OWNER_GPIO, \ - .conf1 = GPIO_SENSE_DISABLE } - /* Number of pins used by SerialIo controllers */ #define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 #define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 @@ -269,19 +143,6 @@ typedef struct { #define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) #define N_PCH_GPIO_PAD_MODE 10 -struct gpio_config { - u8 gpio; - u32 conf0; - u32 conf1; - u8 owner; - u8 route; - u8 irqen; - u8 reset; - u8 blink; - u8 pirq; -} __attribute__ ((packed)); - - /* For any GpioPad usage in code use GPIO_PAD type*/ typedef u32 GPIO_PAD;

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New patch to review for coreboot: intel/braswell: fix build
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11065 -gerrit commit 1dd96ed9bbe64dd9c90e11f79b569c126514f212 Author: Jenny TC <jenny.tc(a)intel.com> Date: Thu Jun 18 14:02:00 2015 +0530 intel/braswell: fix build Commit "BCRD2: Enable LPDDR3" with the Change-Id listed below contained additions to braswell's chip.h which were lost during merging. BRANCH=None BUG=None TEST=google/strago builds Change-Id: I995b788b6a308cefa23228544127bb1e384bbcc7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 561edf23ab696772fd0a6af34cb435db9d96e912 Original-Change-Id: Ie08900bc62d517394412cc597274fb8f5b6b0f51 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Original-Change-Id: I1cb5a03b77baf2df125b648dd75c9f8166f5571e Original-Original-Signed-off-by: Jenny TC <jenny.tc(a)intel.com> Original-Original-Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Original-Reviewed-on: https://chromium-review.googlesource.com/282155 Original-Reviewed-on: https://chromium-review.googlesource.com/288880 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/soc/intel/braswell/chip.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 7422bc4..191fc01 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -34,6 +34,9 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable;

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New patch to review for coreboot: google/stout: Implement functions required by CHROMEOS
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11064 -gerrit commit b19997fc029e3fe7613eca35bcc8404e1b250a76 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:18:15 2015 +0200 google/stout: Implement functions required by CHROMEOS BRANCH=none BUG=chromium:513990 TEST=google/stout builds Change-Id: I00de7524297e4471a9f7d6afd0d2b991d29020e9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: b85c54af7d4def45f014ee1d9b79df0b649f90f7 Original-Change-Id: I0870dd11c97cecc932a135f73be8234a88c0622b Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288860 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/stout/chromeos.c | 36 +++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 824cb8f..b2ca6a7 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -35,21 +35,13 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; - - if (!gpio_base) - return; - - u32 gp_lvl = inl(gpio_base + GP_LVL); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; /* Write Protect: GPIO7 */ gpios->gpios[0].port = 7; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl >> 7) & 1; + gpios->gpios[0].value = !get_write_protect_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -68,7 +60,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid Switch: Virtual switch */ gpios->gpios[3].port = -1; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 1; /* Hard-code to open */ + gpios->gpios[3].value = get_lid_switch(); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button: Virtual switch */ @@ -91,6 +83,30 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return 0; + + u32 gp_lvl = inl(gpio_base + GP_LVL); + + return !((gp_lvl >> 7) & 1); +} + +int get_lid_switch(void) +{ + /* hard-code to open */ + return 1; +} + /* The dev-switch is virtual on Stout (and so handled elsewhere). */ int get_developer_mode_switch(void) {

1 0

New patch to review for coreboot: google/parrot: Implement functions required by CHROMEOS
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11063 -gerrit commit e950e9a5921dc3b5c8721142b6e880d04cbe8186 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:18:15 2015 +0200 google/parrot: Implement functions required by CHROMEOS BRANCH=none BUG=chromium:513990 TEST=google/parrot builds Change-Id: I5e354d6160e554f1c41e84eac6102e84de34b81d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: d5a6253e6f19815736a6b433f6c58e3be2e5841b Original-Change-Id: I3a3bf9ead333d56472f856c9efefff239fb70586 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288852 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/parrot/chromeos.c | 41 +++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 0c7f45a..164e192 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -43,16 +43,13 @@ void fill_lb_gpios(struct lb_gpios *gpios) if (!gpio_base) return; - u32 gp_lvl = inl(gpio_base + GP_LVL); - u32 gp_lvl3 = inl(gpio_base + GP_LVL3); - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; /* Write Protect: GPIO70 active high */ gpios->gpios[0].port = 70; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = (gp_lvl3 >> (70 - 64)) & 1; + gpios->gpios[0].value = !get_write_protect_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */ @@ -70,7 +67,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid switch GPIO active high (open). */ gpios->gpios[3].port = 15; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = ((gp_lvl >> 15) & 1); + gpios->gpios[3].value = get_lid_switch(); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); /* Power Button */ @@ -88,6 +85,22 @@ void fill_lb_gpios(struct lb_gpios *gpios) } #endif +int get_lid_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return 0; + + u32 gp_lvl = inl(gpio_base + GP_LVL); + return (gp_lvl >> 15) & 1; +} int get_developer_mode_switch(void) { @@ -115,6 +128,24 @@ int get_developer_mode_switch(void) return !((gp_lvl >> 17) & 1); } +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 0); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); +#endif + u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe; + + if (!gpio_base) + return 0; + + u32 gp_lvl3 = inl(gpio_base + GP_LVL3); + + return !((gp_lvl3 >> (70 - 64)) & 1); +} + int get_recovery_mode_switch(void) { u8 rec_mode;

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New patch to review for coreboot: google/butterfly: Implement functions required by CHROMEOS
by Patrick Georgi 29 Jul '15

29 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11062 -gerrit commit 01dbf17fd0c737296087963032995aed070403ca Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 23:18:15 2015 +0200 google/butterfly: Implement functions required by CHROMEOS BRANCH=none BUG=chromium:513990 TEST=google/butterfly builds Change-Id: Ia678ca4b0778ee4a2e55ba44a5d89ac6dd691b35 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 0d82ea2090fae9c66f41ee05cc20a9b22d3641c0 Original-Change-Id: I2fea10c17b769ca76b9d0b80978b4c512ed8c680 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288851 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> --- src/mainboard/google/butterfly/chromeos.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index fd7ef4e..c23f827 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -56,7 +56,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: GPIO active Low */ gpios->gpios[0].port = WP_GPIO; gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = get_pch_gpio(WP_GPIO); + gpios->gpios[0].value = !get_write_protect_state(); strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); @@ -74,10 +74,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); /* lid switch value from EC */ - lidswitch = (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; gpios->gpios[3].port = -1; gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = lidswitch; + gpios->gpios[3].value = get_lid_switch(); strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH); printk(BIOS_DEBUG,"LID SWITCH FROM EC: %x\n", lidswitch); @@ -126,6 +125,16 @@ int get_pch_gpio(unsigned char gpio_num) return retval; } +int get_write_protect_state(void) +{ + return !get_pch_gpio(WP_GPIO); +} + +int get_lid_switch(void) +{ + return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; +} + int get_developer_mode_switch(void) { int dev_mode = 0;

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coreboot-gerrit July 2015