coreboot-gerrit July 2015

coreboot-gerrit@coreboot.org

1 participants
1048 discussions

Patch set updated for coreboot: intel sandybridge: don't turn off PEG
by Patrick Rudolph 28 Jul '15

28 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11058 -gerrit commit 2aebc87ad7658cdf0f295b1a25ee479c27d21485 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jul 28 07:51:10 2015 +0200 intel sandybridge: don't turn off PEG Don't disable PEG bits while turning on IGD. Fixes PCI device enumeration of PEG devices. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: I2d6522504e4404f2d57f9c319351d08317aefdcb Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index e77cf22..7b60ec7 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -155,6 +155,7 @@ static void sandybridge_setup_graphics(void) void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; + u32 deven; u8 reg8; /* Device ID Override Enable should be done very early */ @@ -172,8 +173,9 @@ void sandybridge_early_initialization(int chipset_type) /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(); - /* Device Enable */ - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_HOST | DEVEN_IGD); + /* Device Enable, don't touch PEG bits */ + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); sandybridge_setup_graphics(); }

1 0

Patch set updated for coreboot: intel sandybridge: enable PEG clock-gating on demand
by Patrick Rudolph 28 Jul '15

28 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11059 -gerrit commit 0e4716de1bbb18eb8d3d2ee77e81f5a051a0a942 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jul 28 08:01:02 2015 +0200 intel sandybridge: enable PEG clock-gating on demand Activate PEG clock-gating only if all PEG devices are disabled. Fixes system hang when trying to access PEG registers. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: I7d62fbb83c16741965639cea1a0e4978d4e3d6da Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/northbridge.c | 48 ++++++++++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 8 ---- src/northbridge/intel/sandybridge/raminit_native.c | 7 ---- 3 files changed, 48 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0e0ba00..76f03f3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -361,6 +361,51 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x88) = reg32; } +/* Disable unused PEG devices based on devicetree */ +static void disable_peg(void) +{ + struct device *dev; + u32 reg; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + reg = pci_read_config32(dev, DEVEN); + + dev = dev_find_slot(0, PCI_DEVFN(1, 2)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG12.\n"); + reg &= ~DEVEN_PEG12; + } + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG11.\n"); + reg &= ~DEVEN_PEG11; + } + dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG10.\n"); + reg &= ~DEVEN_PEG10; + } + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling IGD.\n"); + reg &= ~DEVEN_IGD; + } + dev = dev_find_slot(0, PCI_DEVFN(6, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG60.\n"); + reg &= ~DEVEN_PEG60; + } + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pci_write_config32(dev, DEVEN, reg); + if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { + /* Set the PEG clock gating bit. + * Disables the IO clock on all PEG devices. */ + MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; + printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); + } +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; @@ -411,6 +456,9 @@ static void northbridge_init(struct device *dev) /* Set here before graphics PM init */ MCHBAR32(0x5500) = 0x00100001; + + /* Turn off unused devices */ + disable_peg(); } static void northbridge_enable(device_t dev) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 053a487..1f6b75c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -199,13 +199,6 @@ static void report_memory_config(void) } } -static void post_system_agent_init(struct pei_data *pei_data) -{ - /* If PCIe init is skipped, set the PEG clock gating */ - if (!pei_data->pcie_init) - MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; -} - /** * Find PEI executable in coreboot filesystem and execute it. * @@ -288,6 +281,5 @@ void sdram_initialize(struct pei_data *pei_data) else intel_early_me_status(); - post_system_agent_init(pei_data); report_memory_config(); } diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 790f47c..9df102a 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -234,12 +234,6 @@ static void report_memory_config(void) } } -static void post_system_agent_init(void) -{ - /* If PCIe init is skipped, set the PEG clock gating */ - MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; -} - void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -3888,7 +3882,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); intel_early_me_status(); - post_system_agent_init(); report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume);

1 0

New patch to review for coreboot: intel sandybridge: enable PEG clock-gating on demand
by Patrick Rudolph 28 Jul '15

28 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11059 -gerrit commit b0c2c77dfd4b68d5c6712978f9018b8be71adce6 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jul 28 08:01:02 2015 +0200 intel sandybridge: enable PEG clock-gating on demand Activate PEG clock-gating only if all PEG devices are disabled. Fixes system hang when trying to access PEG registers. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: I7d62fbb83c16741965639cea1a0e4978d4e3d6da Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/northbridge.c | 48 ++++++++++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 8 ---- src/northbridge/intel/sandybridge/raminit_native.c | 7 ---- 3 files changed, 48 insertions(+), 15 deletions(-) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0e0ba00..76f03f3 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -361,6 +361,51 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x88) = reg32; } +/* Disable unused PEG devices based on devicetree */ +static void disable_peg(void) +{ + struct device *dev; + u32 reg; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + reg = pci_read_config32(dev, DEVEN); + + dev = dev_find_slot(0, PCI_DEVFN(1, 2)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG12.\n"); + reg &= ~DEVEN_PEG12; + } + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG11.\n"); + reg &= ~DEVEN_PEG11; + } + dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG10.\n"); + reg &= ~DEVEN_PEG10; + } + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling IGD.\n"); + reg &= ~DEVEN_IGD; + } + dev = dev_find_slot(0, PCI_DEVFN(6, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG60.\n"); + reg &= ~DEVEN_PEG60; + } + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pci_write_config32(dev, DEVEN, reg); + if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { + /* Set the PEG clock gating bit. + * Disables the IO clock on all PEG devices. */ + MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; + printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); + } +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; @@ -411,6 +456,9 @@ static void northbridge_init(struct device *dev) /* Set here before graphics PM init */ MCHBAR32(0x5500) = 0x00100001; + + /* Turn off unused devices */ + disable_peg(); } static void northbridge_enable(device_t dev) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 053a487..1f6b75c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -199,13 +199,6 @@ static void report_memory_config(void) } } -static void post_system_agent_init(struct pei_data *pei_data) -{ - /* If PCIe init is skipped, set the PEG clock gating */ - if (!pei_data->pcie_init) - MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; -} - /** * Find PEI executable in coreboot filesystem and execute it. * @@ -288,6 +281,5 @@ void sdram_initialize(struct pei_data *pei_data) else intel_early_me_status(); - post_system_agent_init(pei_data); report_memory_config(); } diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 790f47c..9df102a 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -234,12 +234,6 @@ static void report_memory_config(void) } } -static void post_system_agent_init(void) -{ - /* If PCIe init is skipped, set the PEG clock gating */ - MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; -} - void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -3888,7 +3882,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); intel_early_me_status(); - post_system_agent_init(); report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume);

1 0

New patch to review for coreboot: intel sandybridge: don't turn off PEG
by Patrick Rudolph 28 Jul '15

28 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11058 -gerrit commit 0c645e4b3cb0d1c41e2f7d5f5bb1c3b8105ac660 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jul 28 07:51:10 2015 +0200 intel sandybridge: don't turn off PEG Don't disable PEG bits while turning on IGD. Fixes PCI device enumaration of PEG devices. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H Change-Id: I2d6522504e4404f2d57f9c319351d08317aefdcb Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index e77cf22..7b60ec7 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -155,6 +155,7 @@ static void sandybridge_setup_graphics(void) void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; + u32 deven; u8 reg8; /* Device ID Override Enable should be done very early */ @@ -172,8 +173,9 @@ void sandybridge_early_initialization(int chipset_type) /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(); - /* Device Enable */ - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_HOST | DEVEN_IGD); + /* Device Enable, don't touch PEG bits */ + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); sandybridge_setup_graphics(); }

1 0

Patch set updated for coreboot: ddr3 spd: account for fine timebase
by Patrick Rudolph 28 Jul '15

28 Jul '15

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11027 -gerrit commit 0e6f8b37d9e87affe6e597b8047c7c726428d20f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Jul 15 10:03:30 2015 +0200 ddr3 spd: account for fine timebase SPD revision 1.1 adds optional fine timebase adjustments. Check SPD revision and apply the correction values. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ" * SPD Rev1.3 * Fine timebase is 1 pico-second. * All compensation values are zero. Change-Id: I3576821af5e78d2e9ea4d583a59dcc90cef6995f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index e1bb873..01b1e7e 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -32,6 +32,18 @@ *----------------------------------------------------------------------------*/ /** + * \brief Converts u8 to signed integer + */ +static inline int u8_to_signed(u8 raw) +{ + int cooked; + cooked = raw & 0x7f; + if (raw & 0x80) + cooked -= 128; + return cooked; +} + +/** * \brief Checks if the DIMM is Registered based on byte[3] of the SPD * * Tells if the DIMM type is registered or not. @@ -110,9 +122,10 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) { int ret; u16 crc, spd_crc; - u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width; + u8 capacity_shift, bus_width; u8 reg8; u32 mtb; /* medium time base */ + u32 fine_tb; /* fine time base */ unsigned int val, param; ret = SPD_STATUS_OK; @@ -239,12 +252,6 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width * dimm->ranks) / dimm->width; - /* Fine Timebase (FTB) Dividend/Divisor */ - /* Dividend */ - ftb_dividend = (spd[9] >> 4) & 0x0f; - /* Divisor */ - ftb_divisor = spd[9] & 0x0f; - /* Medium Timebase = * Medium Timebase (MTB) Dividend / * Medium Timebase (MTB) Divisor */ @@ -277,6 +284,26 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* Minimum Four Activate Window Delay Time (tFAWmin) */ dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + /* SPD Revision 1.1+ */ + if (((spd[1] & 0xf0) == 0x10) && ((spd[1] & 0x0f) > 0) + && (spd[9] & 0xf0) && (spd[9] & 0x0f)) { + /* Fine Timebase (FTB) is in units of pico-seconds, + * while MTB is in units of nano-seconds + * Dividend/Divisor */ + fine_tb = ((spd[9] & 0xf0) << 4) / (spd[9] & 0x0f); + + /* SDRAM Minimum Cycle Time (tCKmin) correction */ + dimm->tCK += (u8_to_signed(spd[34]) * fine_tb) / 1000; + /* Minimum CAS Latency Time (tAAmin) correction */ + dimm->tAA += (u8_to_signed(spd[35]) * fine_tb) / 1000; + /* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */ + dimm->tRCD += (u8_to_signed(spd[36]) * fine_tb) / 1000; + /* Minimum Row Precharge Delay Time (tRPmin) correction */ + dimm->tRP += (u8_to_signed(spd[37]) * fine_tb) / 1000; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) correction */ + dimm->tRC += (u8_to_signed(spd[38]) * fine_tb) / 1000; + } + /* SDRAM Optional Features */ reg8 = spd[30]; printram(" Optional features :");

1 0

Patch merged into coreboot/master: arch/x86: make dependency explicit
by gerrit＠coreboot.org 27 Jul '15

27 Jul '15

the following patch was just integrated into master: commit ef0158ec90b5828b8b862deee614fde61c81d4b5 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 17:47:55 2015 +0200 arch/x86: make dependency explicit bootblock.inc requires config.h to be around which may need to be created. Have make be aware of it. Change-Id: I79ad003b461d7da7a5afecdae55fdd07ba735821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/11057 for details. -gerrit

1 0

Patch set updated for coreboot: cbfstool: add cbfs file attribute structure
by Patrick Georgi 27 Jul '15

27 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10937 -gerrit commit 230014e717dff183b8ab1ed647e34551e4c2770d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jul 22 21:32:03 2015 +0200 cbfstool: add cbfs file attribute structure This is a generic structure, not unlike the cbtables design, from which to build specialized TLV data structures. Change-Id: I98a75eef19f049ad67d46cdc2790949dcd155797 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/cbfstool/cbfs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index f63b881..064d3e7 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -85,6 +85,12 @@ struct cbfs_file { _Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch"); +struct cbfs_file_attribute { + uint32_t tag; + uint32_t len; + uint8_t data[]; +} __PACKED; + struct cbfs_stage { uint32_t compression; uint64_t entry;

1 0

New patch to review for coreboot: arch/x86: make dependency explicit
by Patrick Georgi 27 Jul '15

27 Jul '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11057 -gerrit commit 709288c8d0a1996df3657a285c7234e77ce293e8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jul 27 17:47:55 2015 +0200 arch/x86: make dependency explicit bootblock.inc requires config.h to be around which may need to be created. Have make be aware of it. Change-Id: I79ad003b461d7da7a5afecdae55fdd07ba735821 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4b61767..d5b320f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -114,7 +114,7 @@ $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(o @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d

1 0

Patch set updated for coreboot: gigabyte/ga-b75m-d3h: Update device tree
by Damien Zammit 26 Jul '15

26 Jul '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10895 -gerrit commit 0b8707b9e8650a0672b7cde2e2fc61363f1a5510 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Jul 13 15:27:01 2015 +1000 gigabyte/ga-b75m-d3h: Update device tree This patch resolves the outstanding issues with PCI device enumeration and getting the board to boot into GNU/Linux with VGA rom. Previously the board would not boot to GNU/Linux with video, even if VGA rom was used. Bugs in the devicetree were fixed according to superiotool output. Tested on GA-B75M-D3H with VGA rom. Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64) Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 19a476c..f4a8664 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -24,7 +24,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge device pci 1b.0 on # High Definition Audio subsystemid 0x1458 0xa002 end - device pci 1c.0 off end # PCIe Port #1 + device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 @@ -92,17 +92,19 @@ chip northbridge/intel/sandybridge drq 0x74 = 4 end device pnp 2e.4 on # EC + io 0x60 = 0xa30 irq 0x70 = 9 + io 0x62 = 0xa20 end device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 irq 0x70 = 1 + io 0x62 = 0x64 end device pnp 2e.6 on # Mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO - irq 0x70 = 0 - end + device pnp 2e.7 off end # GPIO device pnp 2e.a off end # IR end end

1 0

Patch set updated for coreboot: gigabyte/ga-b75m-d3h: Update device tree
by Damien Zammit 26 Jul '15

26 Jul '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10895 -gerrit commit 908f998c4d2fb14690176a230be3ce5d4d662aa4 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Jul 13 15:27:01 2015 +1000 gigabyte/ga-b75m-d3h: Update device tree This patch resolves all known outstanding issues with PCI device enumeration and getting the board to boot into GNU/Linux with VGA rom. (There were bugs in the devicetree). Tested on GA-B75M-D3H with VGA rom. Booted to GNU/Linux (Fedora 22 4.0.4-301.fc22.x86_64) Change-Id: Ide1f406652659e6f99ee5d993719c187650fffe4 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 19a476c..f4a8664 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -24,7 +24,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # vga controller subsystemid 0x1458 0xd000 end @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge device pci 1b.0 on # High Definition Audio subsystemid 0x1458 0xa002 end - device pci 1c.0 off end # PCIe Port #1 + device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 @@ -92,17 +92,19 @@ chip northbridge/intel/sandybridge drq 0x74 = 4 end device pnp 2e.4 on # EC + io 0x60 = 0xa30 irq 0x70 = 9 + io 0x62 = 0xa20 end device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 irq 0x70 = 1 + io 0x62 = 0x64 end device pnp 2e.6 on # Mouse irq 0x70 = 12 end - device pnp 2e.7 on # GPIO - irq 0x70 = 0 - end + device pnp 2e.7 off end # GPIO device pnp 2e.a off end # IR end end

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2015