coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

New patch to review for coreboot: google/chell: update dptf TSR1 & TSR2 critial points
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12604 -gerrit commit 0d1f21c77624604511bafe4979fbf703ec05fb90 Author: Wisley <wisley.chen(a)quantatw.com> Date: Tue Nov 24 20:12:36 2015 +0800 google/chell: update dptf TSR1 & TSR2 critial points update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie(a)chromium.org> Original-Tested-by: Chen Wisley <wisley.chen(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen(a)quantatw.com> --- src/mainboard/google/chell/acpi/dptf.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index 45783dc..c8362b7 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -25,12 +25,12 @@ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "Charger" #define DPTF_TSR1_PASSIVE 55 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_CRITICAL 75 #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "DRAM" #define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_NAME "WiFi"

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New patch to review for coreboot: mediatek/mt8173: Add GPIO driver
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12603 -gerrit commit 2460984b27945c69ffd2313625d8c340633756f7 Author: Biao Huang <biao.huang(a)mediatek.com> Date: Fri Jul 31 17:10:55 2015 +0800 mediatek/mt8173: Add GPIO driver BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I54755d81144b27cc9a674434609b2d99f1d486ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d88a3ed43ad32e245e54a9599fb8667ce288217b Original-Change-Id: I1142091650c0de2207c7635031aa7edfe487ad88 Original-Signed-off-by: Biao Huang <biao.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292672 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + src/soc/mediatek/mt8173/Makefile.inc | 4 +- src/soc/mediatek/mt8173/gpio.c | 181 +++++++++++++++++++++++++++++ src/soc/mediatek/mt8173/include/soc/gpio.h | 92 +++++++++++++++ 4 files changed, 277 insertions(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 0f0b134..6f23eba 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -12,6 +12,7 @@ config SOC_MEDIATEK_MT8173 select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAS_PRECBMEM_TIMESTAMP_REGION + select GENERIC_GPIO_LIB if SOC_MEDIATEK_MT8173 diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 54b04bd..abaf3cc 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -28,7 +28,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif -bootblock-y += pmic_wrap.c +bootblock-y += gpio.c pmic_wrap.c ################################################################################ @@ -37,6 +37,7 @@ romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c +romstage-y += gpio.c ################################################################################ @@ -45,6 +46,7 @@ ramstage-y += cbfs.c ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c new file mode 100644 index 0000000..1f0e571 --- /dev/null +++ b/src/soc/mediatek/mt8173/gpio.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <gpio.h> +#include <types.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> + +enum { + MAX_8173_GPIO = 134, + MAX_GPIO_REG_BITS = 16, + MAX_GPIO_MODE_PER_REG = 5, + GPIO_MODE_BITS = 3, +}; + +enum { + GPIO_DIRECTION_IN = 0, + GPIO_DIRECTION_OUT = 1, +}; + +enum { + GPIO_MODE = 0, +}; + +static void pos_bit_calc(u32 pin, u32 *pos, u32 *bit) +{ + *pos = pin / MAX_GPIO_REG_BITS; + *bit = pin % MAX_GPIO_REG_BITS; +} + +static void pos_bit_calc_for_mode(u32 pin, u32 *pos, u32 *bit) +{ + *pos = pin / MAX_GPIO_MODE_PER_REG; + *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; +} + +static s32 gpio_set_dir(u32 pin, u32 dir) +{ + u32 pos; + u32 bit; + u16 *reg; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (dir == GPIO_DIRECTION_IN) + reg = &mt8173_gpio->dir[pos].rst; + else + reg = &mt8173_gpio->dir[pos].set; + + write16(reg, 1L << bit); + + return 0; +} + +void gpio_set_pull(gpio_t pin, enum pull_enable enable, + enum pull_select select) +{ + u32 pos; + u32 bit; + u16 *en_reg, *sel_reg; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (enable == GPIO_PULL_DISABLE) { + en_reg = &mt8173_gpio->pullen[pos].rst; + } else { + /* These pins' pulls can't be set through GPIO controller. */ + assert(pin < 22 || pin > 27); + assert(pin < 47 || pin > 56); + assert(pin < 57 || pin > 68); + assert(pin < 73 || pin > 78); + assert(pin < 100 || pin > 105); + assert(pin < 119 || pin > 124); + + en_reg = &mt8173_gpio->pullen[pos].set; + sel_reg = (select == GPIO_PULL_DOWN) ? + (&mt8173_gpio->pullsel[pos].rst) : + (&mt8173_gpio->pullsel[pos].set); + write16(sel_reg, 1L << bit); + } + write16(en_reg, 1L << bit); +} + +int gpio_get(gpio_t pin) +{ + u32 pos; + u32 bit; + u16 *reg; + s32 data; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + reg = &mt8173_gpio->din[pos].val; + data = read32(reg); + + return (data & (1L << bit)) ? 1 : 0; +} + +void gpio_set(gpio_t pin, int output) +{ + u32 pos; + u32 bit; + u16 *reg; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (output == 0) + reg = &mt8173_gpio->dout[pos].rst; + else + reg = &mt8173_gpio->dout[pos].set; + write16(reg, 1L << bit); +} + +void gpio_set_mode(gpio_t pin, int mode) +{ + u32 pos; + u32 bit; + u32 mask = (1L << GPIO_MODE_BITS) - 1; + + assert(pin <= MAX_8173_GPIO); + + pos_bit_calc_for_mode(pin, &pos, &bit); + + clrsetbits_le32(&mt8173_gpio->mode[pos].val, + mask << bit, mode << bit); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); + gpio_set_dir(gpio, GPIO_DIRECTION_IN); + gpio_set_mode(gpio, GPIO_MODE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); + gpio_set(gpio, value); + gpio_set_dir(gpio, GPIO_DIRECTION_OUT); + gpio_set_mode(gpio, GPIO_MODE); +} diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h new file mode 100644 index 0000000..d0a3dd2 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef SOC_MEDIATEK_MT8173_GPIO_H +#define SOC_MEDIATEK_MT8173_GPIO_H + +#include <stdint.h> +#include <stdlib.h> +#include <soc/addressmap.h> + +enum pull_enable { + GPIO_PULL_DISABLE = 0, + GPIO_PULL_ENABLE = 1, +}; + +enum pull_select { + GPIO_PULL_DOWN = 0, + GPIO_PULL_UP = 1, +}; + +enum external_power { + GPIO_EINT_3P3V = 0, + GPIO_EINT_1P8V = 1, +}; + +typedef u32 gpio_t; + +struct val_regs { + uint16_t val; + uint16_t align1; + uint16_t set; + uint16_t align2; + uint16_t rst; + uint16_t align3[3]; +}; + +struct gpio_regs { + struct val_regs dir[9]; + uint8_t rsv00[112]; + struct val_regs pullen[9]; + uint8_t rsv01[112]; + struct val_regs pullsel[9]; + uint8_t rsv02[112]; + uint8_t rsv03[256]; + struct val_regs dout[9]; + uint8_t rsv04[112]; + struct val_regs din[9]; + uint8_t rsv05[112]; + struct val_regs mode[27]; + uint8_t rsv06[336]; + struct val_regs ies[3]; + struct val_regs smt[3]; + uint8_t rsv07[160]; + struct val_regs tdsel[8]; + struct val_regs rdsel[6]; + uint8_t rsv08[32]; + struct val_regs drv_mode[10]; + uint8_t rsv09[96]; + struct val_regs msdc_rsv0[11]; + struct val_regs msdc2_ctrl5; + struct val_regs msdc_rsv1[12]; + uint8_t rsv10[64]; + struct val_regs exmd_ctrl[1]; + uint8_t rsv11[48]; + struct val_regs kpad_ctrl[2]; + struct val_regs hsic_ctrl[4]; +}; + +check_member(gpio_regs, msdc2_ctrl5, 0xcb0); +check_member(gpio_regs, hsic_ctrl[3], 0xe50); + +static struct gpio_regs *const mt8173_gpio = (void *)(GPIO_BASE); + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select); +void gpio_set_mode(gpio_t gpio, int mode); +#endif /* SOC_MEDIATEK_MT8173_GPIO_H */

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New patch to review for coreboot: mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2C
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12602 -gerrit commit 83e07ae3fe29eb41e57060b04a850c83c7016559 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Nov 23 15:08:44 2015 +0800 mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2C L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE from SRAM_L2C to ensure that it can be switched correctly. BRANCH=none BUG=chrome-os-partner47952 TEST=none Change-Id: I255a0116148777d384dda43682365a5e2375cb5d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792 Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313888 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/include/soc/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index a703808..f41ce34 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -34,14 +34,14 @@ SECTIONS SRAM_L2C_START(0x000C0000) BOOTBLOCK(0x000C1000, 85K) VERSTAGE(0x000D7000, 114K) - PRERAM_CBFS_CACHE(0x000F6000, 16K) SRAM_L2C_END(0x00100000) SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) - TIMESTAMP(0x00107000, 4K) - ROMSTAGE(0x00108000, 92K) + PRERAM_CBFS_CACHE(0x00107000, 16K) + TIMESTAMP(0x0010B000, 4K) + ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) TTB(0x00128000, 28K) DMA_COHERENT(0x0012F000, 4K)

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New patch to review for coreboot: cbfs_spi: Initialize spi_flash when initializing cbfs_cache
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12601 -gerrit commit 24e6522e808fcc5e3c3298467c40b713a6197b6b Author: Mary Ruthven <mruthven(a)chromium.org> Date: Tue Nov 24 09:43:27 2015 -0800 cbfs_spi: Initialize spi_flash when initializing cbfs_cache Most devices do not use SPI before they initialize CBMEM. This change initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram cbfs cache so it is not overwritten when boot_device_init is called later. BUG=chromium:210230 BRANCH=none TEST=confirm that the first cbfs access can occur before RAM initialized and after on panther and jerry. Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0 Original-Signed-off-by: Mary Ruthven <mruthven(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/314311 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memlayout.h | 2 +- src/include/symbols.h | 6 +++--- src/lib/cbfs_spi.c | 9 ++++++++- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 899836c..3178bc4 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -82,7 +82,7 @@ #if ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ - REGION(dram_cbfs_cache, addr, size, 4) + REGION(postram_cbfs_cache, addr, size, 4) #elif defined(__PRE_RAM__) #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index bf875ae..aa055ec 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -41,9 +41,9 @@ extern u8 _stack[]; extern u8 _estack[]; #define _stack_size (_estack - _stack) -extern u8 _dram_cbfs_cache[]; -extern u8 _edram_cbfs_cache[]; -#define _dram_cbfs_cache_size (_edram_cbfs_cache - _dram_cbfs_cache) +extern u8 _postram_cbfs_cache[]; +extern u8 _epostram_cbfs_cache[]; +#define _postram_cbfs_cache_size (_epostram_cbfs_cache - _postram_cbfs_cache) extern u8 _cbfs_cache[]; extern u8 _ecbfs_cache[]; diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c index 82c3b83..ffa0628 100644 --- a/src/lib/cbfs_spi.c +++ b/src/lib/cbfs_spi.c @@ -45,7 +45,14 @@ static struct mmap_helper_region_device mdev = static void initialize_mdev(int unused) { - mmap_helper_device_init(&mdev, _dram_cbfs_cache, _dram_cbfs_cache_size); + /* + * Call boot_device_init() to ensure spi_flash is initialized before + * backing mdev with postram cache. This prevents the mdev backing from + * being overwritten if spi_flash was not accessed before dram was up. + */ + boot_device_init(); + mmap_helper_device_init(&mdev, _postram_cbfs_cache, + _postram_cbfs_cache_size); } ROMSTAGE_CBMEM_INIT_HOOK(initialize_mdev);

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New patch to review for coreboot: intel/kunimitsu: Coreboot GPIO changes for FAB 4.
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12600 -gerrit commit fdc5a7f39c70bda1dc57ccf8fbee7d5f031e977d Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Mon Oct 26 15:00:46 2015 -0700 intel/kunimitsu: Coreboot GPIO changes for FAB 4. This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID, AUDIO_IRQ and BOOT_BEEP. BUG=chrome-os-partner:47513 BRANCH=none TEST=Built for kunimitsu but not verified on Fab 4. Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7 Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b Original-Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311806 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/mainboard/intel/kunimitsu/gpio.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 9703cdb..a06e42d 100755 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -60,7 +60,7 @@ static const struct pad_config gpio_table[] = { /* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ /* GPP_A7 */ +/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PCH_LPC_CLK */ /* GPP_A10 */ @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), +/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), /* GSPI0_CS# */ /* GPP_B15 */ /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), @@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = { /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* SATAXPCIE1 */ /* GPP_E1 */ /* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* CPU_GP0 */ /* GPP_E3 */ +/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), /* SATA_DEVSLP1 */ /* GPP_E5 */ /* SATA_DEVSLP2 */ /* GPP_E6 */ @@ -184,7 +184,7 @@ static const struct pad_config gpio_table[] = { /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), -/* I2C5_SCL */ /* GPP_F11 */ +/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -196,7 +196,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* GPP_F23 */ +/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 1, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),

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New patch to review for coreboot: google/glados: Disable kepler device
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12599 -gerrit commit df17fc4441a86f7f2e41e55898c96d32e942ac45 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Nov 21 18:47:49 2015 -0800 google/glados: Disable kepler device Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/devicetree.cb | 9 +++------ src/mainboard/google/glados/gpio.h | 4 ++-- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 7e1e6c7..f6aaac3 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -43,15 +43,12 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" - # Enable Root port 1 and 5. + # Enable Root port 1. register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port (board) register "usb2_ports[1]" = "USB2_PORT_MAX" # Type-C Port (flex) @@ -106,7 +103,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index d42b711..cd7a936 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -115,7 +115,7 @@ static const struct pad_config gpio_table[] = { /* UART0_RXD */ /* GPP_C8 */ /* UART0_TXD */ /* GPP_C9 */ /* UART0_RTS# */ /* GPP_C10 */ -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -230,7 +230,7 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; #endif

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New patch to review for coreboot: google/chell: Update mainboard for EVT
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12598 -gerrit commit 6cb73e1ce7cfefeb91c2bdbcfa583af422ec36c7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Nov 21 18:43:18 2015 -0800 google/chell: Update mainboard for EVT - Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 15 ++++++--------- src/mainboard/google/chell/gpio.h | 6 +++--- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index e76b015..9bd06b2 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -35,7 +35,7 @@ chip soc/intel/skylake register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "2" register "IshEnable" = "0" register "PttSwitch" = "0" @@ -43,18 +43,15 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" - # Enable Root port 1 and 5. + # Enable Root port 1. register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[4]" = "1" # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2# + # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkReqNumber[4]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2 + register "usb2_ports[0]" = "USB2_PORT_LONG" # Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_LONG" # Type-C Port 2 register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera @@ -106,7 +103,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index a347454..c6e07a6 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = { /* UART0_RXD */ /* GPP_C8 */ /* UART0_TXD */ /* GPP_C9 */ /* UART0_RTS# */ /* GPP_C10 */ -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -153,7 +153,7 @@ static const struct pad_config gpio_table[] = { /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ /* GPP_D21 */ -/* SPI1_IO3 */ /* GPP_D22 */ +/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ /* GPP_E1 */ @@ -233,7 +233,7 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; #endif

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New patch to review for coreboot: intel/skylake: Add ACPI device for audio controller
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12597 -gerrit commit 70a54e51338cf7a43f8551669de24cbb34b87995 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Nov 21 18:40:19 2015 -0800 intel/skylake: Add ACPI device for audio controller Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if it has been set in NVS. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on glados and chell Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313824 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/globalnvs.asl | 2 + src/soc/intel/skylake/acpi/pch.asl | 3 ++ src/soc/intel/skylake/acpi/pch_hda.asl | 88 ++++++++++++++++++++++++++++++++ src/soc/intel/skylake/include/soc/nvs.h | 5 +- 4 files changed, 96 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 2018f34..1ea7e53 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -61,6 +61,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit DPTE, 8, // 0x30 - Enable DPTF + NHLA, 64, // 0x31 - NHLT Address + NHLL, 32, // 0x39 - NHLT Length /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index ef46c15..4e7c951 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -30,6 +30,9 @@ /* LPC 0:1f.0 */ #include "lpc.asl" +/* PCH HDA */ +#include "pch_hda.asl" + /* PCIE Ports */ #include "pcie.asl" diff --git a/src/soc/intel/skylake/acpi/pch_hda.asl b/src/soc/intel/skylake/acpi/pch_hda.asl new file mode 100644 index 0000000..509e6bf --- /dev/null +++ b/src/soc/intel/skylake/acpi/pch_hda.asl @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Audio Controller - Device 31, Function 3 */ + +Device (HDAS) +{ + Name (_ADR, 0x001F0003) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 13be921..032068f 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -51,8 +51,9 @@ typedef struct { u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u8 dpte; /* 0x30 - Enable DPTF */ - - u8 unused[207]; + u64 nhla; /* 0x31 - NHLT Address */ + u32 nhll; /* 0x39 - NHLT Length */ + u8 unused[195]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

1 0

New patch to review for coreboot: intel/skylake: Remove unused code to add SSDT2
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12596 -gerrit commit 53d3e292bc757ec6cd1c7b22d2542de638994d9f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Nov 21 18:42:10 2015 -0800 intel/skylake: Remove unused code to add SSDT2 This code is doing nothing and is not needed. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313823 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index cd8b86f..36b5bb4 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -541,26 +541,8 @@ unsigned long southcluster_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - acpi_header_t *ssdt2; - current = acpi_write_hpet(device, current, rsdp); ALIGN_CURRENT; - - ssdt2 = (acpi_header_t *)current; - memset(ssdt2, 0, sizeof(acpi_header_t)); - if (ssdt2->length) { - current += ssdt2->length; - acpi_add_table(rsdp, ssdt2); - printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n",ssdt2, - ssdt2->length); - ALIGN_CURRENT; - } else { - ssdt2 = NULL; - printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); - } - - printk(BIOS_DEBUG, "current = %lx\n", current); - return current; }

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New patch to review for coreboot: intel/fsp: Add post codes for FSP phases
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12595 -gerrit commit 66bf1008c86dca7b62691a407197bd60c3f400cd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sun Nov 22 14:53:57 2015 -0800 intel/fsp: Add post codes for FSP phases Add post codes for the various FSP phases and use them as appropriate in FSP 1.0 and 1.1 implementations. This will make it more consistent to debug FSP hangs and resets. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados and chell Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547 Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313822 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_0/cache_as_ram.inc | 2 +- src/drivers/intel/fsp1_0/fsp_util.c | 3 +++ src/drivers/intel/fsp1_1/after_raminit.S | 2 ++ src/drivers/intel/fsp1_1/cache_as_ram.inc | 2 +- src/drivers/intel/fsp1_1/fsp_util.c | 9 +++++-- src/drivers/intel/fsp1_1/raminit.c | 1 + src/drivers/intel/fsp1_1/ramstage.c | 1 + src/include/console/post_codes.h | 42 +++++++++++++++++++++++++++++++ 8 files changed, 58 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index 24de3a8..045bfb3 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -47,7 +47,7 @@ find_fsp_ret: jmp .Lhlt find_fsp_ok: - post_code(0x22) + post_code(POST_FSP_TEMP_RAM_INIT) /* Calculate entry into FSP */ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index ca381ff..8688ca5 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -92,6 +92,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) /* Call back to romstage for board specific changes */ romstage_fsp_rt_buffer_callback(&FspRtBuffer); + post_code(POST_FSP_MEMORY_INIT); FspInitApi(&FspInitParams); /* Should never return. Control will continue from ContinuationFunc */ @@ -321,6 +322,7 @@ static void fsp_after_pci_enum(void *unused) { /* This call needs to be done before resource allocation. */ printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); + post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); FspNotify(EnumInitPhaseAfterPciEnumeration); printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); @@ -334,6 +336,7 @@ static void fsp_finalize(void *unused) { printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); print_fsp_info(); + post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); FspNotify(EnumInitPhaseReadyToBoot); printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index 7f7461e..85a0a8c 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -31,6 +31,8 @@ /* Switch to the stack in RAM */ movl %eax, %esp + post_code(POST_FSP_TEMP_RAM_EXIT) + /* Calculate TempRamExit entry into FSP */ movl fih_car, %ebp mov 0x40(%ebp), %eax diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 7d68f32..35abdb4 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -65,7 +65,7 @@ find_fsp_ret: cmp $CONFIG_FSP_LOC, %eax jbe halt1 - post_code(0x22) + post_code(POST_FSP_TEMP_RAM_INIT) /* Calculate entry into FSP */ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 21239bd..14ad8c6 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -161,8 +161,13 @@ void fsp_notify(u32 phase) fsp_header_ptr->NotifyPhaseEntryOffset); notify_phase_params.Phase = phase; - timestamp_add_now(phase == EnumInitPhaseReadyToBoot ? - TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE); + if (phase == EnumInitPhaseReadyToBoot) { + timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); + post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); + } else { + timestamp_add_now(TS_FSP_BEFORE_FINALIZE); + post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); + } status = notify_phase_proc(&notify_phase_params); diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 50704a8..a19f6ae 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -122,6 +122,7 @@ void raminit(struct romstage_params *params) fsp_memory_init_params.HobListPtr); timestamp_add_now(TS_FSP_MEMORY_INIT_START); + post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); post_code(0x37); timestamp_add_now(TS_FSP_MEMORY_INIT_END); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 15a7cbc..aa1b658 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -137,6 +137,7 @@ static void fsp_run_silicon_init(int is_s3_wakeup) timestamp_add_now(TS_FSP_SILICON_INIT_START); printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n", &silicon_init_params, fsp_silicon_init); + post_code(POST_FSP_SILICON_INIT); status = fsp_silicon_init(&silicon_init_params); timestamp_add_now(TS_FSP_SILICON_INIT_END); printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 44a3ef2..e6d1243 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -203,6 +203,48 @@ #define POST_BS_PAYLOAD_BOOT 0x7b /** + * \brief Before calling FSP TempRamInit + * + * Going to call into FSP binary for TempRamInit phase + */ +#define POST_FSP_TEMP_RAM_INIT 0x90 + +/** + * \brief Before calling FSP TempRamExit + * + * Going to call into FSP binary for TempRamExit phase + */ +#define POST_FSP_TEMP_RAM_EXIT 0x91 + +/** + * \brief Before calling FSP MemoryInit + * + * Going to call into FSP binary for MemoryInit phase + */ +#define POST_FSP_MEMORY_INIT 0x92 + +/** + * \brief Before calling FSP SiliconInit + * + * Going to call into FSP binary for SiliconInit phase + */ +#define POST_FSP_SILICON_INIT 0x93 + +/** + * \brief Before calling FSP Notify before resource allocation + * + * Going to call into FSP binary for Notify phase + */ +#define POST_FSP_NOTIFY_BEFORE_ENUMERATE 0x94 + +/** + * \brief Before calling FSP Notify before finalize + * + * Going to call into FSP binary for Notify phase + */ +#define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 + +/** * \brief Entry into elf boot * * This POST code is called right before invoking jmp_to_elf_entry()

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coreboot-gerrit December 2015