coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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752 discussions

Patch merged into coreboot/master: mainboard/intel/d510mo: Add Intel D510MO mainboard
by gerrit＠coreboot.org 02 Dec '15

02 Dec '15

the following patch was just integrated into master: commit 74d165b18d749bf959f717b37ea67b84066271d6 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon May 4 10:41:21 2015 +1000 mainboard/intel/d510mo: Add Intel D510MO mainboard Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/10074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/10074 for details. -gerrit

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Patch merged into coreboot/master: x86/smm: Initialize SMM on some CPUs one-by-one
by gerrit＠coreboot.org 02 Dec '15

02 Dec '15

the following patch was just integrated into master: commit 149c4c5d0191f1728a66ec986c3eae698cbf87cb Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Nov 28 21:27:05 2015 +1100 x86/smm: Initialize SMM on some CPUs one-by-one We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/6311 Tested-by: build bot (Jenkins) Tested-by: BSI firmware lab <coreboot-labor(a)bsi.bund.de> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/6311 for details. -gerrit

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Patch merged into coreboot/master: northbridge/intel/pineview: Add native raminit
by gerrit＠coreboot.org 02 Dec '15

02 Dec '15

the following patch was just integrated into master: commit 003d15cab43fe34f1916d6f3877f2a6f2b8f6e25 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Nov 20 17:17:51 2015 +1100 northbridge/intel/pineview: Add native raminit Does native ram init for Intel Atom D5xx 8086:a000 northbridge Tested on Intel D510MO mainboard, board boots linux kernel - Works fully with both dimms populated (2x2GB), memtest passes 100% - Almost boots with only one dimm in one of the slots (suspect bad memory map with one dimm?) - Reads garbage with only one dimm in other slot Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/12501 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/12501 for details. -gerrit

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Patch merged into coreboot/master: northbridge/intel/pineview: Add remaining boilerplate code for northbridge
by gerrit＠coreboot.org 02 Dec '15

02 Dec '15

the following patch was just integrated into master: commit f7060f1d0f72bab5b349846bc97784895643cf50 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Nov 14 00:59:21 2015 +1100 northbridge/intel/pineview: Add remaining boilerplate code for northbridge This patch does *not* include native raminit Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/12430 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12430 for details. -gerrit

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Patch set updated for coreboot: drivers/intel/fsp1_1: Don't hide build related options behind HAVE_FSP_BIN
by Stefan Reinauer 02 Dec '15

02 Dec '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12465 -gerrit commit a60f966623330be6531177f8d1261d122bdba838 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Nov 18 15:28:19 2015 -0800 drivers/intel/fsp1_1: Don't hide build related options behind HAVE_FSP_BIN The right thing to do is to hide them behind PLATFORM_USES_FSP1_1. The only things that should depend on HAVE_FSP_BIN is the code that actually adds the file to CBFS, and the path to the file in Kconfig. Removing the HAVE_FSP_BIN check requires some default values for two Kconfig variables. Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/intel/fsp1_1/Kconfig | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 51fa314..692d566 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -40,8 +40,6 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot -if HAVE_FSP_BIN - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0 @@ -62,19 +60,19 @@ config FSP_FILE config FSP_IMAGE_ID_STRING string "8 byte platform string identifying the FSP platform" + default "$XXXFSP$" help 8 ASCII character byte signature string that will help match the FSP binary to a supported hardware configuration. config FSP_LOC hex "Intel FSP Binary location in CBFS" + default 0xffee0000 help The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -endif #HAVE_FSP_BIN - config DISPLAY_FAST_BOOT_DATA bool "Display fast boot data" default n

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New patch to review for coreboot: util/nvramtool: Use correct virtual address when mapping tables
by Timothy Pearson 01 Dec '15

01 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12619 -gerrit commit 98d1ea3aa91f6bf7f78d694922670cf938d1b01b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Dec 1 13:49:59 2015 -0600 util/nvramtool: Use correct virtual address when mapping tables The existing code used a stale pointer from a previously unmapped region of memory when parsing the coreboot tables. Use the correct pointer from the currently mapped memory region when parsing. Change-Id: Id9a1c70655fe25bc079e5bee55f15adf674694f8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/nvramtool/lbtable.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c index 1c7bc0a..5db61c5 100644 --- a/util/nvramtool/lbtable.c +++ b/util/nvramtool/lbtable.c @@ -489,6 +489,9 @@ static const struct lb_header *lbtable_scan(unsigned long start, } map_pages(p, table->table_bytes + sizeof(*table)); + + table = (const struct lb_header *)phystov(p); + /* validate table checksum */ if (table->table_checksum != compute_ip_checksum(((char *)table) + sizeof(*table),

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New patch to review for coreboot: google/lars: Disable eMMC HS400 capability
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12618 -gerrit commit cbe7ff798cf96e821387cc8389857b29b7ddf228 Author: david <david_wu(a)quantatw.com> Date: Tue Nov 24 14:41:35 2015 +0800 google/lars: Disable eMMC HS400 capability BUG=chrome-os-partner:48017 BRANCH=none TEST=Verify eMMC is working fine. Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491 Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7 Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313912 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- src/mainboard/google/lars/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index cb49968..d743921 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -35,7 +35,7 @@ chip soc/intel/skylake register "SmbusEnable" = "1" register "Cio2Enable" = "0" register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "2" register "IshEnable" = "0" register "PttSwitch" = "0"

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New patch to review for coreboot: mediatek/mt8173: Add mtcmos power-on control for audio and display
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12617 -gerrit commit 6b0f68c47c15fddd19fb7cbada604e755032d3ac Author: CC Ma <cc.ma(a)mediatek.com> Date: Fri Jul 31 17:10:59 2015 +0800 mediatek/mt8173: Add mtcmos power-on control for audio and display BRANCH=none BUG=none TEST=none Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0 Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8 Original-Signed-off-by: CC Ma <cc.ma(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292677 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/include/soc/mtcmos.h | 25 +++++++++ src/soc/mediatek/mt8173/mtcmos.c | 76 ++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/src/soc/mediatek/mt8173/include/soc/mtcmos.h b/src/soc/mediatek/mt8173/include/soc/mtcmos.h new file mode 100644 index 0000000..4a27a1b --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mtcmos.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MTCMOS_H__ +#define __SOC_MEDIATEK_MT8173_MTCMOS_H__ + +void mtcmos_audio_power_on(void); +void mtcmos_display_power_on(void); +#endif /* __SOC_MEDIATEK_MT8173_MTCMOS_H__ */ diff --git a/src/soc/mediatek/mt8173/mtcmos.c b/src/soc/mediatek/mt8173/mtcmos.c new file mode 100644 index 0000000..b4edea6 --- /dev/null +++ b/src/soc/mediatek/mt8173/mtcmos.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/mtcmos.h> +#include <soc/spm.h> + +enum { + SRAM_ISOINT_B = 1U << 6, + SRAM_CKISO = 1U << 5, + PWR_CLK_DIS = 1U << 4, + PWR_ON_2ND = 1U << 3, + PWR_ON = 1U << 2, + PWR_ISO = 1U << 1, + PWR_RST_B = 1U << 0 +}; + +enum { + SRAM_PDN = 0xf << 8, + DIS_SRAM_ACK = 0x1 << 12, + AUD_SRAM_ACK = 0xf << 12, +}; + +enum { + DIS_PWR_STA_MASK = 0x1 << 3, + AUD_PWR_STA_MASK = 0x1 << 24, +}; + +static void mtcmos_power_on(u32 *pwr_con, u32 pwr_sta_mask) +{ + write32(&mt8173_spm->poweron_config_set, + (SPM_PROJECT_CODE << 16) | (1U << 0)); + + setbits_le32(pwr_con, PWR_ON); + setbits_le32(pwr_con, PWR_ON_2ND); + + while (!(read32(&mt8173_spm->pwr_status) & pwr_sta_mask) || + !(read32(&mt8173_spm->pwr_status_2nd) & pwr_sta_mask)) + continue; + + clrbits_le32(pwr_con, PWR_CLK_DIS); + clrbits_le32(pwr_con, PWR_ISO); + setbits_le32(pwr_con, PWR_RST_B); + clrbits_le32(pwr_con, SRAM_PDN); +} + +void mtcmos_audio_power_on(void) +{ + mtcmos_power_on(&mt8173_spm->audio_pwr_con, AUD_PWR_STA_MASK); + while (read32(&mt8173_spm->audio_pwr_con) & AUD_SRAM_ACK) + continue; +} + +void mtcmos_display_power_on(void) +{ + mtcmos_power_on(&mt8173_spm->dis_pwr_con, DIS_PWR_STA_MASK); + while (read32(&mt8173_spm->dis_pwr_con) & DIS_SRAM_ACK) + continue; +} +

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New patch to review for coreboot: mediatek/mt8173: Add RTC driver
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12616 -gerrit commit 5c32d84a9170f4a9191053adc55123eeb79e968b Author: Tianping Fang <tianping.fang(a)mediatek.com> Date: Fri Jul 31 17:10:58 2015 +0800 mediatek/mt8173: Add RTC driver BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af Original-Signed-off-by: Tianping Fang <tianping.fang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292676 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Makefile.inc | 2 +- src/soc/mediatek/mt8173/bootblock.c | 3 + src/soc/mediatek/mt8173/include/soc/rtc.h | 188 +++++++++++++++++ src/soc/mediatek/mt8173/rtc.c | 321 ++++++++++++++++++++++++++++++ 4 files changed, 513 insertions(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b14ebcc..a5b3875 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -30,7 +30,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c -bootblock-y += wdt.c +bootblock-y += wdt.c rtc.c bootblock-y += mmu_operations.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index cd951a8..103602f 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -21,6 +21,7 @@ #include <soc/mmu_operations.h> #include <soc/mt6391.h> #include <soc/pll.h> +#include <soc/rtc.h> #include <soc/wdt.h> void bootblock_soc_init(void) @@ -37,4 +38,6 @@ void bootblock_soc_init(void) /* init watch dog, will disable AP watch dog */ mtk_wdt_init(); + + rtc_boot(); } diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h new file mode 100644 index 0000000..5ae6e04 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/rtc.h @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOC_MEDIATEK_MT8173_RTC_H +#define SOC_MEDIATEK_MT8173_RTC_H + +#include <stdint.h> +#include "mt6391.h" + +/* + * Default values for RTC initialization + * Year (YEA) : 1970 ~ 2037 + * Month (MTH) : 1 ~ 12 + * Day of Month (DOM): 1 ~ 31 + */ + +enum { + RTC_DEFAULT_YEA = 2010, + RTC_DEFAULT_MTH = 1, + RTC_DEFAULT_DOM = 1, + RTC_DEFAULT_DOW = 5 +}; + +enum { + RTC_2SEC_REBOOT_ENABLE = 1, + RTC_2SEC_MODE = 2 +}; + +/* RTC registers */ +enum { + RTC_BBPU = 0xE000, + RTC_IRQ_STA = 0xE002, + RTC_IRQ_EN = 0xE004, + RTC_CII_EN = 0xE006 +}; + +enum { + RTC_TC_SEC = 0xE00A, + RTC_TC_MIN = 0xE00C, + RTC_TC_HOU = 0xE00E, + RTC_TC_DOM = 0xE010, + RTC_TC_DOW = 0xE012, + RTC_TC_MTH = 0xE014, + RTC_TC_YEA = 0xE016 +}; + +enum { + RTC_AL_SEC = 0xE018, + RTC_AL_MIN = 0xE01A, + RTC_AL_HOU = 0xE01C, + RTC_AL_DOM = 0xE01E, + RTC_AL_DOW = 0xE020, + RTC_AL_MTH = 0xE022, + RTC_AL_YEA = 0xE024, + RTC_AL_MASK = 0xE008 +}; + +enum { + RTC_OSC32CON = 0xE026, + RTC_CON = 0xE03E, + RTC_WRTGR = 0xE03C +}; + +enum { + RTC_POWERKEY1 = 0xE028, + RTC_POWERKEY2 = 0xE02A +}; + +enum { + RTC_PDN1 = 0xE02C, + RTC_PDN2 = 0xE02E, + RTC_SPAR0 = 0xE030, + RTC_SPAR1 = 0xE032, + RTC_PROT = 0xE036, + RTC_DIFF = 0xE038, + RTC_CALI = 0xE03A +}; + +enum { + RTC_OSC32CON_UNLOCK1 = 0x1A57, + RTC_OSC32CON_UNLOCK2 = 0x2B68 +}; + +enum { + RTC_PROT_UNLOCK1 = 0x586A, + RTC_PROT_UNLOCK2 = 0x9136 +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_BBPU = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + + RTC_CBUSY_TIMEOUT_US = 800 +}; + +enum { + RTC_BBPU_KEY = 0x43 << 8 +}; + +enum { + RTC_IRQ_STA_AL = 1U << 0, + RTC_IRQ_STA_TC = 1U << 1, + RTC_IRQ_STA_LP = 1U << 3 +}; + +enum { + RTC_IRQ_EN_AL = 1U << 0, + RTC_IRQ_EN_TC = 1U << 1, + RTC_IRQ_EN_ONESHOT = 1U << 2, + RTC_IRQ_EN_LP = 1U << 3, + RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL +}; + +enum { + RTC_OSC32CON_AMPEN = 1U << 8, + RTC_OSC32CON_LNBUFEN = 1U << 11 +}; + +enum { + RTC_POWERKEY1_KEY = 0xa357, + RTC_POWERKEY2_KEY = 0x67d2 +}; + +enum { + RTC_CON_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15 +}; + +enum { + RTC_CALI_BBPU_2SEC_EN = 1U << 8, + RTC_CALI_BBPU_2SEC_MODE_SHIFT = 9, + RTC_CALI_BBPU_2SEC_MODE_MSK = 3U << RTC_CALI_BBPU_2SEC_MODE_SHIFT, + RTC_CALI_BBPU_2SEC_STAT = 1U << 11 +}; + +enum { + RTC_SPAR0_32K_LESS = 1U << 6 +}; + +enum { + RTC_MIN_YEAR = 1968, + RTC_BASE_YEAR = 1900, + RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR, + + RTC_NUM_YEARS = 128 +}; + +enum { + RTC_STATE_REBOOT = 0, + RTC_STATE_RECOVER = 1, + RTC_STATE_INIT = 2 +}; + +void rtc_boot(void); + +#endif /* SOC_MEDIATEK_MT8173_RTC_H */ diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c new file mode 100644 index 0000000..b50a61c --- /dev/null +++ b/src/soc/mediatek/mt8173/rtc.c @@ -0,0 +1,321 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <bcd.h> +#include <console/console.h> +#include <delay.h> +#include <rtc.h> +#include <timer.h> + +#include <soc/mt6391.h> +#include <soc/pmic_wrap.h> +#include <soc/rtc.h> + +#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) + +/* ensure rtc write success */ +static inline int rtc_busy_wait(void) +{ + struct stopwatch sw; + u16 bbpu; + + stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US); + + do { + pwrap_read(RTC_BBPU, &bbpu); + /* Time > 1sec, time out and set recovery mode enable.*/ + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n"); + return 0; + } + } while (bbpu & RTC_BBPU_CBUSY); + + return 1; +} + +static int write_trigger(void) +{ + pwrap_write(RTC_WRTGR, 1); + return rtc_busy_wait(); +} + +/* unlock rtc write interface */ +static int writeif_unlock(void) +{ + pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1); + if (!write_trigger()) + return 0; + pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2); + if (!write_trigger()) + return 0; + + return 1; +} + +/* set rtc time */ +int rtc_set(const struct rtc_time *time) +{ + return -1; +} + +/* get rtc time */ +int rtc_get(struct rtc_time *time) +{ + u16 value; + + pwrap_read(RTC_TC_SEC, &value); + time->sec = value; + pwrap_read(RTC_TC_MIN, &value); + time->min = value; + pwrap_read(RTC_TC_HOU, &value); + time->hour = value; + pwrap_read(RTC_TC_DOM, &value); + time->mday = value; + pwrap_read(RTC_TC_MTH, &value); + time->mon = value; + pwrap_read(RTC_TC_YEA, &value); + time->year = (value + RTC_MIN_YEAR_OFFSET) % 100; + + return 0; +} + +/* set rtc xosc setting */ +static void rtc_xosc_write(u16 val) +{ + pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1); + udelay(200); + pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2); + udelay(200); + + pwrap_write(RTC_OSC32CON, val); + udelay(200); + mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0); + write_trigger(); +} + +/* initialize rtc related registers */ +static int rtc_reg_init(void) +{ + u16 irqsta; + + pwrap_write(RTC_IRQ_EN, 0); + pwrap_write(RTC_CII_EN, 0); + pwrap_write(RTC_AL_MASK, 0); + pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR); + pwrap_write(RTC_AL_MTH, 1); + pwrap_write(RTC_AL_DOM, 1); + pwrap_write(RTC_AL_DOW, 4); + pwrap_write(RTC_AL_HOU, 0); + pwrap_write(RTC_AL_MIN, 0); + pwrap_write(RTC_AL_SEC, 0); + + pwrap_write(RTC_DIFF, 0); + pwrap_write(RTC_CALI, 0); + if (!write_trigger()) + return 0; + + pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */ + + /* init time counters after resetting RTC_DIFF and RTC_CALI */ + pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR); + pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH); + pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM); + pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW); + pwrap_write(RTC_TC_HOU, 0); + pwrap_write(RTC_TC_MIN, 0); + pwrap_write(RTC_TC_SEC, 0); + + return write_trigger(); +} + +/* initialize rtc related gpio */ +static int rtc_gpio_init(void) +{ + u16 con; + + mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE, + MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */ + + /* Export 32K clock RTC_32K2V8 */ + pwrap_read(RTC_CON, &con); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN); + con |= (RTC_CON_GPEN | RTC_CON_GOE); + con &= ~(RTC_CON_F32KOB); + pwrap_write(RTC_CON, con); + return write_trigger(); +} + +/* set xosc mode */ +static void rtc_osc_init(void) +{ + u16 con; + + /* enable 32K export */ + rtc_gpio_init(); + + pwrap_write(PMIC_RG_TOP_CKTST2, 0x0); + pwrap_read(RTC_OSC32CON, &con); + if ((con & 0x1f) != 0x0) /* check XOSCCALI */ + rtc_xosc_write(0x3); +} + +/* low power detect setting */ +static int rtc_lpd_init(void) +{ + mt6391_write(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0); + if (!write_trigger()) + return 0; + + mt6391_write(RTC_CON, RTC_CON_LPRST, 0, 0); + if (!write_trigger()) + return 0; + + mt6391_write(RTC_CON, 0, RTC_CON_LPRST, 0); + if (!write_trigger()) + return 0; + + return 1; +} + +/* rtc init check */ +static int rtc_init(u8 recover) +{ + printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover); + + if (!writeif_unlock()) + return 0; + + if (!rtc_gpio_init()) + return 0; + + /* Use SW to detect 32K mode instead of HW */ + if (recover) + mt6391_write(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9); + + rtc_xosc_write(0x3); + + if (recover) + mdelay(1000); + + /* write powerkeys */ + pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + if (!write_trigger()) + return 0; + + if (recover) + mt6391_write(PMIC_RG_CHRSTATUS, 0, 0x4, 9); + + rtc_xosc_write(0); + + if (!rtc_reg_init()) + return 0; + if (!rtc_lpd_init()) + return 0; + + return 1; +} + +/* enable rtc bbpu */ +static void rtc_bbpu_power_on(void) +{ + u16 bbpu; + int ret; + + /* pull PWRBB high */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN; + pwrap_write(RTC_BBPU, bbpu); + ret = write_trigger(); + printk(BIOS_INFO, "[RTC] %s write_trigger=%d\n", __func__, ret); + + /* enable DCXO to transform external 32KHz clock to 26MHz clock + directly sent to SoC */ + mt6391_write(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0); + mt6391_write(PMIC_RG_DCXO_POR2_CON3, + BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0); + mt6391_write(PMIC_RG_DCXO_CON2, + BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0); + + pwrap_read(RTC_BBPU, &bbpu); + printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu); + + /* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */ + mt6391_write(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14); +} + +static u8 rtc_check_state(void) +{ + u16 con; + u16 pwrky1; + u16 pwrky2; + + pwrap_read(RTC_CON, &con); + pwrap_read(RTC_POWERKEY1, &pwrky1); + pwrap_read(RTC_POWERKEY2, &pwrky2); + + if (con & RTC_CON_LPSTA_RAW) + return RTC_STATE_INIT; + + if (!rtc_busy_wait()) + return RTC_STATE_RECOVER; + + if (!writeif_unlock()) + return RTC_STATE_RECOVER; + + if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY) + return RTC_STATE_INIT; + else + return RTC_STATE_REBOOT; +} + +/* the rtc boot flow entry */ +void rtc_boot(void) +{ + u16 bbpu; + u16 con; + u16 irqsta; + + pwrap_write(PMIC_RG_TOP_CKPDN, 0); + pwrap_write(PMIC_RG_TOP_CKPDN2, 0); + + switch (rtc_check_state()) { + case RTC_STATE_REBOOT: + mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0); + write_trigger(); + rtc_osc_init(); + break; + case RTC_STATE_RECOVER: + rtc_init(1); + break; + case RTC_STATE_INIT: + default: + if (!rtc_init(0)) + rtc_init(1); + break; + } + + pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */ + pwrap_read(RTC_BBPU, &bbpu); + pwrap_read(RTC_CON, &con); + + printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta); + printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con); + rtc_bbpu_power_on(); +}

1 0

New patch to review for coreboot: mediatek/mt8173: Add I2C driver
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12615 -gerrit commit 7e5a855db188143203836f7b0b3258a8e83c0b5d Author: Liguo Zhang <liguo.zhang(a)mediatek.com> Date: Fri Jul 31 17:10:51 2015 +0800 mediatek/mt8173: Add I2C driver BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: If2cac5aecc5675048e0e2d28897b1a82e099de7d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2a3d867fd1e547cadc6c947f38082fddc2265d32 Original-Change-Id: I4f3a9b403b949d8ae8e3c393cc9441fb66ea5f1d Original-Signed-off-by: liguo.zhang <liguo.zhang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292667 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 1 - src/soc/mediatek/mt8173/Makefile.inc | 1 + src/soc/mediatek/mt8173/i2c.c | 333 ++++++++++++++++++++++++++++++ src/soc/mediatek/mt8173/include/soc/i2c.h | 134 ++++++++++++ 4 files changed, 468 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 640fe24..4fcb574 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS select VIRTUAL_DEV_SWITCH - select VBOOT2_MOCK_SECDATA config MAINBOARD_DIR string diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index e29154b..b14ebcc 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -35,6 +35,7 @@ bootblock-y += mmu_operations.c ################################################################################ +verstage-y += i2c.c verstage-y += spi.c verstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c new file mode 100644 index 0000000..6e383d4 --- /dev/null +++ b/src/soc/mediatek/mt8173/i2c.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <delay.h> +#include <device/i2c.h> +#include <string.h> +#include <symbols.h> +#include <timer.h> +#include <arch/io.h> +#include <soc/addressmap.h> +#include <soc/i2c.h> +#include <soc/pll.h> + +#define I2C_CLK_HZ (AXI_HZ / 16) + +static struct mtk_i2c i2c[7] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)I2C_BASE, + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x1000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x100), + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x180), + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x9000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200), + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xa000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x280), + }, + + /* i2c5 is reserved for internal use. */ + { + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xc000), + .i2c_dma_regs = (void *)I2C_DMA_BASE, + } +}; + +#define I2CTAG "[I2C][PL] " + +#if CONFIG_DEBUG_I2C +#define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) +#else +#define I2CLOG(fmt, arg...) +#endif /* CONFIG_DEBUG_I2C */ + +#define I2CERR(fmt, arg...) printk(BIOS_ERR, I2CTAG fmt, ##arg) + +static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs) +{ + write32(&dma_regs->dma_rst, 0x1); + udelay(50); + write32(&dma_regs->dma_rst, 0x2); + udelay(50); + write32(&dma_regs->dma_rst, 0x0); + udelay(50); +} + +static inline void mtk_i2c_dump_info(uint8_t bus) +{ + struct mt8173_i2c_regs *regs; + + regs = i2c[bus].i2c_regs; + + I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n" + "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n" + "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n" + "DEBUGSTAT %x\nEXT_CONF %x\n", + (read32(&regs->salve_addr)), + (read32(&regs->intr_mask)), + (read32(&regs->intr_stat)), + (read32(&regs->control)), + (read32(&regs->transfer_len)), + (read32(&regs->transac_len)), + (read32(&regs->delay_len)), + (read32(&regs->timing)), + (read32(&regs->start)), + (read32(&regs->fifo_stat)), + (read32(&regs->io_config)), + (read32(&regs->hs)), + (read32(&regs->debug_stat)), + (read32(&regs->ext_conf))); + + I2CLOG("addr address %x\n", (uint32_t)regs); +} + +static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_seg *seg, + enum i2c_modes read) +{ + uint32_t ret_code = I2C_OK; + uint16_t status; + uint32_t time_out_val = 0; + uint8_t addr; + uint32_t write_len = 0; + uint32_t read_len = 0; + uint8_t *write_buffer = NULL; + uint8_t *read_buffer = NULL; + uint8_t sample_div; + uint8_t step_div; + uint32_t i2c_freq; + struct mt8173_i2c_regs *regs; + struct mt8173_i2c_dma_regs *dma_regs; + struct stopwatch sw; + + regs = i2c[bus].i2c_regs; + dma_regs = i2c[bus].i2c_dma_regs; + + addr = seg[0].chip; + + switch (read) { + case I2C_WRITE_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + write_len = seg[0].len; + write_buffer = seg[0].buf; + break; + + case I2C_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + read_len = seg[0].len; + read_buffer = seg[0].buf; + break; + + /* Must use special write-then-read mode for repeated starts. */ + case I2C_WRITE_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + assert(seg[1].len > 0 && seg[1].len <= 255); + write_len = seg[0].len; + read_len = seg[1].len; + write_buffer = seg[0].buf; + read_buffer = seg[1].buf; + break; + } + + /* Calculate i2c frequency */ + sample_div = 1; + step_div = div_round_up(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); + assert(sample_div < 8 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz); + write32(&regs->timing, (sample_div - 1) << 8 | (step_div - 1)); + + /* Clear interrupt status */ + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + write32(&regs->fifo_addr_clr, 0x1); + + /* Enable interrupt */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + switch (read) { + case I2C_WRITE_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, write_len); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + break; + + case I2C_READ_MODE: + /* control registers */ + write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, read_len); + + /* set i2c read slave address*/ + write32(&regs->slave_addr, (addr << 1 | 0x1)); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + + case I2C_WRITE_READ_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, DIR_CHG | ACK_ERR_DET_EN | DMA_EN | + CLK_EXT | REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transfer_len, write_len); + write32(&regs->transfer_aux_len, read_len); + write32(&regs->transac_len, 2); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + } + + write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_en, I2C_DMA_START_EN); + + /* start transfer transaction */ + write32(&regs->start, 0x1); + + stopwatch_init_msecs_expire(&sw, 100); + + /* polling mode : see if transaction complete */ + while (1) { + status = read32(&regs->intr_stat); + if (status & I2C_HS_NACKERR) { + ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + I2CERR("[i2c%d transfer] transaction NACK error\n", + bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_ACKERR) { + ret_code = I2C_TRANSFER_FAIL_ACKERR; + I2CERR("[i2c%d transfer] transaction ACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_TRANSAC_COMP) { + ret_code = I2C_OK; + memcpy(read_buffer, _dma_coherent, read_len); + break; + } + + if (stopwatch_expired(&sw)) { + ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + I2CERR("[i2c%d transfer] transaction timeout:%d\n", bus, + time_out_val); + mtk_i2c_dump_info(bus); + break; + } + } + + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + /* clear bit mask */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + /* reset the i2c controller for next i2c transfer. */ + write32(&regs->softreset, 0x1); + + i2c_dma_reset(dma_regs); + + return ret_code; +} + +static uint8_t mtk_i2c_should_combine(struct i2c_seg *seg, int left_count) +{ + if (left_count >= 2 && seg[0].read == 0 && seg[1].read == 1 && + seg[0].chip == seg[1].chip) + return 1; + else + return 0; +} + +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) +{ + int ret = 0; + int i; + int read; + + for (i = 0; i < seg_count; i++) { + if (mtk_i2c_should_combine(&segments[i], seg_count - i)) + read = I2C_WRITE_READ_MODE; + else + read = segments[i].read; + + ret = mtk_i2c_transfer(bus, &segments[i], read); + + if (ret) + break; + + if (read == I2C_WRITE_READ_MODE) + i++; + } + + return ret; +} diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h new file mode 100644 index 0000000..295a9aa --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOC_MEDIATEK_MT8173_I2C_H +#define SOC_MEDIATEK_MT8173_I2C_H + +#include <stddef.h> + +/* I2C Configuration */ +enum { + I2C_HS_DEFAULT_VALUE = 0x0102, +}; + +enum i2c_modes { + I2C_WRITE_MODE = 0, + I2C_READ_MODE = 1, + I2C_WRITE_READ_MODE = 2, +}; + +enum { + I2C_DMA_CON_TX = 0x0, + I2C_DMA_CON_RX = 0x1, + I2C_DMA_START_EN = 0x1, + I2C_DMA_INT_FLAG_NONE = 0x0, + I2C_DMA_CLR_FLAG = 0x0, + I2C_DMA_FLUSH_FLAG = 0x1, +}; + +/* I2C DMA Registers */ +struct mt8173_i2c_dma_regs { + uint32_t dma_int_flag; + uint32_t dma_int_en; + uint32_t dma_en; + uint32_t dma_rst; + uint32_t reserved1; + uint32_t dma_flush; + uint32_t dma_con; + uint32_t dma_tx_mem_addr; + uint32_t dma_rx_mem_addr; + uint32_t dma_tx_len; + uint32_t dma_rx_len; +}; + +check_member(mt8173_i2c_dma_regs, dma_tx_len, 0x24); + +/* I2C Register */ +struct mt8173_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t reserved1; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t fifo_addr_clr; + uint32_t reserved2; + uint32_t io_config; + uint32_t debug; + uint32_t hs; + uint32_t reserved3; + uint32_t softreset; + uint32_t dcm; + uint32_t reserved4[3]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t transfer_aux_len; +}; + +check_member(mt8173_i2c_regs, debug_stat, 0x64); + +struct mtk_i2c { + struct mt8173_i2c_regs *i2c_regs; + struct mt8173_i2c_dma_regs *i2c_dma_regs; +}; + +enum { + I2C_TRANS_LEN_MASK = (0xff), + I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), + I2C_CONTROL_MASK = (0x3f << 1) +}; + +/* Register mask */ +enum { + I2C_HS_NACKERR = (1 << 2), + I2C_ACKERR = (1 << 1), + I2C_TRANSAC_COMP = (1 << 0), +}; + +/* i2c control bits */ +enum { + ACK_ERR_DET_EN = (1 << 5), + DIR_CHG = (1 << 4), + CLK_EXT = (1 << 3), + DMA_EN = (1 << 2), + REPEATED_START_FLAG = (1 << 1), + STOP_FLAG = (0 << 1) +}; + +/* I2C Status Code */ + +enum { + I2C_OK = 0x0000, + I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, + I2C_TRANSFER_INVALID_LENGTH = 0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, + I2C_TRANSFER_FAIL_ACKERR = 0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 +}; + +#endif /* SOC_MEDIATEK_MT8173_I2C_H */

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coreboot-gerrit December 2015