coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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752 discussions

New patch to review for coreboot: google/oak: Add MMU support
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12614 -gerrit commit f32f60cd74ebb070d726b54cf58a39d1e2850007 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Fri Jul 31 17:10:50 2015 +0800 google/oak: Add MMU support BRANCH=none BUG=none TEST=build pass Change-Id: Ib46b243102969e2860479070e19640fb6cb9bdd6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3ee2a20ec56359e917bb8f4825846c54d4f6276a Original-Change-Id: Iedc81a85569b00524620e9ba128e7d77f17b0405 Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292666 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/romstage.c | 5 ++ src/soc/mediatek/mt8173/Makefile.inc | 2 + src/soc/mediatek/mt8173/bootblock.c | 3 + .../mediatek/mt8173/include/soc/mmu_operations.h | 39 ++++++++++++ src/soc/mediatek/mt8173/mmu_operations.c | 72 ++++++++++++++++++++++ 5 files changed, 121 insertions(+) diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index ce736e4..354e876 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -20,6 +20,7 @@ #include <arch/cpu.h> #include <arch/exception.h> #include <arch/io.h> +#include <arch/mmu.h> #include <cbfs.h> #include <console/console.h> @@ -29,6 +30,8 @@ #include <symbols.h> #include <timestamp.h> +#include <soc/mmu_operations.h> + void main(void) { timestamp_add_now(TS_START_ROMSTAGE); @@ -37,5 +40,7 @@ void main(void) console_init(); exception_init(); + mt8173_mmu_after_dram(); + run_ramstage(); } diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 4321989..e29154b 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -31,6 +31,7 @@ endif bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += wdt.c +bootblock-y += mmu_operations.c ################################################################################ @@ -51,6 +52,7 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c romstage-y += spi.c romstage-y += gpio.c +romstage-y += mmu_operations.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index b284dd0..cd951a8 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -18,6 +18,7 @@ */ #include <bootblock_common.h> +#include <soc/mmu_operations.h> #include <soc/mt6391.h> #include <soc/pll.h> #include <soc/wdt.h> @@ -32,6 +33,8 @@ void bootblock_soc_init(void) /* post init pll */ mt_pll_post_init(); + mt8173_mmu_init(); + /* init watch dog, will disable AP watch dog */ mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/mmu_operations.h b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h new file mode 100644 index 0000000..82393f9 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mmu_operations.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ +#define __SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ + +#include <arch/mmu.h> + +enum { + DEV_MEM = MA_DEV | MA_S | MA_RW, + CACHED_MEM = MA_MEM | MA_NS | MA_RW, + SECURE_MEM = MA_MEM | MA_S | MA_RW, + UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, +}; + +extern unsigned char _sram_l2c[]; +extern unsigned char _esram_l2c[]; +#define _sram_l2c_size (_esram_l2c - _sram_l2c) + +void mt8173_mmu_init(void); +void mt8173_mmu_after_dram(void); + +#endif //__SOC_MEDIATEK_MT8173_MMU_OPERATIONS_H__ diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c new file mode 100644 index 0000000..5d3a8d8 --- /dev/null +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/mmu.h> +#include <console/console.h> +#include <symbols.h> +#include <stdlib.h> +#include <stdint.h> +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> + +static const uint64_t dram_size = (uint64_t)CONFIG_DRAM_SIZE_MB * MiB; + +void mt8173_mmu_init(void) +{ + mmu_init(); + + /* Set 0x0 to end of dram as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + dram_size, DEV_MEM); + + /* SRAM is cached */ + mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); + + /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ + mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + + /* set ttb as secure */ + mmu_config_range(_ttb, _ttb_size, SECURE_MEM); + + mmu_enable(); +} + +void mt8173_mmu_after_dram(void) +{ + /* Remap DRAM as cached now that it's up and running */ + mmu_config_range(_dram, dram_size, CACHED_MEM); + + /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ + /* TODO: Implement true unmapping, and also use it for the zero-page! */ + mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM); + + /* Careful: changing cache geometry while it's active is a bad idea! */ + mmu_disable(); + + /* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max + * available L2 cache for A53 in MT8173. */ + write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8); + /* turn off the l2c sram clock */ + write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN); + + /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + mmu_enable(); +}

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New patch to review for coreboot: mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock code
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12613 -gerrit commit 2b3539bd65fe81249c08c0ffdaca0577a647ef5f Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Jul 31 17:10:48 2015 +0800 mediatek/mt8173: Add gen-bl-img.py for mt8173 bootblock code BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3 Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292664 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Makefile.inc | 4 ++ util/mtkheader/gen-bl-img.py | 95 ++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 53dc9ff..4321989 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -65,6 +65,10 @@ ramstage-y += wdt.c ################################################################################ +# Generate the actual coreboot bootblock code +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8173 sf $< $@ + CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include endif diff --git a/util/mtkheader/gen-bl-img.py b/util/mtkheader/gen-bl-img.py new file mode 100755 index 0000000..700ebe0 --- /dev/null +++ b/util/mtkheader/gen-bl-img.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python + +# +# This file is part of the coreboot project. +# +# Copyright (c) 2015 MediaTek Inc. +# Author: Tristan Shieh <tristan.shieh(a)mediatek.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +import struct +import sys +import hashlib + +def read(path): + with open(path, "rb") as f: + return f.read() + +def write(path, data): + with open(path, "wb") as f: + f.write(data) + +def padding(data, size, pattern = '\0'): + return data + pattern * (size - len(data)) + +def align(data, size, pattern = '\0'): + return padding(data, (len(data) + (size - 1)) & ~(size - 1), pattern) + +gfh_infos = { + 'mt8173': struct.pack("44I", + 0x014d4d4d, 0x00000038, 0x454c4946, 0x464e495f, + 0x0000004f, 0x00000001, 0x01050001, 0x000C0f50, + 0xffffffff, 0x00020000, 0x000000a8, 0x00000020, + 0x000000B0, 0x00000001, 0x014d4d4d, 0x0001000c, + 0x00000001, 0x034d4d4d, 0x00070064, 0x00001182, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00006400, 0x00001388, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + )} + +def gen_emmc_header(data): + header = (padding(struct.pack("<12sII", "EMMC_BOOT", 1, 512), 512, '\xff') + + padding(struct.pack("<8sIIIIIIII", "BRLYT", 1, 2048, 2048 + len(data), + 0x42424242, 0x00010005, 2048, 2048 + len(data), 1) + '\0' * 140, 512, '\xff') + + '\0' * 1024) + return header + +def gen_sf_header(data): + header = (padding(struct.pack("<12sII", "SF_BOOT", 1, 512), 512, '\xff') + + padding(struct.pack("<8sIIIIIIII", "BRLYT", 1, 2048, 2048 + len(data), + 0x42424242, 0x00010007, 2048, 2048 + len(data), 1) + '\0' * 140, 512, '\xff') + + '\0' * 1024) + return header + +gen_dev_header = { + "emmc": gen_emmc_header, + "sf": gen_sf_header +} + +def gen_preloader(chip_ver, flash_type, data): + gfh_info = gfh_infos[chip_ver] + gfh_info = gfh_info[0:32] + struct.pack("1I", len(data)+len(gfh_info)+32) + gfh_info[36:len(gfh_info)] + + gfh_hash = hashlib.sha256(gfh_info + data).digest() + + data = align(gfh_info + data + gfh_hash, 512, '\xff') + header = gen_dev_header[flash_type](data) + return header + data + +def main(argv): + if len(argv) != 5: + print "Usage: %s <chip> <flash_type> <input_file> <output_file>" % argv[0] + print "\t flash_type: emmc/sf" + print "\t chip : mt8173" + + exit(1) + write(argv[4], gen_preloader(argv[1], argv[2], read(argv[3]))) + +if __name__ == "__main__": + main(sys.argv)

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New patch to review for coreboot: google/oak: Add support for verstage
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12612 -gerrit commit 6a33e8e2c45506a29aa2e71868bd529dd28df5ed Author: Itamar <itamar.gold(a)mediatek.com> Date: Fri Jul 31 17:10:46 2015 +0800 google/oak: Add support for verstage Add support for vertage and add watchdog driver for hard reset. BRANCH=none BUG=none TEST=build pass and can boot to kernel with vboot2 enabled Change-Id: I578a69a1e43aad8c90c3914efd09d556920f728e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 + src/mainboard/google/oak/Kconfig | 14 +++++++ src/mainboard/google/oak/Makefile.inc | 3 ++ src/soc/mediatek/mt8173/Kconfig | 1 + src/soc/mediatek/mt8173/Makefile.inc | 12 ++++++ src/soc/mediatek/mt8173/bootblock.c | 4 ++ src/soc/mediatek/mt8173/include/soc/wdt.h | 58 ++++++++++++++++++++++++++ src/soc/mediatek/mt8173/wdt.c | 68 +++++++++++++++++++++++++++++++ 8 files changed, 162 insertions(+) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 1cbc9a4..b527f3a 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -76,6 +76,8 @@ verstage-y += ../../lib/memset.c verstage-y += ../../lib/memcpy.c verstage-y += ../../lib/memmove.c +verstage-y += transition.c transition_asm.S + endif # CONFIG_ARCH_VERSTAGE_ARM64 ################################################################################ diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index e45fb4c..640fe24 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -29,7 +29,9 @@ config BOARD_SPECIFIC_OPTIONS select EC_SOFTWARE_SYNC select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS select VIRTUAL_DEV_SWITCH + select VBOOT2_MOCK_SECDATA config MAINBOARD_DIR string @@ -47,4 +49,16 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0 +config DRIVER_TPM_I2C_BUS + hex + default 0x2 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index dca67db..dd6abf0 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -22,6 +22,9 @@ bootblock-y += memlayout.ld bootblock-y += chromeos.c bootblock-y += boardid.c +verstage-y += chromeos.c +verstage-y += memlayout.ld + romstage-y += chromeos.c romstage-y += romstage.c romstage-y += memlayout.ld diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 6f23eba..f781aef 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8173 select GENERIC_UDELAY select HAS_PRECBMEM_TIMESTAMP_REGION select GENERIC_GPIO_LIB + select HAVE_HARD_RESET if SOC_MEDIATEK_MT8173 diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 563caf4..53dc9ff 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -30,6 +30,17 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c +bootblock-y += wdt.c + +################################################################################ + +verstage-y += spi.c + +verstage-$(CONFIG_DRIVERS_UART) += uart.c + +verstage-y += timer.c +verstage-y += wdt.c +verstage-y += cbfs.c ################################################################################ @@ -50,6 +61,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += gpio.c +ramstage-y += wdt.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index ef09cae..b284dd0 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -20,6 +20,7 @@ #include <bootblock_common.h> #include <soc/mt6391.h> #include <soc/pll.h> +#include <soc/wdt.h> void bootblock_soc_init(void) { @@ -30,4 +31,7 @@ void bootblock_soc_init(void) /* post init pll */ mt_pll_post_init(); + + /* init watch dog, will disable AP watch dog */ + mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/wdt.h b/src/soc/mediatek/mt8173/include/soc/wdt.h new file mode 100644 index 0000000..b7b7ba4 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/wdt.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOC_MEDIATEK_MT8173_WDT_H +#define SOC_MEDIATEK_MT8173_WDT_H + +#include <stdint.h> + +struct mt8173_wdt_regs { + u32 wdt_mode; + u32 wdt_length; + u32 wdt_restart; + u32 wdt_status; + u32 wdt_interval; + u32 wdt_swrst; + u32 wdt_swsysrst; + u32 reserved[9]; + u32 wdt_debug_ctrl; +}; + +/* WDT_MODE */ +enum { + MTK_WDT_MODE_KEY = 0x22000000, + MTK_WDT_MODE_DUAL_MODE = 1 << 6, + MTK_WDT_MODE_IRQ = 1 << 3, + MTK_WDT_MODE_EXTEN = 1 << 2, + MTK_WDT_MODE_EXT_POL = 1 << 1, + MTK_WDT_MODE_ENABLE = 1 << 0 +}; + +/* WDT_RESET */ +enum { + MTK_WDT_SWRST_KEY = 0x1209, + MTK_WDT_STA_SPM_RST = 1 << 1, + MTK_WDT_STA_SW_RST = 1 << 30, + MTK_WDT_STA_HW_RST = 1 << 31 +}; + +int mtk_wdt_init(void); + +#endif /* SOC_MEDIATEK_MT8173_WDT_H */ + diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c new file mode 100644 index 0000000..2d725b1 --- /dev/null +++ b/src/soc/mediatek/mt8173/wdt.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <reset.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE; + +int mtk_wdt_init(void) +{ + uint32_t wdt_sta; + + /* Write Mode register will clear status register */ + wdt_sta = read32(&mt8173_wdt->wdt_status); + + printk(BIOS_INFO, "WDT: Last reset was "); + if (wdt_sta & MTK_WDT_STA_HW_RST) + printk(BIOS_INFO, "hardware watchdog\n"); + else if (wdt_sta & MTK_WDT_STA_SW_RST) + printk(BIOS_INFO, "normal software reboot\n"); + else if (wdt_sta & MTK_WDT_STA_SPM_RST) + printk(BIOS_INFO, "SPM reboot\n"); + else if (!wdt_sta) + printk(BIOS_INFO, "cold boot\n"); + else + printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta); + + /* Config watchdog reboot mode: + * Clearing bits: + * DUAL_MODE & IRQ: trigger reset instead of irq then reset. + * EXT_POL: select watchdog output signal as active low. + * ENABLE: disable watchdog on initialization. + * Setting bit EXTEN to enable watchdog output. + */ + clrsetbits_le32(&mt8173_wdt->wdt_mode, + MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | + MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, + MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + + return wdt_sta; +} + +void hard_reset(void) +{ + write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + while (1) + ; +}

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New patch to review for coreboot: mediatek/mt8173: Add SPI support
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12611 -gerrit commit 187bea5ebdb70249821167fe1ec1d6e12bfc9bce Author: Leilk Liu <leilk.liu(a)mediatek.com> Date: Fri Jul 31 17:10:46 2015 +0800 mediatek/mt8173: Add SPI support BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I82d982b40dd0bfaa7770a6b08c70b20337a46955 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 41acc14e9fe54924d20e4e5a2d1519251f0e1c87 Original-Change-Id: I2559be4191da9af523944563729171bd92a86cd0 Original-Signed-off-by: Leilk Liu <leilk.liu(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292661 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/bootblock.c | 3 + src/soc/mediatek/mt8173/Makefile.inc | 3 + src/soc/mediatek/mt8173/include/soc/spi.h | 113 +++++++++++ src/soc/mediatek/mt8173/spi.c | 306 ++++++++++++++++++++++++++++++ 4 files changed, 425 insertions(+) diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 54301e4..3b0492b 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -25,6 +25,7 @@ #include <soc/mt6391.h> #include <soc/pericfg.h> #include <soc/pinmux.h> +#include <soc/spi.h> #include "gpio.h" @@ -50,6 +51,8 @@ void bootblock_mainboard_init(void) /* set i2c related gpio */ i2c_set_gpio_pinmux(); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); + setup_chromeos_gpios(); if (board_id() < 4) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index a18d8a8..563caf4 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -22,6 +22,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c bootblock-y += cbfs.c bootblock-y += pll.c +bootblock-y += spi.c bootblock-y += timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) @@ -37,11 +38,13 @@ romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c romstage-y += cbmem.c +romstage-y += spi.c romstage-y += gpio.c ################################################################################ ramstage-y += cbmem.c +ramstage-y += spi.c ramstage-y += cbfs.c ramstage-y += soc.c ramstage-y += timer.c diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h new file mode 100644 index 0000000..a39eff6 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MTK_MT8173_SPI_H +#define MTK_MT8173_SPI_H + +#include <spi-generic.h> +#include <types.h> + +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); + +/* SPI_CFG0_REG */ +enum { + SPI_CFG0_SCK_HIGH_SHIFT = 0, + SPI_CFG0_SCK_LOW_SHIFT = 8, + SPI_CFG0_CS_HOLD_SHIFT = 16, + SPI_CFG0_CS_SETUP_SHIFT = 24, +}; + +/*SPI_CFG1_REG*/ +enum { + SPI_CFG1_CS_IDLE_SHIFT = 0, + SPI_CFG1_PACKET_LOOP_SHIFT = 8, + SPI_CFG1_PACKET_LENGTH_SHIFT = 16, + + SPI_CFG1_CS_IDLE_MASK = 0xff << SPI_CFG1_CS_IDLE_SHIFT, + SPI_CFG1_PACKET_LOOP_MASK = 0xff << SPI_CFG1_PACKET_LOOP_SHIFT, + SPI_CFG1_PACKET_LENGTH_MASK = 0x3ff << SPI_CFG1_PACKET_LENGTH_SHIFT, +}; + +enum { + SPI_CMD_ACT_SHIFT = 0, + SPI_CMD_RESUME_SHIFT = 1, + SPI_CMD_RST_SHIFT = 2, + SPI_CMD_PAUSE_EN_SHIFT = 4, + SPI_CMD_DEASSERT_SHIFT = 5, + SPI_CMD_CPHA_SHIFT = 8, + SPI_CMD_CPOL_SHIFT = 9, + SPI_CMD_RX_DMA_SHIFT = 10, + SPI_CMD_TX_DMA_SHIFT = 11, + SPI_CMD_TXMSBF_SHIFT = 12, + SPI_CMD_RXMSBF_SHIFT = 13, + SPI_CMD_RX_ENDIAN_SHIFT = 14, + SPI_CMD_TX_ENDIAN_SHIFT = 15, + SPI_CMD_FINISH_IE_SHIFT = 16, + SPI_CMD_PAUSE_IE_SHIFT = 17, + + SPI_CMD_ACT_EN = BIT(SPI_CMD_ACT_SHIFT), + SPI_CMD_RESUME_EN = BIT(SPI_CMD_RESUME_SHIFT), + SPI_CMD_RST_EN = BIT(SPI_CMD_RST_SHIFT), + SPI_CMD_PAUSE_EN = BIT(SPI_CMD_PAUSE_EN_SHIFT), + SPI_CMD_DEASSERT_EN = BIT(SPI_CMD_DEASSERT_SHIFT), + SPI_CMD_CPHA_EN = BIT(SPI_CMD_CPHA_SHIFT), + SPI_CMD_CPOL_EN = BIT(SPI_CMD_CPOL_SHIFT), + SPI_CMD_RX_DMA_EN = BIT(SPI_CMD_RX_DMA_SHIFT), + SPI_CMD_TX_DMA_EN = BIT(SPI_CMD_TX_DMA_SHIFT), + SPI_CMD_TXMSBF_EN = BIT(SPI_CMD_TXMSBF_SHIFT), + SPI_CMD_RXMSBF_EN = BIT(SPI_CMD_RXMSBF_SHIFT), + SPI_CMD_RX_ENDIAN_EN = BIT(SPI_CMD_RX_ENDIAN_SHIFT), + SPI_CMD_TX_ENDIAN_EN = BIT(SPI_CMD_TX_ENDIAN_SHIFT), + SPI_CMD_FINISH_IE_EN = BIT(SPI_CMD_FINISH_IE_SHIFT), + SPI_CMD_PAUSE_IE_EN = BIT(SPI_CMD_PAUSE_IE_SHIFT), +}; + +enum spi_pad_mask { + SPI_PAD0_MASK = 0x0, + SPI_PAD1_MASK = 0x1, + SPI_PAD2_MASK = 0x2, + SPI_PAD3_MASK = 0x3, + SPI_PAD_SEL_MASK = 0x3 +}; + + +struct mtk_spi_bus { + struct spi_slave slave; + struct mtk_spi_regs *regs; + int initialized; + int state; +}; + +void mtk_spi_init(unsigned int bus, unsigned int pad_select, + unsigned int speed_hz); +#endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c new file mode 100644 index 0000000..30b228b --- /dev/null +++ b/src/soc/mediatek/mt8173/spi.c @@ -0,0 +1,306 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <endian.h> +#include <spi_flash.h> +#include <stdlib.h> +#include <string.h> +#include <timer.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/pinmux.h> +#include <soc/pll.h> +#include <soc/spi.h> + +enum { + MTK_FIFO_DEPTH = 32, + MTK_TXRX_TIMEOUT_US = 1000 * 1000, + MTK_ARBITRARY_VALUE = 0xdeaddead +}; + +enum { + MTK_SPI_IDLE = 0, + MTK_SPI_PAUSE_IDLE = 1 +}; + +enum { + MTK_SPI_BUSY_STATUS = 1, + MTK_SPI_PAUSE_FINISH_INT_STATUS = 3 +}; + +static struct mtk_spi_bus spi_bus[1] = { + { + .slave = { + .bus = 0, + }, + .regs = (void *)SPI_BASE, + .state = MTK_SPI_IDLE, + } +}; + +static inline struct mtk_spi_bus *to_mtk_spi(struct spi_slave *slave) +{ + return container_of(slave, struct mtk_spi_bus, slave); +} + +static void spi_sw_reset(struct mtk_spi_regs *regs) +{ + setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); + clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_RST_EN); +} + +static void mtk_spi_set_gpio_pinmux(enum spi_pad_mask pad_select) +{ + /* TODO: implement support for other pads when needed */ + assert(pad_select == SPI_PAD1_MASK); + gpio_set_mode(PAD_MSDC2_DAT2, PAD_MSDC2_DAT2_FUNC_SPI_CK_1); + gpio_set_mode(PAD_MSDC2_DAT3, PAD_MSDC2_DAT3_FUNC_SPI_MI_1); + gpio_set_mode(PAD_MSDC2_CLK, PAD_MSDC2_CLK_FUNC_SPI_MO_1); + gpio_set_mode(PAD_MSDC2_CMD, PAD_MSDC2_CMD_FUNC_SPI_CS_1); +} + +void mtk_spi_init(unsigned int bus, unsigned int pad_select, + unsigned int speed_hz) +{ + u32 div, sck_ticks, cs_ticks, reg_val; + /* mtk spi HW just support bus 0 */ + assert(bus == 0); + struct mtk_spi_bus *slave = &spi_bus[bus]; + struct mtk_spi_regs *regs = slave->regs; + + if (speed_hz < SPI_HZ / 2) + div = div_round_up(SPI_HZ, speed_hz); + else + div = 1; + + sck_ticks = div_round_up(div, 2); + cs_ticks = sck_ticks * 2; + + printk(BIOS_DEBUG, "SPI%u initialized at %u Hz", + pad_select, SPI_HZ / (sck_ticks * 2)); + + /* set the timing */ + write32(&regs->spi_cfg0_reg, + ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | + ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | + ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | + ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); + clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + + reg_val = read32(&regs->spi_cmd_reg); + + reg_val &= ~SPI_CMD_CPHA_EN; + reg_val &= ~SPI_CMD_CPOL_EN; + + /* set the mlsbx and mlsbtx */ + reg_val |= SPI_CMD_TXMSBF_EN; + reg_val |= SPI_CMD_RXMSBF_EN; + + /* set the tx/rx endian */ +#ifdef __LITTLE_ENDIAN + reg_val &= ~SPI_CMD_TX_ENDIAN_EN; + reg_val &= ~SPI_CMD_RX_ENDIAN_EN; +#else + reg_val |= SPI_CMD_TX_ENDIAN_EN; + reg_val |= SPI_CMD_RX_ENDIAN_EN; +#endif + + /* clear pause mode */ + reg_val &= ~SPI_CMD_PAUSE_EN; + + /* set finish interrupt always enable */ + reg_val |= SPI_CMD_FINISH_IE_EN; + + /* set pause interrupt always enable */ + reg_val |= SPI_CMD_PAUSE_IE_EN; + + /* disable dma mode */ + reg_val &= ~(SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN); + + /* set deassert mode */ + reg_val &= ~SPI_CMD_DEASSERT_EN; + + write32(&regs->spi_cmd_reg, reg_val); + + mtk_spi_set_gpio_pinmux(pad_select); + /* pad select */ + clrsetbits_le32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, + pad_select); +} + +static void mtk_spi_dump_data(const char *name, const uint8_t *data, + int size) +{ +#ifdef MTK_SPI_DEBUG + int i; + + printk(BIOS_DEBUG, "%s: 0x ", name); + for (i = 0; i < size; i++) + printk(BIOS_INFO, "%#x ", data[i]); + printk(BIOS_DEBUG, "\n"); +#endif +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + struct mtk_spi_bus *eslave; + + switch (bus) { + case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: + eslave = &spi_bus[bus]; + assert(read32(&eslave->regs->spi_cfg0_reg) != 0); + spi_sw_reset(eslave->regs); + return &eslave->slave; + default: + die ("wrong bus number.\n"); + }; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); + struct mtk_spi_regs *regs = mtk_slave->regs; + + setbits_le32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); + mtk_slave->state = MTK_SPI_IDLE; + + return 0; +} + +static int mtk_spi_fifo_transfer(struct spi_slave *slave, void *in, + const void *out, u32 size) +{ + struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); + struct mtk_spi_regs *regs = mtk_slave->regs; + uint8_t *inb = (uint8_t *)in; + const uint32_t *outb = (const uint32_t *)out; + uint32_t reg_val, i, word_count; + struct stopwatch sw; + + if (!size || size > MTK_FIFO_DEPTH) + return -1; + + clrsetbits_le32(&regs->spi_cfg1_reg, + SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, + ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | + (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + + word_count = div_round_up(size, sizeof(u32)); + if (inb) { + /* The SPI controller will transmit in full-duplex for RX, + * therefore we need arbitrary data on MOSI which the slave + * must ignore. + */ + for (i = 0; i < word_count; i++) + write32(&regs->spi_tx_data_reg, MTK_ARBITRARY_VALUE); + } + if (outb) { + for (i = 0; i < word_count; i++) + write32(&regs->spi_tx_data_reg, outb[i]); + mtk_spi_dump_data("the outb data is", + (const uint8_t *)outb, size); + } + + if (mtk_slave->state == MTK_SPI_IDLE) { + setbits_le32(&regs->spi_cmd_reg, SPI_CMD_ACT_EN); + mtk_slave->state = MTK_SPI_PAUSE_IDLE; + } else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) { + setbits_le32(&regs->spi_cmd_reg, SPI_CMD_RESUME_EN); + } + + stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); + while ((read32(&regs->spi_status1_reg) & MTK_SPI_BUSY_STATUS) == 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "Timeout waiting for status1 status.\n"); + goto error; + } + } + stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); + while ((read32(&regs->spi_status0_reg) & + MTK_SPI_PAUSE_FINISH_INT_STATUS) == 0) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "Timeout waiting for status0 status.\n"); + goto error; + } + } + + if (inb) { + for (i = 0; i < size; i++) { + if (i % 4 == 0) + reg_val = read32(&regs->spi_rx_data_reg); + *(inb + i) = (reg_val >> ((i % 4) * 8)) & 0xff; + } + mtk_spi_dump_data("the inb data is", inb, size); + } + + return 0; +error: + spi_sw_reset(regs); + mtk_slave->state = MTK_SPI_IDLE; + return -1; +} + +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytes_out, + void *din, unsigned int bytes_in) +{ + uint32_t min_size; + int ret; + + while (bytes_out || bytes_in) { + if (bytes_in && bytes_out) + min_size = MIN(MIN(bytes_out, bytes_in), MTK_FIFO_DEPTH); + else if (bytes_out) + min_size = MIN(bytes_out, MTK_FIFO_DEPTH); + else if (bytes_in) + min_size = MIN(bytes_in, MTK_FIFO_DEPTH); + + ret = mtk_spi_fifo_transfer(slave, din, dout, min_size); + if (ret != 0) + return ret; + + if (bytes_out) { + bytes_out -= min_size; + dout = (const uint8_t *)dout + min_size; + } + + if (bytes_in) { + bytes_in -= min_size; + din = (uint8_t *)din + min_size; + } + } + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); + struct mtk_spi_regs *regs = mtk_slave->regs; + + clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN); + spi_sw_reset(regs); + mtk_slave->state = MTK_SPI_IDLE; +}

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New patch to review for coreboot: google/oak: Add timestamps in romstage
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12610 -gerrit commit 66f842b993e0f588488925e8c3987ad485593b76 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Jul 31 17:10:44 2015 +0800 google/oak: Add timestamps in romstage BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963 Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292660 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c index 268f15f..ce736e4 100644 --- a/src/mainboard/google/oak/romstage.c +++ b/src/mainboard/google/oak/romstage.c @@ -27,9 +27,12 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <symbols.h> +#include <timestamp.h> void main(void) { + timestamp_add_now(TS_START_ROMSTAGE); + /* init uart baudrate when pll on */ console_init(); exception_init();

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New patch to review for coreboot: mediatek/mt8173: Add APIs for PMIC GPIO control
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12609 -gerrit commit 96114b9b6ac66b0fa77bbafd312ca2cda9f79513 Author: Biao Huang <biao.huang(a)mediatek.com> Date: Thu Sep 3 17:39:12 2015 +0800 mediatek/mt8173: Add APIs for PMIC GPIO control BRANCH=chromeos-2015.07 BUG=none TEST=verified on Oak rev3 Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96 Original-Signed-off-by: Biao Huang <biao.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297224 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/include/soc/mt6391.h | 35 ++++++ src/soc/mediatek/mt8173/mt6391.c | 159 +++++++++++++++++++++++++++ 2 files changed, 194 insertions(+) diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h index 304ef22..5a07355 100644 --- a/src/soc/mediatek/mt8173/include/soc/mt6391.h +++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h @@ -308,4 +308,39 @@ void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift); void mt6391_enable_reset_when_ap_resets(void); void mt6391_init(void); +/* + * PMIC GPIO REGISTER DEFINITION + */ +enum { + MT6391_GPIO_DIR_BASE = 0xC000, + MT6391_GPIO_PULLEN_BASE = 0xC020, + MT6391_GPIO_PULLSEL_BASE = 0xC040, + MT6391_GPIO_DOUT_BASE = 0xC080, + MT6391_GPIO_DIN_BASE = 0xC0A0, + MT6391_GPIO_MODE_BASE = 0xC0C0, +}; + +enum mt6391_pull_enable { + MT6391_GPIO_PULL_DISABLE = 0, + MT6391_GPIO_PULL_ENABLE = 1, +}; + +enum mt6391_pull_select { + MT6391_GPIO_PULL_DOWN = 0, + MT6391_GPIO_PULL_UP = 1, +}; + +/* + * PMIC GPIO Exported Function + */ +int mt6391_gpio_get(u32 gpio); +void mt6391_gpio_set(u32 gpio, int value); +void mt6391_gpio_input_pulldown(u32 gpio); +void mt6391_gpio_input_pullup(u32 gpio); +void mt6391_gpio_input(u32 gpio); +void mt6391_gpio_output(u32 gpio, int value); +void mt6391_gpio_set_pull(u32 gpio, enum mt6391_pull_enable enable, + enum mt6391_pull_select select); +void mt6391_gpio_set_mode(u32 gpio, int mode); + #endif /* __SOC_MEDIATEK_MT8173_MT6391_H__ */ diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 49fc0b0..91de817 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -16,11 +16,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <assert.h> #include <console/console.h> #include <delay.h> +#include <soc/addressmap.h> #include <soc/mt6391.h> #include <soc/pmic_wrap.h> +#include <types.h> #if CONFIG_DEBUG_PMIC #define DEBUG_PMIC(level, x...) printk(level, x) @@ -432,3 +435,159 @@ void mt6391_init(void) /* Adjust default BUCK voltage from eFuse */ mt6391_default_buck_voltage(); } + +/* API of GPIO in PMIC MT6391 */ +enum { + MAX_GPIO_REG_BITS = 16, + MAX_GPIO_MODE_PER_REG = 5, + GPIO_MODE_BITS = 3, + GPIO_PORT_OFFSET = 3, + GPIO_SET_OFFSET = 2, + GPIO_RST_OFFSET = 4, + MAX_MT6391_GPIO = 40 +}; + +enum { + MT6391_GPIO_DIRECTION_IN = 0, + MT6391_GPIO_DIRECTION_OUT = 1, +}; + +enum { + MT6391_GPIO_MODE = 0, +}; + +static void pos_bit_calc(u32 pin, u16 *pos, u16 *bit) +{ + *pos = (pin / MAX_GPIO_REG_BITS) << GPIO_PORT_OFFSET; + *bit = pin % MAX_GPIO_REG_BITS; +} + +static void pos_bit_calc_mode(u32 pin, u16 *pos, u16 *bit) +{ + *pos = (pin / MAX_GPIO_MODE_PER_REG) << GPIO_PORT_OFFSET; + *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; +} + +static s32 mt6391_gpio_set_dir(u32 pin, u32 dir) +{ + u16 pos; + u16 bit; + u16 reg; + + assert(pin <= MAX_MT6391_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (dir == MT6391_GPIO_DIRECTION_IN) + reg = MT6391_GPIO_DIR_BASE + pos + GPIO_RST_OFFSET; + else + reg = MT6391_GPIO_DIR_BASE + pos + GPIO_SET_OFFSET; + + if (pwrap_write(reg, 1L << bit) != 0) + return -1; + + return 0; +} + +void mt6391_gpio_set_pull(u32 pin, enum mt6391_pull_enable enable, + enum mt6391_pull_select select) +{ + u16 pos; + u16 bit; + u16 en_reg, sel_reg; + + assert(pin <= MAX_MT6391_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (enable == MT6391_GPIO_PULL_DISABLE) { + en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_RST_OFFSET; + } else { + en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_SET_OFFSET; + sel_reg = (select == MT6391_GPIO_PULL_DOWN) ? + (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_RST_OFFSET) : + (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_SET_OFFSET); + pwrap_write(sel_reg, 1L << bit); + } + pwrap_write(en_reg, 1L << bit); +} + +int mt6391_gpio_get(u32 pin) +{ + u16 pos; + u16 bit; + u16 reg; + u16 data; + + assert(pin <= MAX_MT6391_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + reg = MT6391_GPIO_DIN_BASE + pos; + pwrap_read(reg, &data); + + return (data & (1L << bit)) ? 1 : 0; +} + +void mt6391_gpio_set(u32 pin, int output) +{ + u16 pos; + u16 bit; + u16 reg; + + assert(pin <= MAX_MT6391_GPIO); + + pos_bit_calc(pin, &pos, &bit); + + if (output == 0) + reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_RST_OFFSET; + else + reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_SET_OFFSET; + + pwrap_write(reg, 1L << bit); +} + +void mt6391_gpio_set_mode(u32 pin, int mode) +{ + u16 pos; + u16 bit; + u16 mask = (1L << GPIO_MODE_BITS) - 1; + + assert(pin <= MAX_MT6391_GPIO); + + pos_bit_calc_mode(pin, &pos, &bit); + mt6391_write(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit); +} + +void mt6391_gpio_input_pulldown(u32 gpio) +{ + mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE, + MT6391_GPIO_PULL_DOWN); + mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN); + mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); +} + +void mt6391_gpio_input_pullup(u32 gpio) +{ + mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE, + MT6391_GPIO_PULL_UP); + mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN); + mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); +} + +void mt6391_gpio_input(u32 gpio) +{ + mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE, + MT6391_GPIO_PULL_DOWN); + mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN); + mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); +} + +void mt6391_gpio_output(u32 gpio, int value) +{ + mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE, + MT6391_GPIO_PULL_DOWN); + mt6391_gpio_set(gpio, value); + mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_OUT); + mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); +}

1 0

New patch to review for coreboot: mediatek/mt8173: Add mt6391 PMIC driver
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12608 -gerrit commit c48c374c235c1dafba07dc6122e83d283ae93a7d Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Fri Jul 31 17:10:52 2015 +0800 mediatek/mt8173: Add mt6391 PMIC driver BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/bootblock.c | 5 + src/soc/mediatek/mt8173/Makefile.inc | 2 +- src/soc/mediatek/mt8173/bootblock.c | 4 + src/soc/mediatek/mt8173/include/soc/mt6391.h | 311 +++++++++++++++++++ src/soc/mediatek/mt8173/mt6391.c | 434 +++++++++++++++++++++++++++ 5 files changed, 755 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index e82ad6e..54301e4 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -18,9 +18,11 @@ */ #include <arch/io.h> +#include <boardid.h> #include <bootblock_common.h> #include <delay.h> #include <soc/gpio.h> +#include <soc/mt6391.h> #include <soc/pericfg.h> #include <soc/pinmux.h> @@ -49,4 +51,7 @@ void bootblock_mainboard_init(void) i2c_set_gpio_pinmux(); setup_chromeos_gpios(); + + if (board_id() < 4) + mt6391_enable_reset_when_ap_resets(); } diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 3f3fb0b..a18d8a8 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -28,7 +28,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif -bootblock-y += gpio.c gpio_init.c pmic_wrap.c +bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index aaa7f61..ef09cae 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -18,12 +18,16 @@ */ #include <bootblock_common.h> +#include <soc/mt6391.h> #include <soc/pll.h> void bootblock_soc_init(void) { mt_pll_init(); + /* init pmic wrap SPI interface and pmic */ + mt6391_init(); + /* post init pll */ mt_pll_post_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h new file mode 100644 index 0000000..304ef22 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MT6391_H__ +#define __SOC_MEDIATEK_MT8173_MT6391_H__ + +#include <types.h> + +/* + * PMIC definition + */ +enum { + PMIC6391_E1_CID_CODE = 0x1091, + PMIC6391_E2_CID_CODE = 0x2091, + PMIC6397_E1_CID_CODE = 0x1097, + PMIC6397_E2_CID_CODE = 0x2097, + PMIC6397_E3_CID_CODE = 0x3097, + PMIC6397_E4_CID_CODE = 0x4097 +}; + +/* + * PMIC Register Index + */ + +/* PCHR Register Definition */ +enum { + PMIC_RG_CHR_CON1 = 0x0002, + PMIC_RG_CHR_CON6 = 0x000C, + PMIC_RG_CHR_CON13 = 0x001A, + PMIC_RG_CHR_CON18 = 0x0024, + PMIC_RG_CHR_CON21 = 0x002A, + PMIC_RG_CHR_CON23 = 0x002E, +}; + +/* TOP Register Definition */ +enum{ + PMIC_RG_CID = 0x0100, + PMIC_RG_TOP_CKPDN = 0x0102, + PMIC_RG_TOP_CKPDN2 = 0x0108, + PMIC_RG_TOP_RST_CON = 0x0114, + PMIC_RG_WRP_CKPDN = 0x011A, + PMIC_RG_TOP_RST_MISC = 0x0126, + PMIC_RG_TOP_CKCON1 = 0x0128, + PMIC_RG_TOP_CKCON2 = 0x012A, + PMIC_RG_TOP_CKTST1 = 0x012C, + PMIC_RG_TOP_CKTST2 = 0x012E, + PMIC_RG_OC_DEG_EN = 0x0130, + PMIC_RG_OC_CTL1 = 0x0134, + PMIC_RG_CHRSTATUS = 0x0144, + PMIC_RG_OCSTATUS0 = 0x0146, + PMIC_RG_OCSTATUS1 = 0x0148, + PMIC_RG_OCSTATUS2 = 0x014A, + PMIC_RG_TOP_CKPDN3 = 0x01CE, + PMIC_RG_TOP_CKCON3 = 0x01D4 +}; + +/* INT Register Definition */ +enum{ + PMIC_RG_INT_CON0 = 0x0178, + PMIC_RG_INT_CON1 = 0x017E, +}; + +/* FQMTR Register Definition */ +enum{ + PMIC_RG_FQMTR_CON0 = 0x0188, + PMIC_RG_FQMTR_CON1 = 0x018A, + PMIC_RG_FQMTR_CON2 = 0x018C +}; + +/* EFUSE Register Definition */ +enum{ + PMIC_RG_EFUSE_DOUT_256_271 = 0x01EE, + PMIC_RG_EFUSE_DOUT_272_287 = 0x01F0, + PMIC_RG_EFUSE_DOUT_288_303 = 0x01F2, + PMIC_RG_EFUSE_DOUT_304_319 = 0x01F4 +}; + +/* BUCK Register Definition */ +enum{ + PMIC_RG_BUCK_CON3 = 0x0206, + PMIC_RG_BUCK_CON8 = 0x0210, + PMIC_RG_VCA15_CON1 = 0x0216, + PMIC_RG_VCA15_CON5 = 0x021E, + PMIC_RG_VCA15_CON7 = 0x0222, + PMIC_RG_VCA15_CON8 = 0x0224, + PMIC_RG_VCA15_CON9 = 0x0226, + PMIC_RG_VCA15_CON10 = 0x0228, + PMIC_RG_VCA15_CON11 = 0x022A, + PMIC_RG_VCA15_CON18 = 0x0238, + PMIC_RG_VSRMCA15_CON5 = 0x0244, + PMIC_RG_VSRMCA15_CON6 = 0x0246, + PMIC_RG_VSRMCA15_CON7 = 0x0248, + PMIC_RG_VSRMCA15_CON8 = 0x024A, + PMIC_RG_VSRMCA15_CON9 = 0x024C, + PMIC_RG_VSRMCA15_CON10 = 0x024E, + PMIC_RG_VSRMCA15_CON11 = 0x0250, + PMIC_RG_VSRMCA15_CON18 = 0x025E, + PMIC_RG_VSRMCA15_CON19 = 0x0260, + PMIC_RG_VSRMCA15_CON20 = 0x0262, + PMIC_RG_VSRMCA15_CON21 = 0x0264, + PMIC_RG_VCORE_CON5 = 0x0270, + PMIC_RG_VCORE_CON6 = 0x0272, + PMIC_RG_VCORE_CON8 = 0x0276, + PMIC_RG_VCORE_CON9 = 0x0278, + PMIC_RG_VCORE_CON10 = 0x027A, + PMIC_RG_VCORE_CON11 = 0x027C, + PMIC_RG_VCORE_CON18 = 0x028A, + PMIC_RG_VGPU_CON1 = 0x028E, + PMIC_RG_VGPU_CON8 = 0x029C, + PMIC_RG_VGPU_CON18 = 0x02B0, + PMIC_RG_VIO18_CON18 = 0x0324, + PMIC_RG_VPCA7_CON5 = 0x0330, + PMIC_RG_VPCA7_CON6 = 0x0332, + PMIC_RG_VPCA7_CON7 = 0x0334, + PMIC_RG_VPCA7_CON8 = 0x0336, + PMIC_RG_VPCA7_CON9 = 0x0338, + PMIC_RG_VPCA7_CON10 = 0x033A, + PMIC_RG_VPCA7_CON11 = 0x033C, + PMIC_RG_VPCA7_CON18 = 0x034A, + PMIC_RG_VSRMCA7_CON5 = 0x0356, + PMIC_RG_VSRMCA7_CON6 = 0x0358, + PMIC_RG_VSRMCA7_CON8 = 0x035C, + PMIC_RG_VSRMCA7_CON9 = 0x035E, + PMIC_RG_VSRMCA7_CON10 = 0x0360, + PMIC_RG_VSRMCA7_CON11 = 0x0362, + PMIC_RG_VSRMCA7_CON18 = 0x0370, + PMIC_RG_VSRMCA7_CON19 = 0x0372, + PMIC_RG_VSRMCA7_CON20 = 0x0374, + PMIC_RG_VSRMCA7_CON21 = 0x0376, + PMIC_RG_VDRM_CON9 = 0x038A, + PMIC_RG_VDRM_CON10 = 0x038C, + PMIC_RG_VDRM_CON18 = 0x039C, + PMIC_RG_BUCK_K_CON0 = 0x039E +}; + +/* ANALDO Register Definition */ +enum{ + PMIC_RG_ANALDO_CON0 = 0x0400, + PMIC_RG_ANALDO_CON2 = 0x0404, + PMIC_RG_ANALDO_CON6 = 0x040C, +}; + +/* DIGLDO Register Definition */ +enum{ + PMIC_RG_DIGLDO_CON5 = 0x041A, + PMIC_RG_DIGLDO_CON6 = 0x041C, + PMIC_RG_DIGLDO_CON8 = 0x0420, + PMIC_RG_DIGLDO_CON10 = 0x0424, + PMIC_RG_DIGLDO_CON19 = 0x0436, + PMIC_RG_DIGLDO_CON20 = 0x0438, + PMIC_RG_DIGLDO_CON22 = 0x043C, + PMIC_RG_DIGLDO_CON24 = 0x0440, + PMIC_RG_DIGLDO_CON27 = 0x0446, + PMIC_RG_DIGLDO_CON30 = 0x044C, + PMIC_RG_DIGLDO_CON33 = 0x045A +}; + +/* STRUP Register Definition */ +enum{ + PMIC_RG_STRUP_CON0 = 0x0500, + PMIC_RG_STRUP_CON2 = 0x0502, + PMIC_RG_STRUP_CON5 = 0x0508, + PMIC_RG_STRUP_CON7 = 0x050C, + PMIC_RG_STRUP_CON10 = 0x0512 +}; + +/* AUXADC Register Definition */ +enum{ + PMIC_RG_AUXADC_CON14 = 0x055E +}; + +/* Driver Register Definition */ +enum{ + PMIC_RG_FLASH_CON0 = 0x0560, + PMIC_RG_KPLED_CON0 = 0x0566 +}; + +/* SPK Register Definition */ +enum{ + PMIC_RG_SPK_CON0 = 0x0600, + PMIC_RG_SPK_CON2 = 0x0604, + PMIC_RG_SPK_CON3 = 0x0606, + PMIC_RG_SPK_CON5 = 0x060A, + PMIC_RG_SPK_CON9 = 0x0612 +}; + +/* FGADC Register Definition */ +enum{ + PMIC_RG_FGADC_CON13 = 0x0632, + PMIC_RG_FGADC_CON16 = 0x0638, + PMIC_RG_FGADC_CON17 = 0x063A, + PMIC_RG_FGADC_CON18 = 0x063C +}; + +/* AUDDAC Register Definition */ +enum{ + PMIC_RG_AUDLDO_CFG0 = 0x0714, + PMIC_RG_AUD_NCP0 = 0x071A +}; + +/* DCXO Register Definition */ +enum{ + PMIC_RG_PMIC_RG_RG_DCXO_CON0 = 0x83a, + PMIC_RG_DCXO_CON2 = 0x83e, + PMIC_RG_DCXO_MANUAL_CON1 = 0x844, + PMIC_RG_DCXO_ANALOG_CON1 = 0x84a, + PMIC_RG_DCXO_FORCE_MODE1 = 0x854, + PMIC_RG_DCXO_POR2_CON3 = 0x85c +}; + +/* TOP MASK and SHIFT Definition */ +enum{ + PMIC_RG_FQMTR_PDN_SHIFT = 1, + PMIC_RG_AP_RST_DIS_MASK = 0x1, + PMIC_RG_AP_RST_DIS_SHIFT = 0, + PMIC_RG_RST_PART_SEL_MASK = 0x1, + PMIC_RG_RST_PART_SEL_SHIFT = 4, + PMIC_RG_TOP_RST_MISC_RSV_3_MASK = 0x1, + PMIC_RG_TOP_RST_MISC_RSV_3_SHIFT = 3, + PMIC_RG_STRUP_MAN_RST_EN_MASK = 0x1, + PMIC_RG_STRUP_MAN_RST_EN_SHIFT = 2, + PMIC_RG_SYSRSTB_EN_MASK = 0x1, + PMIC_RG_SYSRSTB_EN_SHIFT = 1, + PMIC_RG_PWRKEY_DEB_MASK = 0x1, + PMIC_RG_PWRKEY_DEB_SHIFT = 3, + PMIC_RG_HOMEKEY_DEB_MASK = 0x1, + PMIC_RG_HOMEKEY_DEB_SHIFT = 4 +}; + +/* ANALDO MASK and SHIFT Definition */ +enum{ + PMIC_RG_VCAMA_VOSEL_MASK = 0x3, + PMIC_RG_VCAMA_VOSEL_SHIFT = 6, + PMIC_RG_VCAMA_EN_MASK = 0x1, + PMIC_RG_VCAMA_EN_SHIFT = 15, +}; + +/* DCXO MASK and SHIFT Definition */ +enum{ + PMIC_RG_DCXO_C2_UNTRIM_MASK = 0x1, + PMIC_RG_DCXO_C2_UNTRIM_SHIFT = 15, + PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_MASK = 0x1, + PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_SHIFT = 9, + PMIC_RG_DCXO_MANUAL_SYNC_EN_MASK = 0x1, + PMIC_RG_DCXO_MANUAL_SYNC_EN_SHIFT = 8, + PMIC_RG_DCXO_ATTEN_BB_MASK = 0x3, + PMIC_RG_DCXO_ATTEN_BB_SHIFT = 11, + PMIC_RG_DCXO_LDO_BB_V_MASK = 0x3, + PMIC_RG_DCXO_LDO_BB_V_SHIFT = 2 +}; + +enum ldo_power { + LDO_VCAMD, + LDO_VCAMIO, + LDO_VCAMAF, + LDO_VGP4, + LDO_VGP5, + LDO_VGP6, + LDO_VTCXO, + LDO_VA28, + LDO_VCAMA, + LDO_VIO28, + LDO_VUSB, + LDO_VMC, + LDO_VMCH, + LDO_VEMC3V3, + LDO_VIBR, +}; + +enum ldo_voltage { + LDO_1P2 = 0, + LDO_1P3 = 1, + LDO_1P5 = 2, + LDO_1P8 = 3, + LDO_2P5 = 4, + LDO_2P8 = 5, + LDO_3P0 = 6, + LDO_3P3 = 7, + LDO_NUM_VOLTAGES, + + LDO_1P22, /* only VCAMD */ + LDO_1P0, /* only VCAMIO */ + LDO_2P0, /* only VGP5 */ +}; + +/* + * PMIC Exported Function + */ +void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel); +u32 mt6391_read(u16 reg, u32 mask, u32 shift); +void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift); +void mt6391_enable_reset_when_ap_resets(void); +void mt6391_init(void); + +#endif /* __SOC_MEDIATEK_MT8173_MT6391_H__ */ diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c new file mode 100644 index 0000000..49fc0b0 --- /dev/null +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -0,0 +1,434 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6391.h> +#include <soc/pmic_wrap.h> + +#if CONFIG_DEBUG_PMIC +#define DEBUG_PMIC(level, x...) printk(level, x) +#else +#define DEBUG_PMIC(level, x...) +#endif + +u32 mt6391_read(u16 reg, u32 mask, u32 shift) +{ + u16 rdata; + + pwrap_wacs2(0, reg, 0, &rdata, 1); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + DEBUG_PMIC(BIOS_INFO, "[%s] Reg[%#x]=%#x\n", + __func__, reg, rdata); + return rdata; +} + +void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift) +{ + u16 rdata; + u16 old_rdata, new_rdata; + + pwrap_wacs2(0, reg, 0, &rdata, 1); + old_rdata = rdata; + + rdata &= ~(mask << shift); + rdata |= (val << shift); + new_rdata = rdata; + + pwrap_wacs2(1, reg, rdata, &rdata, 1); + + DEBUG_PMIC(BIOS_INFO, "[%s] write Reg[%#x]=%#x -> %#x\n", + __func__, reg, old_rdata, new_rdata); + return; +} + +void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel) +{ + u16 addr; + switch (ldo) { + case LDO_VCAMD: + assert(vsel != 0); + if (vsel == LDO_1P22) + vsel = 0; + break; + case LDO_VCAMIO: + assert(vsel != 1); + if (vsel == LDO_1P0) + vsel = 1; + break; + case LDO_VGP5: + assert(vsel != 7); + if (vsel == LDO_2P0) + vsel = 7; + break; + default: + break; + } + assert(vsel < LDO_NUM_VOLTAGES); + + if (ldo == LDO_VGP6) + addr = PMIC_RG_DIGLDO_CON33; + else + addr = PMIC_RG_DIGLDO_CON19 + ldo * 2; + + mt6391_write(addr, vsel, 0x7, 5); + mt6391_write(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15); + +} + +void mt6391_enable_reset_when_ap_resets(void) +{ + /* Enable AP watchdog reset */ + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0); +} + +static void mt6391_init_setting(void) +{ + /* Enable PMIC RST function (depends on main chip RST function) */ + /* + * state1: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=1, RG_RST_PART_SEL=1 + * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1 + * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0 + */ + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1); + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2); + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4); + + /* Disable AP watchdog reset */ + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0); + + /* Enable CA15 by default for different PMIC behavior */ + mt6391_write(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0); + mt6391_write(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0); + mt6391_write(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0); + udelay(200); /* delay for Buck ready */ + + /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */ + mt6391_write(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3); + /* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9); + /* [8:8]: RG_OSC_SEL_AUTO; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8); + /* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6); + /* [5:5]: RG_SMPS_AUTOFF_DIS; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5); + /* [7:7]: VDRM_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7); + /* [6:6]: VSRMCA7_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6); + /* [5:5]: VPCA7_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5); + /* [4:4]: VIO18_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4); + /* [3:3]: VGPU_DEG_EN; For OC protection */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3); + /* [2:2]: VCORE_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2); + /* [1:1]: VSRMCA15_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1); + /* [0:0]: VCA15_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0); + /* [11:11]: RG_INT_EN_THR_H; */ + mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 11); + /* [10:10]: RG_INT_EN_THR_L; */ + mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 10); + /* [4:4]: RG_INT_EN_BAT_L; */ + mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 4); + /* [11:11]: RG_INT_EN_VGPU; OC protection */ + mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 11); + /* [8:8]: RG_INT_EN_VCA15; OC protection */ + mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 8); + /* [12:0]: BUCK_RSV; for OC protection */ + mt6391_write(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0); + /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 10); + /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6); + /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4); + /* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2); + /* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0); + /* [13:12]: RG_VCA15_CSL2; for OC protection */ + mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12); + /* [11:10]: RG_VCA15_CSL1; for OC protection */ + mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10); + /* [15:15]: VCA15_SFCHG_REN; soft change rising enable */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15); + /* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8); + /* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7); + /* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0); + /* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0); + /* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */ + mt6391_write(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8); + /* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */ + mt6391_write(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4); + /* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5); + /* [5:4]: VSRMCA15_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4); + /* [15:15]: VSRMCA15_SFCHG_REN; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15); + /* [14:8]: VSRMCA15_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8); + /* [7:7]: VSRMCA15_SFCHG_FEN; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7); + /* [6:0]: VSRMCA15_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); + /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ + mt6391_write(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); + /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ + mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); + /* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */ + mt6391_write(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1); + /* [5:4]: VCORE_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4); + /* [15:15]: VCORE_SFCHG_REN; */ + mt6391_write(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15); + /* [14:8]: VCORE_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8); + /* [6:0]: VCORE_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0); + /* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */ + mt6391_write(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0); + /* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control R2R to */ + mt6391_write(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8); + /* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */ + mt6391_write(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4); + /* [1:0]: VCORE_TRANSTD; */ + mt6391_write(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0); + /* [9:8]: RG_VGPU_CSL; for OC protection */ + mt6391_write(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8); + /* [15:15]: VGPU_SFCHG_REN; */ + mt6391_write(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15); + /* [14:8]: VGPU_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8); + /* [6:0]: VGPU_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0); + /* [5:4]: VGPU_VOSEL_TRANS_EN; */ + mt6391_write(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4); + /* [1:0]: VGPU_TRANSTD; */ + mt6391_write(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0); + /* [5:4]: VPCA7_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4); + /* [15:15]: VPCA7_SFCHG_REN; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15); + /* [14:8]: VPCA7_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8); + /* [7:7]: VPCA7_SFCHG_FEN; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7); + /* [6:0]: VPCA7_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0); + /* [6:0]: VPCA7_VOSEL_SLEEP; */ + mt6391_write(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0); + /* [8:8]: VPCA7_VSLEEP_EN; */ + mt6391_write(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8); + /* [5:4]: VPCA7_VOSEL_TRANS_EN; */ + mt6391_write(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4); + /* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5); + /* [5:4]: VSRMCA7_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4); + /* [15:15]: VSRMCA7_SFCHG_REN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15); + /* [14:8]: VSRMCA7_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8); + /* [7:7]: VSRMCA7_SFCHG_FEN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7); + /* [6:0]: VSRMCA7_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0); + /* [6:0]: VSRMCA7_VOSEL_SLEEP; */ + mt6391_write(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0); + /* [8:8]: VSRMCA7_VSLEEP_EN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x1, 0x1, 8); + /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4); + /* [8:8]: VDRM_VSLEEP_EN; */ + mt6391_write(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8); + /* [2:2]: VIBR_THER_SHEN_EN; */ + mt6391_write(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2); + /* [5:5]: THR_HWPDN_EN; */ + mt6391_write(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5); + /* [3:3]: RG_RST_DRVSEL; */ + mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3); + /* [2:2]: RG_EN_DRVSEL; */ + mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2); + /* [1:1]: PWRBB_DEB_EN; */ + mt6391_write(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1); + /* [12:12]: VSRMCA15_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12); + /* [11:11]: VPCA15_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11); + /* [10:10]: VCORE_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10); + /* [9:9]: VSRMCA7_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9); + /* [8:8]: VPCA7_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8); + /* [1:1]: STRUP_PWROFF_PREOFF_EN; */ + mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1); + /* [0:0]: STRUP_PWROFF_SEQ_EN; */ + mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0); + /* [15:8]: RG_ADC_TRIM_CH_SEL; */ + mt6391_write(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8); + /* [1:1]: FLASH_THER_SHDN_EN; */ + mt6391_write(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1); + /* [1:1]: KPLED_THER_SHDN_EN; */ + mt6391_write(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1); + /* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */ + mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8); + /* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */ + mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0); + /* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */ + mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8); + /* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */ + mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0); + /* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */ + mt6391_write(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0); + /* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */ + mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8); + /* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */ + mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0); + /* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */ + mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8); + /* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */ + mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0); + /* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */ + mt6391_write(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0); + /* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */ + mt6391_write(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0); + /* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0); + /* [1:1]: VPCA7_VOSEL_CTRL; */ + mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1); + /* [1:1]: VSRMCA7_VOSEL_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1); + /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */ + mt6391_write(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4); + /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4); + /* [4:4]: VPCA7_TRACK_ON_CTRL; */ + mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4); + /* [4:4]: VSRMCA7_TRACK_ON_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4); + /* [15:14]: VGPU OC; */ + mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 14); + /* [3:2]: VCA15 OC; */ + mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 2); + + /* Set VPCA7 to 1.2V */ + mt6391_write(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0); + mt6391_write(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0); + /* Set VSRMCA7 to 1.1V */ + mt6391_write(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0); + mt6391_write(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0); + + /* Enable VGP6 and set to 3.3V*/ + mt6391_write(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15); + mt6391_write(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5); + + /* Set VDRM to 1.21875V */ + mt6391_write(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); + mt6391_write(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0); + + /* 26M clock amplitute adjust */ + mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); + mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11); + + /* For low power, set VTCXO switch by SRCVOLTEN */ + mt6391_write(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0); + /* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */ + mt6391_write(PMIC_RG_ANALDO_CON0, 0, 0x3, 13); + /* [11]=0(VTCXO_ON_CTRL), */ + mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 11); + /* [10]=1(RG_VTCXO_EN), */ + mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 10); + /* [4:3]=1(RG_VTCXOTD_SEL) */ + mt6391_write(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3); + /* For low power, VIO18 set sleep_en to HW mode */ + mt6391_write(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8); + +} + +static void mt6391_default_buck_voltage(void) +{ + u16 reg_val = 0; + u16 buck_val = 0; + /* There are two kinds of PMIC used for MT8173 : MT6397s/MT6391. + * MT6397s: the default voltage of register was not suitable for + * MT8173, needs to apply the setting of eFuse. + * VPCA15/VSRMCA15/: 1.15V + * VCORE: 1.05V + * + * MT6391: the default voltage of register was matched for MT8173. + * VPAC15/VCORE/VGPU: 1.0V + * VSRMCA15: 1.0125V + */ + reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0); + + if ((reg_val & 0x01) == 0x01) { + /* VCORE */ + reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12); + buck_val = mt6391_read(PMIC_RG_VCORE_CON9, 0x7f, 0x0); + + /* VCORE_VOSEL[3:6] => eFuse bit 268-271 */ + buck_val = (buck_val & 0x07) | (reg_val << 3); + mt6391_write(PMIC_RG_VCORE_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VCORE_CON10, buck_val, 0x7f, 0x0); + + reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0); + /* VCA15 */ + buck_val = 0; + buck_val = mt6391_read(PMIC_RG_VCA15_CON9, 0x7f, 0x0); + buck_val = (buck_val & 0x07) | ((reg_val & 0x0F) << 3); + mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0); + + /* VSAMRCA15 */ + buck_val = 0; + buck_val = mt6391_read(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0); + buck_val = (buck_val & 0x07) | ((reg_val & 0xF0) >> 1); + mt6391_write(PMIC_RG_VSRMCA15_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VSRMCA15_CON10, buck_val, 0x7f, 0x0); + + /* set the power control by register(use original) */ + mt6391_write(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12); + } +} + +void mt6391_init(void) +{ + if (pwrap_init()) + die("ERROR - Failed to initial pmic wrap!"); + /* pmic initial setting */ + mt6391_init_setting(); + + /* Adjust default BUCK voltage from eFuse */ + mt6391_default_buck_voltage(); +}

1 0

New patch to review for coreboot: google/oak: Add board_id() and ram_code() implementation
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12607 -gerrit commit 91e85ebd1996f668f4efd2bb62098b39b353df5d Author: CC Ma <cc.ma(a)mediatek.com> Date: Fri Jul 31 17:10:58 2015 +0800 google/oak: Add board_id() and ram_code() implementation BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 1 + src/mainboard/google/oak/Makefile.inc | 3 ++ src/mainboard/google/oak/boardid.c | 60 +++++++++++++++++++++++++++++++++++ src/mainboard/google/oak/gpio.h | 9 ++++++ 4 files changed, 73 insertions(+) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index a7904ca..e45fb4c 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -22,6 +22,7 @@ if BOARD_GOOGLE_OAK config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_MEDIATEK_MT8173 + select BOARD_ID_AUTO select CHROMEOS_VBNV_EC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index dbfc1db..dca67db 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -20,12 +20,15 @@ bootblock-y += bootblock.c bootblock-y += memlayout.ld bootblock-y += chromeos.c +bootblock-y += boardid.c romstage-y += chromeos.c romstage-y += romstage.c romstage-y += memlayout.ld +romstage-y += boardid.c ramstage-y += mainboard.c ramstage-y += chromeos.c ramstage-y += memlayout.ld +ramstage-y += boardid.c diff --git a/src/mainboard/google/oak/boardid.c b/src/mainboard/google/oak/boardid.c new file mode 100644 index 0000000..fe5ad0a --- /dev/null +++ b/src/mainboard/google/oak/boardid.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boardid.h> +#include <gpio.h> +#include <console/console.h> +#include <stdlib.h> +#include "gpio.h" + +static int board_id_value = -1; + +static uint8_t get_board_id(void) +{ + uint8_t bid = 0; + static gpio_t pins[] = {[2] = BOARD_ID_2, [1] = BOARD_ID_1, + [0] = BOARD_ID_0}; + + bid = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_INFO, "Board ID %d\n", bid); + + return bid; +} + +uint8_t board_id(void) +{ + if (board_id_value < 0) + board_id_value = get_board_id(); + + return board_id_value; +} + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = RAM_ID_3, [2] = RAM_ID_2, [1] = RAM_ID_1, + [0] = RAM_ID_0}; + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_INFO, "RAM Config: %u\n", code); + + return code; +} diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h index d319749..e07c9e3 100644 --- a/src/mainboard/google/oak/gpio.h +++ b/src/mainboard/google/oak/gpio.h @@ -23,6 +23,15 @@ enum { LID = PAD_EINT12, + /* Board ID related GPIOS. */ + BOARD_ID_0 = PAD_RDN3_A, + BOARD_ID_1 = PAD_RDP3_A, + BOARD_ID_2 = PAD_RDN2_A, + /* RAM ID related GPIOS. */ + RAM_ID_0 = PAD_RDP2_A, + RAM_ID_1 = PAD_RCN_A, + RAM_ID_2 = PAD_RCP_A, + RAM_ID_3 = PAD_RDN1_A, /* Write Protect */ WRITE_PROTECT = PAD_EINT4, /* Power button */

1 0

New patch to review for coreboot: google/oak: Implement the code which reads GPIOs for ChromeOS.
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12606 -gerrit commit 83b6d82f4293da40d2ddaf4565e2479c26972915 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Jul 31 17:10:57 2015 +0800 google/oak: Implement the code which reads GPIOs for ChromeOS. BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/bootblock.c | 4 ++ src/mainboard/google/oak/chromeos.c | 86 +++++++++++++++++++++++++++++++++++- src/mainboard/google/oak/gpio.h | 40 +++++++++++++++++ 3 files changed, 128 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 38a777c..e82ad6e 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -24,6 +24,8 @@ #include <soc/pericfg.h> #include <soc/pinmux.h> +#include "gpio.h" + static void i2c_set_gpio_pinmux(void) { gpio_set_mode(PAD_SDA1, PAD_SDA1_FUNC_SDA1); @@ -45,4 +47,6 @@ void bootblock_mainboard_init(void) /* set i2c related gpio */ i2c_set_gpio_pinmux(); + + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index 8d45a13..9f4cbaa 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -18,10 +18,88 @@ */ #include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <gpio.h> +#include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(WRITE_PROTECT); + gpio_input_pullup(EC_IN_RW); + gpio_input_pullup(EC_IRQ); + gpio_input_pullup(LID); + gpio_input_pullup(POWER_BUTTON); + gpio_output(EC_SUSPEND_L, 1); +} + void fill_lb_gpios(struct lb_gpios *gpios) { + int count = 0; + + /* Write protect : active low */ + gpios->gpios[count].port = WRITE_PROTECT; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(WRITE_PROTECT); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = LID; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: active high */ + gpios->gpios[count].port = POWER_BUTTON; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + /* EC in RW: active high */ + gpios->gpios[count].port = EC_IN_RW; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC in RW", + GPIO_MAX_NAME_LENGTH); + count++; + + /* EC interrupt: GPIO active low */ + gpios->gpios[count].port = EC_IRQ; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "EC interrupt", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); } int get_developer_mode_switch(void) @@ -31,10 +109,14 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - return 0; + uint32_t ec_events; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_write_protect_state(void) { - return 0; + return !gpio_get(WRITE_PROTECT); } diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h new file mode 100644 index 0000000..d319749 --- /dev/null +++ b/src/mainboard/google/oak/gpio.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_OAK_GPIO_H__ +#define __MAINBOARD_GOOGLE_OAK_GPIO_H__ +#include <soc/pinmux.h> + +enum { + LID = PAD_EINT12, + /* Write Protect */ + WRITE_PROTECT = PAD_EINT4, + /* Power button */ + POWER_BUTTON = PAD_EINT14, + /* EC Interrupt */ + EC_IRQ = PAD_EINT0, + /* EC in RW signal */ + EC_IN_RW = PAD_DAIPCMIN, + /* EC AP suspend */ + EC_SUSPEND_L = PAD_KPROW1, +}; + +void setup_chromeos_gpios(void); + +#endif /* __MAINBOARD_GOOGLE_OAK_GPIO_H__ */

1 0

New patch to review for coreboot: google/oak: Initialize the necessary pins
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12605 -gerrit commit a9fc5dac2e72f8d21ccb2c9d02aa68431f595751 Author: Biao Huang <biao.huang(a)mediatek.com> Date: Fri Jul 31 17:10:56 2015 +0800 google/oak: Initialize the necessary pins BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/bootblock.c | 15 +++ src/soc/mediatek/mt8173/Makefile.inc | 2 +- src/soc/mediatek/mt8173/gpio_init.c | 74 ++++++++++++ src/soc/mediatek/mt8173/include/soc/gpio.h | 2 + src/soc/mediatek/mt8173/include/soc/mipi.h | 38 ++++++ src/soc/mediatek/mt8173/include/soc/pinmux.h | 170 +++++++++++++++++++++++++++ 6 files changed, 300 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index ddd71b3..38a777c 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -20,7 +20,17 @@ #include <arch/io.h> #include <bootblock_common.h> #include <delay.h> +#include <soc/gpio.h> #include <soc/pericfg.h> +#include <soc/pinmux.h> + +static void i2c_set_gpio_pinmux(void) +{ + gpio_set_mode(PAD_SDA1, PAD_SDA1_FUNC_SDA1); + gpio_set_mode(PAD_SCL1, PAD_SCL1_FUNC_SCL1); + gpio_set_mode(PAD_SDA4, PAD_SDA4_FUNC_SDA4); + gpio_set_mode(PAD_SCL4, PAD_SCL4_FUNC_SCL4); +} void bootblock_mainboard_early_init(void) { @@ -30,4 +40,9 @@ void bootblock_mainboard_early_init(void) void bootblock_mainboard_init(void) { + /* adjust gpio params when external voltage is 1.8V */ + gpio_init(GPIO_EINT_1P8V); + + /* set i2c related gpio */ + i2c_set_gpio_pinmux(); } diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index abaf3cc..3f3fb0b 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -28,7 +28,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif -bootblock-y += gpio.c pmic_wrap.c +bootblock-y += gpio.c gpio_init.c pmic_wrap.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c new file mode 100644 index 0000000..527a795 --- /dev/null +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mipi.h> + +/* + * GPIO 47-56 are controlled by MIPI register by default. + * When they are used as GPI, we have to set IES of MIPI register to 1. + * Additionally, pulls of these pins are controlled by MIPI, + * and pull-setting of these pins are forbidden in our driver. + */ +static void set_gpi_from_mipi(void) +{ + setbits_le32(&mt8173_mipi->mipi_rx_ana4c, + 1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */ + 1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */ + 1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */ + 1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */ + 1 << 24); /* RF_MIPI_GPI4_IES GPI51 */ + + setbits_le32(&mt8173_mipi->mipi_rx_ana50, + 1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */ + 1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */ + 1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */ + 1 << 18 | /* RG_MIPI_GPI8_IES GPI55 */ + 1 << 24); /* RF_MIPI_GPI9_IES GPI56 */ +} + +/* + * overwrite the T/RDSEL default value of exmd_ctrl and + * msdc2_ctrl5 as b'1010 + */ +static void gpio_set_duty(enum external_power ext_power) +{ + /* EXMD control reg */ + if (ext_power == GPIO_EINT_1P8V) { + /* exmd_ctrl[9:4] = b`000000, [3:0] = b`1010 */ + write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x3F5); + write16(&mt8173_gpio->exmd_ctrl[0].set, 0xA); + } else if (ext_power == GPIO_EINT_3P3V) { + /* exmd_ctrl[9:4] = b`001100, [3:0] = b`1010 */ + write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x335); + write16(&mt8173_gpio->exmd_ctrl[0].set, 0xCA); + } + + /* other R/TDSEL */ + /* msdc2_ctrl5 , bit[3:0] = b`1010 */ + write16(&mt8173_gpio->msdc2_ctrl5.set, 0xA); + write16(&mt8173_gpio->msdc2_ctrl5.rst, 0x5); +} + +void gpio_init(enum external_power ext_power) +{ + set_gpi_from_mipi(); + gpio_set_duty(ext_power); +} diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index d0a3dd2..821053c 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -89,4 +89,6 @@ static struct gpio_regs *const mt8173_gpio = (void *)(GPIO_BASE); void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); void gpio_set_mode(gpio_t gpio, int mode); +void gpio_init(enum external_power); + #endif /* SOC_MEDIATEK_MT8173_GPIO_H */ diff --git a/src/soc/mediatek/mt8173/include/soc/mipi.h b/src/soc/mediatek/mt8173/include/soc/mipi.h new file mode 100644 index 0000000..bf8b3b4 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mipi.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MIPI_H__ +#define __SOC_MEDIATEK_MT8173_MIPI_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mipi_rx_regs { + uint32_t rev0[19]; + uint32_t mipi_rx_ana4c; + uint32_t mipi_rx_ana50; + uint32_t rev1; +}; + +check_member(mipi_rx_regs, mipi_rx_ana4c, 0x4c); +check_member(mipi_rx_regs, rev1, 0x54); + +static struct mipi_rx_regs *const mt8173_mipi = (void *)(ANA_MIPI_CS1_BASE); + +#endif /* __SOC_MEDIATEK_MT8173_MIPI_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/pinmux.h b/src/soc/mediatek/mt8173/include/soc/pinmux.h new file mode 100644 index 0000000..846c693 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/pinmux.h @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef SOC_MEDIATEK_MT8173_PINMUX_H +#define SOC_MEDIATEK_MT8173_PINMUX_H + +#define PINMUX_CONSTANTS(index, name, func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name = index, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +enum { + PINMUX_CONSTANTS(0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20), + PINMUX_CONSTANTS(1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21), + PINMUX_CONSTANTS(2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22), + PINMUX_CONSTANTS(3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23), + PINMUX_CONSTANTS(4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7), + PINMUX_CONSTANTS(5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), + PINMUX_CONSTANTS(6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), + PINMUX_CONSTANTS(7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), + PINMUX_CONSTANTS(8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), + PINMUX_CONSTANTS(9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), + PINMUX_CONSTANTS(10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7), + PINMUX_CONSTANTS(11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), + PINMUX_CONSTANTS(12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32), + PINMUX_CONSTANTS(13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32), + PINMUX_CONSTANTS(14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6), + PINMUX_CONSTANTS(15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29), + PINMUX_CONSTANTS(16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7), + PINMUX_CONSTANTS(17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7), + PINMUX_CONSTANTS(38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7), + PINMUX_CONSTANTS(39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17), + PINMUX_CONSTANTS(40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18), + PINMUX_CONSTANTS(41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19), + PINMUX_CONSTANTS(42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7), + PINMUX_CONSTANTS(58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8), + PINMUX_CONSTANTS(59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9), + PINMUX_CONSTANTS(60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10), + PINMUX_CONSTANTS(61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11), + PINMUX_CONSTANTS(62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12), + PINMUX_CONSTANTS(63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13), + PINMUX_CONSTANTS(64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14), + PINMUX_CONSTANTS(65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16), + PINMUX_CONSTANTS(66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15), + PINMUX_CONSTANTS(67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17), + PINMUX_CONSTANTS(68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18), + PINMUX_CONSTANTS(69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19), + PINMUX_CONSTANTS(70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), + PINMUX_CONSTANTS(71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), + PINMUX_CONSTANTS(72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22), + PINMUX_CONSTANTS(73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24), + PINMUX_CONSTANTS(74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25), + PINMUX_CONSTANTS(75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26), + PINMUX_CONSTANTS(76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27), + PINMUX_CONSTANTS(77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28), + PINMUX_CONSTANTS(78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23), + PINMUX_CONSTANTS(79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31), + PINMUX_CONSTANTS(88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24), + PINMUX_CONSTANTS(93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25), + PINMUX_CONSTANTS(94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26), + PINMUX_CONSTANTS(95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27), + PINMUX_CONSTANTS(96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28), + PINMUX_CONSTANTS(97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29), + PINMUX_CONSTANTS(98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30), + PINMUX_CONSTANTS(99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31), + PINMUX_CONSTANTS(100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), + PINMUX_CONSTANTS(101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1), + PINMUX_CONSTANTS(102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2), + PINMUX_CONSTANTS(103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3), + PINMUX_CONSTANTS(104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), + PINMUX_CONSTANTS(105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), + PINMUX_CONSTANTS(106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), + PINMUX_CONSTANTS(109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), + PINMUX_CONSTANTS(110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), + PINMUX_CONSTANTS(111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), + PINMUX_CONSTANTS(112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), + PINMUX_CONSTANTS(113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0), + PINMUX_CONSTANTS(114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1), + PINMUX_CONSTANTS(115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2), + PINMUX_CONSTANTS(116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3), + PINMUX_CONSTANTS(117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9), + PINMUX_CONSTANTS(118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10), + PINMUX_CONSTANTS(119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11), + PINMUX_CONSTANTS(120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12), + PINMUX_CONSTANTS(121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), + PINMUX_CONSTANTS(122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14), + PINMUX_CONSTANTS(123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15), + PINMUX_CONSTANTS(124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), + PINMUX_CONSTANTS(125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4), + PINMUX_CONSTANTS(129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5), + PINMUX_CONSTANTS(130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6), + PINMUX_CONSTANTS(131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7), + PINMUX_CONSTANTS(132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8), + PINMUX_CONSTANTS(133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), + PINMUX_CONSTANTS(134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), +}; + +#endif /* SOC_MEDIATEK_MT8173_PINMUX_H */

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coreboot-gerrit December 2015