the following patch was just integrated into master:
commit d808017760a9f9ecd1e6820dd5a92d14f14c6146
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Nov 26 19:12:44 2015 -0700
kconfig_lint: Separate errors from warnings
- Create subroutines for printing warnings and errors
- Change all the existing warning and error routines to use subroutines
- Add new command line options to suppress errors and to print notes
Change-Id: I04893faffca21c5bb7b51be920cca4620dc283c3
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/12555
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12555 for details.
-gerrit
the following patch was just integrated into master:
commit cacbcf481513b69fe379058803800731b85d2660
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Nov 16 22:33:48 2015 -0700
coreinfo: use coreboot crosscompiler
Set up coreinfo makefile to use .xcompile and the coreboot 32-bit cross
compiler toolchain.
Restrict to x86_32 gcc compiler.
Tested in QEMU
Change-Id: I1cc180a5eeaf6cb9a36fdcef70a9819d0f459168
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/12454
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor(a)bsi.bund.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12454 for details.
-gerrit
the following patch was just integrated into master:
commit 89b4abdf80ae64374f378058bc3f2f5484a7f977
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Tue Dec 1 18:34:42 2015 +0100
build system: replace files on UPDATE_IMAGE
So far the build system only added files starting with CBFS_PREFIX/ in
the UPDATE_IMAGE configuration, but there are a number of files that
exist in the global namespace (eg. config, revision, but also
cmos_layout.bin).
Now, existing files are removed if necessary.
Change-Id: I977ff85fe18115c84268103be72e91ca854e62a4
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/12581
Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Tested-by: BSI firmware lab <coreboot-labor(a)bsi.bund.de>
See https://review.coreboot.org/12581 for details.
-gerrit
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12621
-gerrit
commit 0e9b16390e1f8d0c6d38b779e0fdd3909aad9887
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Wed Dec 2 14:03:02 2015 +1100
mainboard/intel/d510mo: Licence fixes and azalia verb table
Azalia verb table replicated from vendor bios.
Licence headers added where appropriate.
Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/mainboard/intel/d510mo/cstates.c | 15 +++++++++++++++
src/mainboard/intel/d510mo/hda_verb.c | 36 +++++++++++++++++++++++++++++++++--
src/mainboard/intel/d510mo/romstage.c | 4 ++--
3 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c
index 2d543ff..b7eb6df 100644
--- a/src/mainboard/intel/d510mo/cstates.c
+++ b/src/mainboard/intel/d510mo/cstates.c
@@ -1,3 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <device/device.h>
#include <arch/x86/include/arch/acpigen.h>
diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c
index 072a306..a0dba38 100644
--- a/src/mainboard/intel/d510mo/hda_verb.c
+++ b/src/mainboard/intel/d510mo/hda_verb.c
@@ -1,7 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
#include <device/azalia_device.h>
-const u32 cim_verb_data[0] = {};
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0662,
+ 0x8086d618, // Subsystem ID
+ 0x0000000a, // Number of entries
-const u32 pc_beep_verbs[0] = {};
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19841),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214420),
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4015c603),
+ AZALIA_PIN_CFG(0, 0x1e, 0x99430130),
+};
+const u32 pc_beep_verbs[] = {
+};
AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index b0bd0c0..f6e957e 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -125,9 +125,9 @@ void main(unsigned long bist)
post_code(0x30);
- printk(BIOS_DEBUG, "Start native raminit\n");
+ printk(BIOS_DEBUG, "Initializing memory\n");
sdram_initialize(0, spd_addrmap);
- printk(BIOS_DEBUG, "Native raminit done\n");
+ printk(BIOS_DEBUG, "Memory initialized\n");
post_code(0x31);
ram_check(0x200000,0x300000);
the following patch was just integrated into master:
commit d9c193d8b3bcc73dff4f6085c5b6164c0f6a4108
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Nov 26 22:34:42 2015 -0700
toolchain.inc: Add IASL test as part of coreboot toolchain
Even though coreboot has IASL as part of its toolchain, it was not being
picked up when testing to make sure coreboot is being compiled with
the coreboot toolchain.
This patch adds an iasl test when testing coreboot toolchain.
Change-Id: I5b989869417c3f60057a91842b911855d9528f1b
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/12543
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/12543 for details.
-gerrit
the following patch was just integrated into master:
commit 335a9b61b3856486645727dfdef8ed32b036c860
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Nov 25 12:44:15 2015 -0700
toolchain.inc: Improve help messages for coreboot toolchain
Show better help text on how to compile the coreboot toolchain or use
an unsupported toolchain.
Change-Id: I64a2159d324d673784669b2464c1a2769b048678
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/12557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/12557 for details.
-gerrit