coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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752 discussions

New patch to review for coreboot: util/board_status: Fix a couple of ugly wiki lines
by Timothy Pearson 03 Dec '15

03 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12631 -gerrit commit 487cecabd4a93b7efe9b6d4cbdb34f24bf44b535 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Dec 2 18:07:22 2015 -0600 util/board_status: Fix a couple of ugly wiki lines Change-Id: I3881a27060c0cd66a7228d201f477e89f364daca Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/board_status/to-wiki/towiki.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index e46d606..922e470 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -221,7 +221,7 @@ EOF northbridge="$(sed -n "/^[[:space:]]*select NORTHBRIDGE_/ s,^[[:space:]]*select NORTHBRIDGE_,,p" "$vendor_board_dir/Kconfig")" northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_PI_$.*$,AMD \1 (PI),g;s,INTEL_FSP_$.*$,Intel® \1 (FSP),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel®,g;')" - southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_ISA_DMA_INIT)" + southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_|grep -v DISABLE_)" southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" @@ -242,7 +242,7 @@ EOF AMD_SOCKET_S1G1) cpu_nice="AMD Turion™ / X2 Sempron™"; socket_nice="Socket S1G1";; - AMD_SOCKET_G34) + AMD_SOCKET_G34|AMD_SOCKET_G34_NON_AGESA) cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; socket_nice="Socket G34";; AMD_SOCKET_C32|AMD_SOCKET_C32_NON_AGESA)

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New patch to review for coreboot: Rangeley: Change A, A, A, A IRQ routing to A, A, A, B
by Martin Roth 02 Dec '15

02 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12630 -gerrit commit 4663f2ed83885baac6b89565d4750d0025c38901 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 2 16:24:00 2015 -0700 Rangeley: Change A, A, A, A IRQ routing to A, A, A, B Devices that have their IRQ routing set to A, A, A, A don't get an IRQ value assigned because that series evaluates to 0. The code that sets the IRQ values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused IRQs from A to any other value, it assigns the values correctly. This issue did not affect ACPI IRQ routing. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/irqroute.h | 6 +++--- src/mainboard/intel/mohonpeak/irqroute.h | 8 +++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/littleplains/irqroute.h b/src/mainboard/intel/littleplains/irqroute.h index 2f18345..5f0794a 100644 --- a/src/mainboard/intel/littleplains/irqroute.h +++ b/src/mainboard/intel/littleplains/irqroute.h @@ -41,12 +41,12 @@ PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* @@ -66,4 +66,4 @@ PIRQ_PIC(G, 14), \ PIRQ_PIC(H, 15) -#endif /* IRQROUTE_H */ \ No newline at end of file +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h index 2f18345..913ae52 100644 --- a/src/mainboard/intel/mohonpeak/irqroute.h +++ b/src/mainboard/intel/mohonpeak/irqroute.h @@ -34,6 +34,8 @@ * IR13h SATA3.0 INT(A) - PIRQ A * IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + + /* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ @@ -41,12 +43,12 @@ PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* @@ -66,4 +68,4 @@ PIRQ_PIC(G, 14), \ PIRQ_PIC(H, 15) -#endif /* IRQROUTE_H */ \ No newline at end of file +#endif /* IRQROUTE_H */

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New patch to review for coreboot: fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, B
by Martin Roth 02 Dec '15

02 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12629 -gerrit commit 34da6e70e209da9de1bd8a201562dcdc59778fa9 Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 2 16:20:53 2015 -0700 fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, B Devices that have their IRQ routing set to A, A, A, A don't get an IRQ value assigned because that series evaluates to 0. The code that sets the IRQ values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused IRQs from A to any other value, it assigns the values correctly. This issue did not affect ACPI IRQ routing. Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/bayleybay_fsp/irqroute.h | 3 ++- src/mainboard/intel/minnowmax/irqroute.h | 3 ++- src/mainboard/siemens/mc_tcu3/irqroute.h | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h index e3523e9..8b6a46e 100644 --- a/src/mainboard/intel/bayleybay_fsp/irqroute.h +++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h @@ -44,8 +44,9 @@ #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h index bdf3d94..4242acf 100644 --- a/src/mainboard/intel/minnowmax/irqroute.h +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -45,8 +45,9 @@ #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h index e3523e9..8b6a46e 100644 --- a/src/mainboard/siemens/mc_tcu3/irqroute.h +++ b/src/mainboard/siemens/mc_tcu3/irqroute.h @@ -44,8 +44,9 @@ #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \

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New patch to review for coreboot: mainboard/asus/kgpe-d16: Enable romstage spinlocks
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12628 -gerrit commit f0c6b62cf3c86d3d0a484b227c4c5b9b673e70f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Nov 5 13:16:55 2015 -0600 mainboard/asus/kgpe-d16: Enable romstage spinlocks Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 1 + src/mainboard/asus/kgpe-d16/romstage.c | 20 +++++++++++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index c4f3962..67b43ca 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 select SUPERIO_NUVOTON_NCT5572D select PARALLEL_CPU_INIT + select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index df76ab4..13eacd2 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -312,6 +312,18 @@ static void execute_memory_test(void) } #endif +static spinlock_t printk_spinlock CAR_GLOBAL; + +spinlock_t* romstage_console_lock(void) +{ + return car_get_var_ptr(&printk_spinlock); +} + +void initialize_romstage_console_lock(void) +{ + car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED; +} + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { uint32_t esp; @@ -338,6 +350,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); + /* Initialize the printk spinlock */ + initialize_romstage_console_lock(); + /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); @@ -407,11 +422,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x36); /* Wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fix up prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ wait_all_core0_started(); /* run _early_setup before soft-reset. */

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Patch set updated for coreboot: southbridge/amd/sr5650: Add MCFG ACPI table support
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12050 -gerrit commit 88011581a36e2fdb25e54cb364915da95b275619 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 15:20:42 2015 -0500 southbridge/amd/sr5650: Add MCFG ACPI table support Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--- src/southbridge/amd/rs780/rs780.c | 12 ++++ src/southbridge/amd/sb700/lpc.c | 6 -- src/southbridge/amd/sb800/lpc.c | 7 +- src/southbridge/amd/sr5650/Kconfig | 9 +++ src/southbridge/amd/sr5650/ht.c | 107 ++++++++++++++++++++++++++++- src/southbridge/amd/sr5650/sr5650.c | 18 +++++ 7 files changed, 156 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c8bf8fa..b376171 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -737,16 +737,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_MMCONF_SUPPORT - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); -#endif + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT) && !IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); + } if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c82a629..6eb4295 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -349,6 +350,17 @@ void rs780_enable(device_t dev) } } +#if !IS_ENABLED(CONFIG_AMD_SB_CIMX) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* FIXME + * Leave table blank until proper contents + * are determined. + */ + return current; +} +#endif + struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("ATI RS780") .enable_dev = rs780_enable, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a71fe1f..78933fa 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -30,12 +30,6 @@ #include <cpu/amd/powernow.h> #include "sb700.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 756a0c4..18d4471 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,6 @@ #include <arch/acpi.h> #include "sb800.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig index 29017c6..f2d12ff 100644 --- a/src/southbridge/amd/sr5650/Kconfig +++ b/src/southbridge/amd/sr5650/Kconfig @@ -15,3 +15,12 @@ config SOUTHBRIDGE_AMD_SR5650 bool + +if SOUTHBRIDGE_AMD_SR5650 +config EXT_CONF_SUPPORT + bool "Enable PCI-E MMCONFIG support" + default n + help + Select to enable PCI-E MMCONFIG support on the SR5650. + +endif diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 6119985..e74d36b 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -20,7 +20,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/ioapic.h> +#include <lib.h> #include "sr5650.h" +#include "cmn.h" /* Table 6-6 Recommended Interrupt Routing Configuration */ typedef struct _apic_device_info { @@ -154,11 +156,29 @@ static void pcie_init(struct device *dev) static void sr5690_read_resource(struct device *dev) { + struct resource *res; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + } + pci_dev_read_resources(dev); /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + res = new_resource(dev, 0x1c); /* PCIe MCFG space */ + res->base = EXT_CONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_ASSIGNED | IORESOURCE_RESERVE | IORESOURCE_BRIDGE; + } compact_resources(dev); } @@ -166,7 +186,88 @@ static void sr5690_read_resource(struct device *dev) /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ static void sr5690_set_resources(struct device *dev) { - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + uint32_t reg; + device_t amd_ht_cfg_dev; + device_t amd_addr_map_dev; + resource_t res_base; + resource_t res_end; + uint32_t base; + uint32_t limit; + struct resource *res; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + + res = probe_resource(dev, 0x1c); + if (res) { + /* Find requisite AMD CPU devices */ + amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + if (!amd_ht_cfg_dev || !amd_addr_map_dev) { + printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); + } + else { + /* Set up MMCONFIG bus range */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ + pci_write_config32(dev, 0x1c, res->base); + + /* Enable MMCONFIG decoding. */ + set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + + /* Set up nonposted resource in MMIO space */ + res_base = res->base; /* Get the base address */ + res_end = resource_end(res); /* Get the limit (rounded up) */ + printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); + + /* Locate an unused MMIO resource */ + for (reg = 0xb8; reg >= 0x80; reg -= 8) { + base = pci_read_config32(amd_addr_map_dev, reg); + limit = pci_read_config32(amd_addr_map_dev, reg + 4); + if (!(base & 0x3)) + break; /* Unused resource found */ + } + + /* If an unused MMIO resource was available, set up the mapping */ + if (!(base & 0x3)) { + uint32_t sblk; + + /* Remember this resource has been stored. */ + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " <mmconfig>"); + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; + + /* Calculate the MMIO mapping base */ + base &= 0x000000f0; + base |= ((res_base >> 8) & 0xffffff00); + base |= 3; + + /* Calculate the MMIO mapping limit */ + limit &= 0x00000048; + limit |= ((res_end >> 8) & 0xffffff00); + limit |= (sblk << 4); + limit |= (1 << 7); + + /* Configure and enable MMIO mapping */ + printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); + pci_write_config32(amd_addr_map_dev, reg + 4, limit); + pci_write_config32(amd_addr_map_dev, reg, base); + } + else { + printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); + } + } + } + } + pci_dev_set_resources(dev); } diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 07b4a02..54f0071 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -796,6 +796,24 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, i free(root_level); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Report MMCONF base */ + res = probe_resource(dev, 0x1c); + if (res) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); + } + + return current; +} + static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) { uint8_t *p;

1 0

Patch set updated for coreboot: northbridge/amd/amdht: Reduce excessive romstage array size
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12573 -gerrit commit c0beb74cc125e3110f3af3b3843aac5852583d41 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Nov 16 11:48:38 2015 -0600 northbridge/amd/amdht: Reduce excessive romstage array size Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/ht_wrapper.c | 65 +++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 18c0ac4..f8ea854 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -90,28 +90,43 @@ static const char * event_class_string_decodes[] = { [HT_EVENT_CLASS_INFO] = "INFO" }; -static const char * event_string_decodes[] = { - [HT_EVENT_COH_EVENTS] = "HT_EVENT_COH_EVENTS", - [HT_EVENT_COH_NO_TOPOLOGY] = "HT_EVENT_COH_NO_TOPOLOGY", - [HT_EVENT_COH_LINK_EXCEED] = "HT_EVENT_COH_LINK_EXCEED", - [HT_EVENT_COH_FAMILY_FEUD] = "HT_EVENT_COH_FAMILY_FEUD", - [HT_EVENT_COH_NODE_DISCOVERED] = "HT_EVENT_COH_NODE_DISCOVERED", - [HT_EVENT_COH_MPCAP_MISMATCH] = "HT_EVENT_COH_MPCAP_MISMATCH", - [HT_EVENT_NCOH_EVENTS] = "HT_EVENT_NCOH_EVENTS", - [HT_EVENT_NCOH_BUID_EXCEED] = "HT_EVENT_NCOH_BUID_EXCEED", - [HT_EVENT_NCOH_LINK_EXCEED] = "HT_EVENT_NCOH_LINK_EXCEED", - [HT_EVENT_NCOH_BUS_MAX_EXCEED] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", - [HT_EVENT_NCOH_CFG_MAP_EXCEED] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", - [HT_EVENT_NCOH_DEVICE_FAILED] = "HT_EVENT_NCOH_DEVICE_FAILED", - [HT_EVENT_NCOH_AUTO_DEPTH] = "HT_EVENT_NCOH_AUTO_DEPTH", - [HT_EVENT_OPT_EVENTS] = "HT_EVENT_OPT_EVENTS", - [HT_EVENT_OPT_REQUIRED_CAP_RETRY] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", - [HT_EVENT_OPT_REQUIRED_CAP_GEN3] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", - [HT_EVENT_HW_EVENTS] = "HT_EVENT_HW_EVENTS", - [HT_EVENT_HW_SYNCHFLOOD] = "HT_EVENT_HW_SYNCHFLOOD", - [HT_EVENT_HW_HTCRC] = "HT_EVENT_HW_HTCRC" +typedef struct { + uint32_t code; + const char * string; +} event_string_decode_t; + +static const event_string_decode_t event_string_decodes[] = { + { HT_EVENT_COH_EVENTS, "HT_EVENT_COH_EVENTS" }, + { HT_EVENT_COH_NO_TOPOLOGY, "HT_EVENT_COH_NO_TOPOLOGY" }, + { HT_EVENT_COH_LINK_EXCEED, "HT_EVENT_COH_LINK_EXCEED" }, + { HT_EVENT_COH_FAMILY_FEUD, "HT_EVENT_COH_FAMILY_FEUD" }, + { HT_EVENT_COH_NODE_DISCOVERED, "HT_EVENT_COH_NODE_DISCOVERED" }, + { HT_EVENT_COH_MPCAP_MISMATCH, "HT_EVENT_COH_MPCAP_MISMATCH" }, + { HT_EVENT_NCOH_EVENTS, "HT_EVENT_NCOH_EVENTS" }, + { HT_EVENT_NCOH_BUID_EXCEED, "HT_EVENT_NCOH_BUID_EXCEED" }, + { HT_EVENT_NCOH_LINK_EXCEED, "HT_EVENT_NCOH_LINK_EXCEED" }, + { HT_EVENT_NCOH_BUS_MAX_EXCEED, "HT_EVENT_NCOH_BUS_MAX_EXCEED" }, + { HT_EVENT_NCOH_CFG_MAP_EXCEED, "HT_EVENT_NCOH_CFG_MAP_EXCEED" }, + { HT_EVENT_NCOH_DEVICE_FAILED, "HT_EVENT_NCOH_DEVICE_FAILED" }, + { HT_EVENT_NCOH_AUTO_DEPTH, "HT_EVENT_NCOH_AUTO_DEPTH" }, + { HT_EVENT_OPT_EVENTS, "HT_EVENT_OPT_EVENTS" }, + { HT_EVENT_OPT_REQUIRED_CAP_RETRY, "HT_EVENT_OPT_REQUIRED_CAP_RETRY" }, + { HT_EVENT_OPT_REQUIRED_CAP_GEN3, "HT_EVENT_OPT_REQUIRED_CAP_GEN3" }, + { HT_EVENT_HW_EVENTS, "HT_EVENT_HW_EVENTS" }, + { HT_EVENT_HW_SYNCHFLOOD, "HT_EVENT_HW_SYNCHFLOOD" }, + { HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" } }; +static const char * event_string_decode(uint32_t event) { + uint32_t i; + for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++) + if (event_string_decodes[i].code == event) + break; + if (i == ARRAY_SIZE(event_string_decodes)) + return NULL; + return event_string_decodes[i].string; +} + /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) */ @@ -146,7 +161,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: case HT_EVENT_COH_FAMILY_FEUD: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); break; case HT_EVENT_COH_NODE_DISCOVERED: { @@ -163,11 +178,11 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_NCOH_LINK_EXCEED: case HT_EVENT_NCOH_BUS_MAX_EXCEED: case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); break; case HT_EVENT_NCOH_DEVICE_FAILED: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", evt->node, evt->link, evt->depth, evt->attemptedBUID); @@ -176,7 +191,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) } case HT_EVENT_NCOH_AUTO_DEPTH: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; printk(log_level, ": node %d link %d depth: %d", evt->node, evt->link, evt->depth); @@ -189,7 +204,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_HW_EVENTS: case HT_EVENT_HW_SYNCHFLOOD: case HT_EVENT_HW_HTCRC: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); break; default: printk(log_level, "HT_EVENT_UNKNOWN");

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Enable CBFS spinlocks
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12062 -gerrit commit d53de0c5984082cf3be1e88840268efc77838aaf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 28 20:02:45 2015 -0500 mainboard/asus/kgpe-d16: Enable CBFS spinlocks Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 1 + src/mainboard/asus/kgpe-d16/romstage.c | 15 ++++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 67b43ca..49dd37b 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_NUVOTON_NCT5572D select PARALLEL_CPU_INIT select HAVE_ROMSTAGE_CONSOLE_SPINLOCK + select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 13eacd2..f9af195 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -324,6 +324,18 @@ void initialize_romstage_console_lock(void) car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED; } +static spinlock_t nvram_cbfs_spinlock CAR_GLOBAL; + +spinlock_t* romstage_nvram_cbfs_lock(void) +{ + return car_get_var_ptr(&nvram_cbfs_spinlock); +} + +void initialize_romstage_nvram_cbfs_lock(void) +{ + car_get_var(nvram_cbfs_spinlock) = SPIN_LOCK_UNLOCKED; +} + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { uint32_t esp; @@ -350,8 +362,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - /* Initialize the printk spinlock */ + /* Initialize the printk and nvram CBFS spinlocks */ initialize_romstage_console_lock(); + initialize_romstage_nvram_cbfs_lock(); /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */

1 0

Patch set updated for coreboot: src/console: Add x86 romstage spinlock option and printk spinlock support
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11958 -gerrit commit aaff81c9666d38136f7db227b0bd7b97a2747aa4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon May 18 16:04:10 2015 -0500 src/console: Add x86 romstage spinlock option and printk spinlock support This paves the way for AP printk spinlock on AMD platforms Change-Id: Ice42a0d3177736bf6e1bc601092e413601866f20 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 4 ++++ src/arch/x86/include/arch/smp/spinlock.h | 11 ++++++++++- src/console/printk.c | 15 +++++++++++++++ src/cpu/amd/car/post_cache_as_ram.c | 4 ++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 8439a00..b8da62a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -468,6 +468,10 @@ config HAVE_HARD_RESET This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code. +config HAVE_ROMSTAGE_CONSOLE_SPINLOCK + bool + default n + config HAVE_MONOTONIC_TIMER def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 32be2f2..74e532c 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#ifndef __PRE_RAM__ +#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -11,9 +11,18 @@ typedef struct { volatile unsigned int lock; } spinlock_t; +#ifdef __PRE_RAM__ +spinlock_t *romstage_console_lock(void); +void initialize_romstage_console_lock(void); +#endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } + +#ifndef __PRE_RAM__ #define DECLARE_SPIN_LOCK(x) static spinlock_t x = SPIN_LOCK_UNLOCKED; +#else +#define DECLARE_SPIN_LOCK(x) +#endif /* * Simple spin lock operations. There are two variants, one clears IRQ's diff --git a/src/console/printk.c b/src/console/printk.c index aab7ff5..99f90a8 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -2,6 +2,7 @@ * blatantly copied from linux/kernel/printk.c * * Copyright (C) 1991, 1992 Linus Torvalds + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * */ @@ -13,7 +14,9 @@ #include <stddef.h> #include <trace.h> +#if (!defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) DECLARE_SPIN_LOCK(console_lock) +#endif void do_putchar(unsigned char byte) { @@ -39,7 +42,13 @@ int do_printk(int msg_level, const char *fmt, ...) #endif DISABLE_TRACE; +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + spin_lock(romstage_console_lock()); +#endif +#else spin_lock(&console_lock); +#endif va_start(args, fmt); i = vtxprintf(wrap_putchar, fmt, args, NULL); @@ -47,7 +56,13 @@ int do_printk(int msg_level, const char *fmt, ...) console_tx_flush(); +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + spin_unlock(romstage_console_lock()); +#endif +#else spin_unlock(&console_lock); +#endif ENABLE_TRACE; return i; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index fb09cd4..8c5757e 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -76,6 +76,10 @@ static void prepare_ramstage_region(void *resume_backup_memory) memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); } +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) + initialize_romstage_console_lock(); +#endif + print_car_debug(" Done\n"); }

1 0

Patch set updated for coreboot: cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12063 -gerrit commit ae1951f21f2de178bcc298dedd9360dcd51aa5b5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 28 20:48:17 2015 -0500 cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 4 ++++ src/arch/x86/include/arch/smp/spinlock.h | 7 ++++++- src/cpu/amd/microcode/microcode.c | 24 +++++++++++++++++++++++- src/mainboard/asus/kgpe-d16/Kconfig | 1 + src/mainboard/asus/kgpe-d16/romstage.c | 15 ++++++++++++++- 5 files changed, 48 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 5c38b7e..ca29a16 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -476,6 +476,10 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK bool default n +config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK + bool + default n + config HAVE_MONOTONIC_TIMER def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 057d9e3..39a81d2 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,10 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) +#if !defined(__PRE_RAM__) \ + || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \ + || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \ + || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -16,6 +19,8 @@ spinlock_t *romstage_console_lock(void); void initialize_romstage_console_lock(void); spinlock_t* romstage_nvram_cbfs_lock(void); void initialize_romstage_nvram_cbfs_lock(void); +spinlock_t* romstage_microcode_cbfs_lock(void); +void initialize_romstage_microcode_cbfs_lock(void); #endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 37d395a..5f3280c 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -21,6 +21,12 @@ #include <cbfs.h> #include <arch/io.h> +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) +#include <smp/spinlock.h> +#endif +#endif + #define UCODE_DEBUG(fmt, args...) \ do { printk(BIOS_DEBUG, "[microcode] "fmt, ##args); } while(0) @@ -197,14 +203,30 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id) return; } +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + spin_lock(romstage_microcode_cbfs_lock()); +#endif +#endif + ucode = cbfs_boot_map_with_leak(microcode_cbfs_file[i], CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { UCODE_DEBUG("microcode file not found. Skipping updates.\n"); - +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + spin_unlock(romstage_microcode_cbfs_lock()); +#endif +#endif return; } amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); + +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK) + spin_unlock(romstage_microcode_cbfs_lock()); +#endif +#endif } } diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 49dd37b..f394ca9 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select PARALLEL_CPU_INIT select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK + select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index f9af195..09de4b5 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -336,6 +336,18 @@ void initialize_romstage_nvram_cbfs_lock(void) car_get_var(nvram_cbfs_spinlock) = SPIN_LOCK_UNLOCKED; } +static spinlock_t microcode_cbfs_spinlock CAR_GLOBAL; + +spinlock_t* romstage_microcode_cbfs_lock(void) +{ + return car_get_var_ptr(&microcode_cbfs_spinlock); +} + +void initialize_romstage_microcode_cbfs_lock(void) +{ + car_get_var(microcode_cbfs_spinlock) = SPIN_LOCK_UNLOCKED; +} + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { uint32_t esp; @@ -362,9 +374,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); - /* Initialize the printk and nvram CBFS spinlocks */ + /* Initialize the printk, nvram CBFS, and microcode CBFS spinlocks */ initialize_romstage_console_lock(); initialize_romstage_nvram_cbfs_lock(); + initialize_romstage_microcode_cbfs_lock(); /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */

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Patch set updated for coreboot: drivers/pc80: Add optional spinlock for nvram CBFS access
by Timothy Pearson 02 Dec '15

02 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12061 -gerrit commit 7d550a56d84f53334fb363e3149e7f8aa654bf05 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 28 19:52:05 2015 -0500 drivers/pc80: Add optional spinlock for nvram CBFS access When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/Kconfig | 4 +++ src/arch/x86/include/arch/smp/spinlock.h | 4 ++- src/cpu/amd/car/post_cache_as_ram.c | 3 +++ src/drivers/pc80/mc146818rtc.c | 43 ++++++++++++++++++++++++++++++-- 4 files changed, 51 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index b8da62a..5c38b7e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -472,6 +472,10 @@ config HAVE_ROMSTAGE_CONSOLE_SPINLOCK bool default n +config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK + bool + default n + config HAVE_MONOTONIC_TIMER def_bool n help diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 74e532c..057d9e3 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -1,7 +1,7 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H -#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) +#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) /* * Your basic SMP spinlocks, allowing only a single CPU anywhere @@ -14,6 +14,8 @@ typedef struct { #ifdef __PRE_RAM__ spinlock_t *romstage_console_lock(void); void initialize_romstage_console_lock(void); +spinlock_t* romstage_nvram_cbfs_lock(void); +void initialize_romstage_nvram_cbfs_lock(void); #endif #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 } diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 8c5757e..435fdcb 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -79,6 +79,9 @@ static void prepare_ramstage_region(void *resume_backup_memory) #if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) initialize_romstage_console_lock(); #endif +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + initialize_romstage_nvram_cbfs_lock(); +#endif print_car_debug(" Done\n"); } diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 0c95265..0afc12b 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,6 +34,11 @@ #define LB_CKS_LOC 0 #endif +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) +#include <smp/spinlock.h> +#endif +#endif static void cmos_reset_date(void) { @@ -204,6 +210,12 @@ enum cb_err get_option(void *dest, const char *name) if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE)) return CB_CMOS_OTABLE_DISABLED; +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + spin_lock(romstage_nvram_cbfs_lock()); +#endif +#endif + /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -213,6 +225,11 @@ enum cb_err get_option(void *dest, const char *name) if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + spin_unlock(romstage_nvram_cbfs_lock()); +#endif +#endif return CB_CMOS_LAYOUT_NOT_FOUND; } ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length); @@ -225,13 +242,35 @@ enum cb_err get_option(void *dest, const char *name) } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + spin_unlock(romstage_nvram_cbfs_lock()); +#endif +#endif return CB_CMOS_OPTION_NOT_FOUND; } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + spin_unlock(romstage_nvram_cbfs_lock()); +#endif +#endif return CB_CMOS_ACCESS_ERROR; - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) + } + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + spin_unlock(romstage_nvram_cbfs_lock()); +#endif +#endif return CB_CMOS_CHECKSUM_INVALID; + } +#ifdef __PRE_RAM__ +#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) + spin_unlock(romstage_nvram_cbfs_lock()); +#endif +#endif return CB_SUCCESS; }

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coreboot-gerrit December 2015