the following patch was just integrated into master:
commit 7a2963b86c4055ae4a929e633597ad92e7325109
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sat Nov 21 18:47:49 2015 -0800
google/glados: Disable kepler device
Disable the kepler device to save power and enable S0ix testing.
It has been disabled in the ME image and was not working anyway..
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54
Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313827
Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/12599
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/12599 for details.
-gerrit
the following patch was just integrated into master:
commit 5b242f6307f1824d0833f957b9829952fa5ad54e
Author: Saurabh Satija <saurabh.satija(a)intel.com>
Date: Mon Oct 26 15:00:46 2015 -0700
intel/kunimitsu: Coreboot GPIO changes for FAB 4.
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID,
AUDIO_IRQ and BOOT_BEEP.
BUG=chrome-os-partner:47513
BRANCH=none
TEST=Built for kunimitsu but not verified on Fab 4.
Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7
Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b
Original-Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311806
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Reviewed-on: https://review.coreboot.org/12600
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12600 for details.
-gerrit
the following patch was just integrated into master:
commit a8aef3acbc0aea2dd594f7133a7024f3babf764a
Author: Mary Ruthven <mruthven(a)chromium.org>
Date: Tue Nov 24 09:43:27 2015 -0800
cbfs_spi: Initialize spi_flash when initializing cbfs_cache
Most devices do not use SPI before they initialize CBMEM. This change
initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram
cbfs cache so it is not overwritten when boot_device_init is called
later.
BUG=chromium:210230
BRANCH=none
TEST=confirm that the first cbfs access can occur before RAM initialized
and after on panther and jerry.
Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec
Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0
Original-Signed-off-by: Mary Ruthven <mruthven(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/314311
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/12601
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12601 for details.
-gerrit
the following patch was just integrated into master:
commit 5e2cfb5cbb4dba71bb9963fa9a183beb1ed6f9d0
Author: Yidi Lin <yidi.lin(a)mediatek.com>
Date: Mon Nov 23 15:08:44 2015 +0800
mediatek/mt8173: move PRERAM_CBFS_CACHE from SRAM_L2C
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE
from SRAM_L2C to ensure that it can be switched correctly.
BRANCH=none
BUG=chrome-os-partner47952
TEST=none
Change-Id: I255a0116148777d384dda43682365a5e2375cb5d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792
Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51
Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313888
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/12602
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12602 for details.
-gerrit
the following patch was just integrated into master:
commit 8996084f82119564362b1f9cb28fcbb7d74b3188
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Sat Nov 21 18:40:19 2015 -0800
intel/skylake: Add ACPI device for audio controller
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if it has been set in NVS.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d
Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313824
Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/12597
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12597 for details.
-gerrit
the following patch was just integrated into master:
commit ad77bf93200cba5fd47378cbadfeb467f1fc4740
Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Date: Tue Oct 27 13:49:14 2015 -0700
intel/Kunimitsu: FAB 4 SPD changes
Updated Memory IDs and SKU IDs for FAB 4
Updated detection of single/dual channel memory to use SPD Index (Memory ID)
Added spd files for new dimms
Removed boardid.h as it is no longer needed
BUG=None
BRANCH=None
TEST=Tested on FAB4 SKU1 and SKU3
Change-Id: I60403c0e636ea28797d94cff9431af921631323e
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4
Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312546
Original-Commit-Ready: Freddy Paul <freddy.paul(a)intel.com>
Original-Tested-by: Freddy Paul <freddy.paul(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>
Reviewed-on: https://review.coreboot.org/12590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12590 for details.
-gerrit
the following patch was just integrated into master:
commit e1aceef9550fa2b857c7f1a38f0c9f81975d42ea
Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Date: Mon Nov 2 16:58:22 2015 -0800
intel/kunimitsu: FAB 4 update for Rcomp Target table
Changed index 3 to be an exception of the default Rcomp Value
BUG=None
BRANCH=None
TEST=Tested on FAB 4 SKU 1
Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622
Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312715
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Freddy Paul <freddy.paul(a)intel.com>
Reviewed-on: https://review.coreboot.org/12591
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12591 for details.
-gerrit
the following patch was just integrated into master:
commit a009158bf9f66c5c8cecaa0aeb0d74154ea4c862
Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Date: Fri Nov 6 13:18:27 2015 -0800
intel/kunimitsu: Updated Micron SPD data
Updated Micron SPD data to correct values
BUG=none
BRANCH=none
TEST=Tested on FAB 4 with Micron Dimm
CQ-DEPEND=CL:312546
Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735
Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313003
Original-Commit-Ready: Freddy Paul <freddy.paul(a)intel.com>
Original-Tested-by: Freddy Paul <freddy.paul(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/12592
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12592 for details.
-gerrit
the following patch was just integrated into master:
commit 1fc5d1f01a9888f9d4b0127c87834966f933124d
Author: david <david_wu(a)quantatw.com>
Date: Mon Nov 23 20:24:54 2015 +0800
google/lars: SPD change for Proto board
Update Memory ID for Proto board
Update detection of single/dual channel memory to use SPD Index (Memory ID)
Remove boardid.h as it is no longer needed
BUG=None
BRANCH=None
TEST=Build and Boot Lars (Proto)
Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8
Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f
Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313903
Original-Commit-Ready: David Wu <david_wu(a)quantatw.com>
Original-Tested-by: David Wu <david_wu(a)quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-on: https://review.coreboot.org/12593
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/12593 for details.
-gerrit