coreboot-gerrit December 2015

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Patch set updated for coreboot: esd/atom15: import esd atom15 board
by Michael Tasche 03 Dec '15

03 Dec '15

Michael Tasche (michael.tasche(a)esd.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12632 -gerrit commit 76da1ee3e90bd3e219abb9128ced82e749153cec Author: Michael Tasche <michael.tasche(a)esd.eu> Date: Thu Dec 3 17:07:01 2015 +0100 esd/atom15: import esd atom15 board This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche(a)esd.eu> --- src/mainboard/esd/Kconfig | 16 ++ src/mainboard/esd/Kconfig.name | 2 + src/mainboard/esd/atom15/Kconfig | 70 +++++++++ src/mainboard/esd/atom15/Kconfig.name | 2 + src/mainboard/esd/atom15/Makefile.inc | 17 ++ src/mainboard/esd/atom15/acpi/ec.asl | 0 src/mainboard/esd/atom15/acpi/mainboard.asl | 20 +++ src/mainboard/esd/atom15/acpi/superio.asl | 0 src/mainboard/esd/atom15/acpi_tables.c | 56 +++++++ src/mainboard/esd/atom15/board_info.txt | 4 + src/mainboard/esd/atom15/cmos.layout | 116 ++++++++++++++ src/mainboard/esd/atom15/devicetree.cb | 93 +++++++++++ src/mainboard/esd/atom15/dsdt.asl | 53 +++++++ src/mainboard/esd/atom15/fadt.c | 32 ++++ src/mainboard/esd/atom15/gpio.c | 231 ++++++++++++++++++++++++++++ src/mainboard/esd/atom15/irqroute.c | 18 +++ src/mainboard/esd/atom15/irqroute.h | 82 ++++++++++ src/mainboard/esd/atom15/mainboard.c | 41 +++++ src/mainboard/esd/atom15/romstage.c | 78 ++++++++++ 19 files changed, 931 insertions(+) diff --git a/src/mainboard/esd/Kconfig b/src/mainboard/esd/Kconfig new file mode 100644 index 0000000..3b9eb58 --- /dev/null +++ b/src/mainboard/esd/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ESD + +choice + prompt "Mainboard model" + +source "src/mainboard/esd/*/Kconfig.name" + +endchoice + +source "src/mainboard/esd/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "esd" + +endif # VENDOR_ESD diff --git a/src/mainboard/esd/Kconfig.name b/src/mainboard/esd/Kconfig.name new file mode 100644 index 0000000..55fe27f --- /dev/null +++ b/src/mainboard/esd/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ESD + bool "esd electronic system design" diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig new file mode 100644 index 0000000..3f4b76b --- /dev/null +++ b/src/mainboard/esd/atom15/Kconfig @@ -0,0 +1,70 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ESD_ATOM15 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select TSC_MONOTONIC_TIMER + select HAVE_ACPI_RESUME + +config MAINBOARD_DIR + string + default "esd/atom15" + +config MAINBOARD_PART_NUMBER + string + default "esd atom15" + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_FILE + string + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + +config CBFS_SIZE + hex + default 0x00300000 + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default y if FSP_PACKAGE_DEFAULT + +endif # BOARD_ESD_ATOM15 diff --git a/src/mainboard/esd/atom15/Kconfig.name b/src/mainboard/esd/atom15/Kconfig.name new file mode 100644 index 0000000..cab7e86 --- /dev/null +++ b/src/mainboard/esd/atom15/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ESD_ATOM15 + bool "Atom15" diff --git a/src/mainboard/esd/atom15/Makefile.inc b/src/mainboard/esd/atom15/Makefile.inc new file mode 100644 index 0000000..3074df2 --- /dev/null +++ b/src/mainboard/esd/atom15/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +ramstage-y += irqroute.c diff --git a/src/mainboard/esd/atom15/acpi/ec.asl b/src/mainboard/esd/atom15/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/esd/atom15/acpi/mainboard.asl b/src/mainboard/esd/atom15/acpi/mainboard.asl new file mode 100644 index 0000000..b032ee1 --- /dev/null +++ b/src/mainboard/esd/atom15/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/esd/atom15/acpi/superio.asl b/src/mainboard/esd/atom15/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/esd/atom15/acpi_tables.c b/src/mainboard/esd/atom15/acpi_tables.c new file mode 100644 index 0000000..48991f5 --- /dev/null +++ b/src/mainboard/esd/atom15/acpi_tables.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> // hexdump +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> +#include <baytrail/iomap.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* No TPM Present */ + gnvs->tpmp = 0; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/esd/atom15/board_info.txt b/src/mainboard/esd/atom15/board_info.txt new file mode 100644 index 0000000..b5099b3 --- /dev/null +++ b/src/mainboard/esd/atom15/board_info.txt @@ -0,0 +1,4 @@ +Category: sbc +ROM protocol: SPI +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout new file mode 100644 index 0000000..8aaa522 --- /dev/null +++ b/src/mainboard/esd/atom15/cmos.layout @@ -0,0 +1,116 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1719 64 h 0 timestamp_value1 +1783 64 h 0 timestamp_value2 +1847 64 h 0 timestamp_value3 +1911 64 h 0 timestamp_value4 +1975 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/esd/atom15/devicetree.cb b/src/mainboard/esd/atom15/devicetree.cb new file mode 100644 index 0000000..4a51158 --- /dev/null +++ b/src/mainboard/esd/atom15/devicetree.cb @@ -0,0 +1,93 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/fsp_baytrail + + #### ACPI Register Settings #### + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + #### FSP register settings #### + register "PcdSataMode" = "SATA_MODE_AHCI" + register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" + register "PcdGttSize" = "GTT_SIZE_DEFAULT" + register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_4G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "8" + register "DIMMtRPtRCD" = "8" + register "DIMMtWR" = "8" + register "DIMMtWTR" = "4" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "4" + register "DIMMtFAW" = "27" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router - + device pci 02.0 off end # 8086 0F31 - GFX micro HDMI + device pci 03.0 off end # 8086 0F38 - MIPI - + + device pci 10.0 off end # 8086 0F14 - EMMC Port - + device pci 11.0 off end # 8086 0F15 - SDIO Port - + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 off end # 8086 0F23 - SATA AHCI - + device pci 14.0 off end # 8086 0F35 - USB XHCI - + device pci 15.0 off end # 8086 0F28 - LP Engine Audio - + device pci 17.0 off end # 8086 0F50 - MMC Port - + device pci 18.0 on end # 8086 0F40 - SIO - DMA - + device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) - + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - + device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) - + device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) - + device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) - + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) - + device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) - + device pci 1a.0 off end # 8086 0F18 - TXE - + device pci 1b.0 off end # 8086 0F04 - HD Audio - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI + device pci 1e.0 on end # 8086 0F06 - SIO - DMA - + device pci 1e.1 on end # 8086 0F08 - PWM 1 - + device pci 1e.2 on end # 8086 0F09 - PWM 2 - + device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart + device pci 1e.4 off end # 8086 0F0C - HSUART 2 - + device pci 1e.5 off end # 8086 0F0E - SPI - + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl new file mode 100644 index 0000000..63b9d03 --- /dev/null +++ b/src/mainboard/esd/atom15/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/esd/atom15/fadt.c b/src/mainboard/esd/atom15/fadt.c new file mode 100644 index 0000000..38b9bfd --- /dev/null +++ b/src/mainboard/esd/atom15/fadt.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baytrail/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt,facs,dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c new file mode 100644 index 0000000..fe29bd5 --- /dev/null +++ b/src/mainboard/esd/atom15/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ + GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ + GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ + GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ + GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ + GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ + GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ + GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ + GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ + GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ + GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ + GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ + GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ + GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ + GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ + GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ + GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ + GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ + GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ + GPIO_FUNC1, /* GPIO_S0_SC[040] - TP12 (SD3_1P8EN) */ + GPIO_FUNC1, /* GPIO_S0_SC[041] - TP11 (/SD3_PWREN) */ + GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ + GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ + GPIO_NC, /* GPIO_S0_SC[055] - No Connect */ + GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ + GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ + GPIO_NC, /* GPIO_S0_SC[058] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[059] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[060] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ + GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ + GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ + GPIO_NC, /* GPIO_S0_SC[072] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[073] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[074] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[075] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[080] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[081] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[088] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[089] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ + GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ + GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ + GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_NC, /* GPIO_S5[00] - No Connect */ + GPIO_FUNC6, /* GPIO_S5[01] - PMC_WAKE_PCIE[1] */ + GPIO_FUNC6, /* GPIO_S5[02] - PMC_WAKE_PCIE[2] */ + GPIO_FUNC6, /* GPIO_S5[03] - PMC_WAKE_PCIE[3] */ + GPIO_NC, /* GPIO_S5[04] - No Connect */ + GPIO_NC, /* GPIO_S5[05] - No Connect */ + GPIO_NC, /* GPIO_S5[06] - No Connect */ + GPIO_NC, /* GPIO_S5[07] - No Connect */ + GPIO_NC, /* GPIO_S5[08] - No Connect */ + GPIO_NC, /* GPIO_S5[09] - No Connect */ + GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ + GPIO_NC, /* GPIO_S5[12] - No Connect */ + GPIO_NC, /* GPIO_S5[13] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ + GPIO_FUNC0, /* GPIO_S5[15] - PMC_WAKE_PCIE[0] */ + GPIO_FUNC(1, PULL_UP, 2K), /* GPIO_S5[16] - PMC_PWRBTN */ + GPIO_NC, /* GPIO_S5[17] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[18] - LPCPD_L (TP7) */ + GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ + GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ + GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ + GPIO_NC, /* GPIO_S5[22] - No Connect */ + GPIO_NC, /* GPIO_S5[23] - No Connect */ + GPIO_NC, /* GPIO_S5[24] - No Connect */ + GPIO_NC, /* GPIO_S5[25] - No Connect */ + GPIO_NC, /* GPIO_S5[26] - No Connect */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - EXP_GPIO1 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - EXP_GPIO2 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - EXP_GPIO3 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - EXP_GPIO4 */ + GPIO_NC, /* GPIO_S5[31] - No Connect */ + GPIO_NC, /* GPIO_S5[32] - No Connect */ + GPIO_NC, /* GPIO_S5[33] - No Connect */ + GPIO_NC, /* GPIO_S5[34] - No Connect */ + GPIO_NC, /* GPIO_S5[35] - No Connect */ + GPIO_NC, /* GPIO_S5[36] - No Connect */ + GPIO_NC, /* GPIO_S5[37] - No Connect */ + GPIO_NC, /* GPIO_S5[38] - No Connect */ + GPIO_NC, /* GPIO_S5[39] - No Connect */ + GPIO_NC, /* GPIO_S5[40] - No Connect */ + GPIO_NC, /* GPIO_S5[41] - No Connect */ + GPIO_NC, /* GPIO_S5[42] - No Connect */ + GPIO_NC, /* GPIO_S5[43] - No Connect */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/esd/atom15/irqroute.c b/src/mainboard/esd/atom15/irqroute.c new file mode 100644 index 0000000..db8c512 --- /dev/null +++ b/src/mainboard/esd/atom15/irqroute.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/esd/atom15/irqroute.h b/src/mainboard/esd/atom15/irqroute.h new file mode 100644 index 0000000..f866069 --- /dev/null +++ b/src/mainboard/esd/atom15/irqroute.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 3), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/esd/atom15/mainboard.c b/src/mainboard/esd/atom15/mainboard.c new file mode 100644 index 0000000..70f96fc --- /dev/null +++ b/src/mainboard/esd/atom15/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c new file mode 100644 index 0000000..230e228 --- /dev/null +++ b/src/mainboard/esd/atom15/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baytrail/romstage.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <baytrail/gpio.h> +#include "chip.h" + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry() +{ + +} + +/** + * Get function disables - most of these will be done automatically + * @param fd_mask + * @param fd2_mask + */ +void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +{ + +} + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ +void late_mainboard_romstage_entry() +{ + + configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + + printk(0, "SW450: %d %d %d %d\n", + read_ssus_gpio(27), + read_ssus_gpio(28), + read_ssus_gpio(29), + read_ssus_gpio(30) ); + +} + +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + u8 use_xhci = UpdData->PcdEnableXhci; + + /* Update XHCI UPD value if required */ + get_option(&use_xhci, "use_xhci_over_ehci"); + if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { + UpdData->PcdEnableXhci = use_xhci; + printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", + UpdData->PcdEnableXhci?"Enabled":"Disabled"); + } + + return; +}

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Patch set updated for coreboot: fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, B
by Martin Roth 03 Dec '15

03 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12629 -gerrit commit 468d67222d3da2b9949336637194918316a14b0f Author: Martin Roth <martinroth(a)google.com> Date: Wed Dec 2 16:20:53 2015 -0700 fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, B Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/bayleybay_fsp/irqroute.h | 3 ++- src/mainboard/intel/minnowmax/irqroute.h | 3 ++- src/mainboard/siemens/mc_tcu3/irqroute.h | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h index e3523e9..8b6a46e 100644 --- a/src/mainboard/intel/bayleybay_fsp/irqroute.h +++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h @@ -44,8 +44,9 @@ #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h index bdf3d94..4242acf 100644 --- a/src/mainboard/intel/minnowmax/irqroute.h +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -45,8 +45,9 @@ #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h index e3523e9..8b6a46e 100644 --- a/src/mainboard/siemens/mc_tcu3/irqroute.h +++ b/src/mainboard/siemens/mc_tcu3/irqroute.h @@ -44,8 +44,9 @@ #define PCIE_BRIDGE_IRQ_ROUTES \ PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \

1 0

New patch to review for coreboot: esd/atom15: import esd atom15 board
by Michael Tasche 03 Dec '15

03 Dec '15

Michael Tasche (michael.tasche(a)esd.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12632 -gerrit commit f990dce070b25364426cb61c72751802e3f41bc3 Author: Michael Tasche <michael.tasche(a)esd.eu> Date: Thu Dec 3 17:07:01 2015 +0100 esd/atom15: import esd atom15 board This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche(a)esd.eu> --- src/mainboard/esd/Kconfig | 16 ++ src/mainboard/esd/Kconfig.name | 2 + src/mainboard/esd/atom15/Kconfig | 70 +++++++++ src/mainboard/esd/atom15/Kconfig.name | 2 + src/mainboard/esd/atom15/Makefile.inc | 17 ++ src/mainboard/esd/atom15/acpi/ec.asl | 0 src/mainboard/esd/atom15/acpi/mainboard.asl | 20 +++ src/mainboard/esd/atom15/acpi/superio.asl | 0 src/mainboard/esd/atom15/acpi_tables.c | 56 +++++++ src/mainboard/esd/atom15/board_info.txt | 4 + src/mainboard/esd/atom15/cmos.layout | 116 ++++++++++++++ src/mainboard/esd/atom15/devicetree.cb | 93 +++++++++++ src/mainboard/esd/atom15/dsdt.asl | 53 +++++++ src/mainboard/esd/atom15/fadt.c | 32 ++++ src/mainboard/esd/atom15/gpio.c | 231 ++++++++++++++++++++++++++++ src/mainboard/esd/atom15/irqroute.c | 18 +++ src/mainboard/esd/atom15/irqroute.h | 82 ++++++++++ src/mainboard/esd/atom15/mainboard.c | 41 +++++ src/mainboard/esd/atom15/romstage.c | 78 ++++++++++ 19 files changed, 931 insertions(+) diff --git a/src/mainboard/esd/Kconfig b/src/mainboard/esd/Kconfig new file mode 100644 index 0000000..3b9eb58 --- /dev/null +++ b/src/mainboard/esd/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_ESD + +choice + prompt "Mainboard model" + +source "src/mainboard/esd/*/Kconfig.name" + +endchoice + +source "src/mainboard/esd/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "esd" + +endif # VENDOR_ESD diff --git a/src/mainboard/esd/Kconfig.name b/src/mainboard/esd/Kconfig.name new file mode 100644 index 0000000..55fe27f --- /dev/null +++ b/src/mainboard/esd/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_ESD + bool "esd electronic system design" diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig new file mode 100644 index 0000000..3f4b76b --- /dev/null +++ b/src/mainboard/esd/atom15/Kconfig @@ -0,0 +1,70 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ESD_ATOM15 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_FSP_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select TSC_MONOTONIC_TIMER + select HAVE_ACPI_RESUME + +config MAINBOARD_DIR + string + default "esd/atom15" + +config MAINBOARD_PART_NUMBER + string + default "esd atom15" + +config MAX_CPUS + int + default 16 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config FSP_FILE + string + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" + +config CBFS_SIZE + hex + default 0x00300000 + +config ENABLE_FSP_FAST_BOOT + bool + depends on HAVE_FSP_BIN + default y + +config VIRTUAL_ROM_SIZE + hex + depends on ENABLE_FSP_FAST_BOOT + default 0x800000 + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default y if FSP_PACKAGE_DEFAULT + +endif # BOARD_ESD_ATOM15 diff --git a/src/mainboard/esd/atom15/Kconfig.name b/src/mainboard/esd/atom15/Kconfig.name new file mode 100644 index 0000000..cab7e86 --- /dev/null +++ b/src/mainboard/esd/atom15/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ESD_ATOM15 + bool "Atom15" diff --git a/src/mainboard/esd/atom15/Makefile.inc b/src/mainboard/esd/atom15/Makefile.inc new file mode 100644 index 0000000..3074df2 --- /dev/null +++ b/src/mainboard/esd/atom15/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +ramstage-y += irqroute.c diff --git a/src/mainboard/esd/atom15/acpi/ec.asl b/src/mainboard/esd/atom15/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/esd/atom15/acpi/mainboard.asl b/src/mainboard/esd/atom15/acpi/mainboard.asl new file mode 100644 index 0000000..b032ee1 --- /dev/null +++ b/src/mainboard/esd/atom15/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/esd/atom15/acpi/superio.asl b/src/mainboard/esd/atom15/acpi/superio.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/esd/atom15/acpi_tables.c b/src/mainboard/esd/atom15/acpi_tables.c new file mode 100644 index 0000000..48991f5 --- /dev/null +++ b/src/mainboard/esd/atom15/acpi_tables.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <lib.h> // hexdump +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> +#include <baytrail/iomap.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* No TPM Present */ + gnvs->tpmp = 0; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/esd/atom15/board_info.txt b/src/mainboard/esd/atom15/board_info.txt new file mode 100644 index 0000000..b5099b3 --- /dev/null +++ b/src/mainboard/esd/atom15/board_info.txt @@ -0,0 +1,4 @@ +Category: sbc +ROM protocol: SPI +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout new file mode 100644 index 0000000..8aaa522 --- /dev/null +++ b/src/mainboard/esd/atom15/cmos.layout @@ -0,0 +1,116 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1719 64 h 0 timestamp_value1 +1783 64 h 0 timestamp_value2 +1847 64 h 0 timestamp_value3 +1911 64 h 0 timestamp_value4 +1975 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/esd/atom15/devicetree.cb b/src/mainboard/esd/atom15/devicetree.cb new file mode 100644 index 0000000..a1ba4d1 --- /dev/null +++ b/src/mainboard/esd/atom15/devicetree.cb @@ -0,0 +1,93 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2014 Intel Corporation +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/fsp_baytrail + + #### ACPI Register Settings #### + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" + + #### FSP register settings #### + register "PcdSataMode" = "SATA_MODE_AHCI" + register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" + register "PcdGttSize" = "GTT_SIZE_DEFAULT" + register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" + register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" + register "IgdRenderStandby" = "IGD_RENDER_STANDBY_ENABLE" + register "EnableMemoryDown" = "MEMORY_DOWN_ENABLE" + register "DRAMSpeed" = "DRAM_SPEED_1066MHZ" + register "DRAMType" = "DRAM_TYPE_DDR3L" + register "DIMM0Enable" = "DIMM0_ENABLE" + register "DIMM1Enable" = "DIMM1_DISABLE" + register "DIMMDWidth" = "DIMM_DWIDTH_X16" + register "DIMMDensity" = "DIMM_DENSITY_4G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT + register "DIMMBusWidth" = "DIMM_BUS_WIDTH_64BIT" + register "DIMMSides" = "DIMM_SIDES_1RANK" + register "DIMMtCL" = "8" + register "DIMMtRPtRCD" = "8" + register "DIMMtWR" = "8" + register "DIMMtWTR" = "4" + register "DIMMtRRD" = "6" + register "DIMMtRTP" = "4" + register "DIMMtFAW" = "27" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router - + device pci 02.0 off end # 8086 0F31 - GFX micro HDMI + device pci 03.0 off end # 8086 0F38 - MIPI - + + device pci 10.0 off end # 8086 0F14 - EMMC Port - + device pci 11.0 off end # 8086 0F15 - SDIO Port - + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 off end # 8086 0F23 - SATA AHCI - + device pci 14.0 off end # 8086 0F35 - USB XHCI - + device pci 15.0 off end # 8086 0F28 - LP Engine Audio - + device pci 17.0 off end # 8086 0F50 - MMC Port - + device pci 18.0 on end # 8086 0F40 - SIO - DMA - + device pci 18.1 on end # 8086 0F41 - I2C Port 1 (0) - + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - + device pci 18.3 on end # 8086 0F43 - I2C Port 3 (2) - + device pci 18.4 on end # 8086 0F44 - I2C Port 4 (3) - + device pci 18.5 on end # 8086 0F45 - I2C Port 5 (4) - + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) - + device pci 18.7 off end # 8086 0F47 - I2C Port 7 (6) - + device pci 1a.0 off end # 8086 0F18 - TXE - + device pci 1b.0 off end # 8086 0F04 - HD Audio - + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) - + device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) - + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) ETHERNET + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) CAN + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling EHCI + device pci 1e.0 on end # 8086 0F06 - SIO - DMA - + device pci 1e.1 on end # 8086 0F08 - PWM 1 - + device pci 1e.2 on end # 8086 0F09 - PWM 2 - + device pci 1e.3 on end # 8086 0F0A - HSUART 1 Alternate uart + device pci 1e.4 off end # 8086 0F0C - HSUART 2 - + device pci 1e.5 off end # 8086 0F0E - SPI - + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/esd/atom15/dsdt.asl b/src/mainboard/esd/atom15/dsdt.asl new file mode 100644 index 0000000..63b9d03 --- /dev/null +++ b/src/mainboard/esd/atom15/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/esd/atom15/fadt.c b/src/mainboard/esd/atom15/fadt.c new file mode 100644 index 0000000..38b9bfd --- /dev/null +++ b/src/mainboard/esd/atom15/fadt.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baytrail/acpi.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt,facs,dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/esd/atom15/gpio.c b/src/mainboard/esd/atom15/gpio.c new file mode 100644 index 0000000..fe29bd5 --- /dev/null +++ b/src/mainboard/esd/atom15/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, /* GPIO_S0_NC[00] - HDMI_HPD */ + GPIO_FUNC2, /* GPIO_S0_NC[01] - HDMI_DDCDAT */ + GPIO_FUNC2, /* GPIO_S0_NC[02] - HDMI_DDCCLK */ + GPIO_NC, /* GPIO_S0_NC[03] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[04] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[05] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[06] - No Connect */ + GPIO_FUNC2, /* GPIO_S0_NC[07] - DDI1_DDCDAT */ + GPIO_NC, /* GPIO_S0_NC[08] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[09] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[10] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[11] - No Connect */ + GPIO_FUNC(0, PULL_UP, 20K), /* GPIO_S0_NC[12] - TP15 */ + GPIO_NC, /* GPIO_S0_NC[13] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[14] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[15] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[16] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[17] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[18] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[19] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[20] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[21] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[22] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[23] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[24] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[25] - No Connect */ + GPIO_NC, /* GPIO_S0_NC[26] - No Connect */ + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX)*/ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, /* GPIO_S0_SC[000] - SATA_GP0 */ + GPIO_FUNC1, /* GPIO_S0_SC[001] - SATA_GP1 */ + GPIO_FUNC1, /* GPIO_S0_SC[002] - SATA_LED_B */ + GPIO_FUNC1, /* GPIO_S0_SC[003] - PCIE_CLKREQ_0 */ + GPIO_FUNC1, /* GPIO_S0_SC[004] - PCIE_CLKREQ_1 */ + GPIO_FUNC1, /* GPIO_S0_SC[005] - PCIE_CLKREQ_2 */ + GPIO_FUNC1, /* GPIO_S0_SC[006] - PCIE_CLKREQ_3 */ + GPIO_FUNC2, /* GPIO_S0_SC[007] - SD3_WP */ + GPIO_NC, /* GPIO_S0_SC[008] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[009] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[010] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[011] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[012] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[013] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[014] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[015] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[016] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[017] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[018] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[019] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[020] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[021] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[022] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[023] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[024] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[025] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[026] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[027] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[028] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[029] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[030] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[031] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[032] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[033] - SD3_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[034] - SD3_D0 */ + GPIO_FUNC1, /* GPIO_S0_SC[035] - SD3_D1 */ + GPIO_FUNC1, /* GPIO_S0_SC[036] - SD3_D2 */ + GPIO_FUNC1, /* GPIO_S0_SC[037] - SD3_D3 */ + GPIO_FUNC1, /* GPIO_S0_SC[038] - SD3_CD# */ + GPIO_FUNC1, /* GPIO_S0_SC[039] - SD3_CMD */ + GPIO_FUNC1, /* GPIO_S0_SC[040] - TP12 (SD3_1P8EN) */ + GPIO_FUNC1, /* GPIO_S0_SC[041] - TP11 (/SD3_PWREN) */ + GPIO_NC, /* GPIO_S0_SC[042] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[043] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[044] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[045] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[046] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[047] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[048] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[049] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[050] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[051] - PCU_SMB_DATA */ + GPIO_FUNC1, /* GPIO_S0_SC[052] - PCU_SMB_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[053] - PCU_SMB_ALERT */ + GPIO_FUNC1, /* GPIO_S0_SC[054] - ILB_8254_SPKR */ + GPIO_NC, /* GPIO_S0_SC[055] - No Connect */ + GPIO_FUNC0, /* GPIO_S0_SC[056] - GPIO_S0_SC_56 */ + GPIO_FUNC1, /* GPIO_S0_SC[057] - PCU_UART3_TXD */ + GPIO_NC, /* GPIO_S0_SC[058] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[059] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[060] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[061] - PCU_UART3_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[062] - LPE_I2S_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[063] - LPE_I2S_FRM */ + GPIO_FUNC1, /* GPIO_S0_SC[064] - LPE_I2S_DATIN */ + GPIO_FUNC1, /* GPIO_S0_SC[065] - LPE_I2S_DATOUT */ + GPIO_FUNC1, /* GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 */ + GPIO_FUNC1, /* GPIO_S0_SC[067] - SOC_SIO_SPI_MISO */ + GPIO_FUNC1, /* GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI */ + GPIO_FUNC1, /* GPIO_S0_SC[069] - SOC_SIO_SPI_CLK */ + GPIO_FUNC1, /* GPIO_S0_SC[070] - SIO_UART1_RXD */ + GPIO_FUNC1, /* GPIO_S0_SC[071] - SIO_UART1_TXD */ + GPIO_NC, /* GPIO_S0_SC[072] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[073] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[074] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[075] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[076] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[077] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[078] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[079] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[080] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[081] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[082] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[083] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[084] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[085] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[086] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[087] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[088] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[089] - No Connect */ + GPIO_FUNC1, /* GPIO_S0_SC[090] - EXP_I2C_SDA */ + GPIO_FUNC1, /* GPIO_S0_SC[091] - EXP_I2C_SCL */ + GPIO_FUNC1, /* GPIO_S0_SC[092] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[093] - 0R GND? */ + GPIO_FUNC1, /* GPIO_S0_SC[094] - SOC_PWM0 */ + GPIO_FUNC1, /* GPIO_S0_SC[095] - SOC_PWM1 */ + GPIO_NC, /* GPIO_S0_SC[096] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[097] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[098] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[099] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[100] - No Connect */ + GPIO_NC, /* GPIO_S0_SC[101] - No Connect */ + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_NC, /* GPIO_S5[00] - No Connect */ + GPIO_FUNC6, /* GPIO_S5[01] - PMC_WAKE_PCIE[1] */ + GPIO_FUNC6, /* GPIO_S5[02] - PMC_WAKE_PCIE[2] */ + GPIO_FUNC6, /* GPIO_S5[03] - PMC_WAKE_PCIE[3] */ + GPIO_NC, /* GPIO_S5[04] - No Connect */ + GPIO_NC, /* GPIO_S5[05] - No Connect */ + GPIO_NC, /* GPIO_S5[06] - No Connect */ + GPIO_NC, /* GPIO_S5[07] - No Connect */ + GPIO_NC, /* GPIO_S5[08] - No Connect */ + GPIO_NC, /* GPIO_S5[09] - No Connect */ + GPIO_OUT_HIGH, /* GPIO_S5[10] - GPIO_S5_10_UNLOCK */ + GPIO_FUNC0, /* GPIO_S5[11] - SUSPWRDNACK (TP14) */ + GPIO_NC, /* GPIO_S5[12] - No Connect */ + GPIO_NC, /* GPIO_S5[13] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[14] - GPIO_S514_J20 */ + GPIO_FUNC0, /* GPIO_S5[15] - PMC_WAKE_PCIE[0] */ + GPIO_FUNC(1, PULL_UP, 2K), /* GPIO_S5[16] - PMC_PWRBTN */ + GPIO_NC, /* GPIO_S5[17] - No Connect */ + GPIO_FUNC1, /* GPIO_S5[18] - LPCPD_L (TP7) */ + GPIO_FUNC0, /* GPIO_S5[19] - SOC_USB_HOST_OC0 */ + GPIO_FUNC0, /* GPIO_S5[20] - SOC_USB_HOST_OC1 */ + GPIO_FUNC0, /* GPIO_S5[21] - SOC_SPI_CS1B */ + GPIO_NC, /* GPIO_S5[22] - No Connect */ + GPIO_NC, /* GPIO_S5[23] - No Connect */ + GPIO_NC, /* GPIO_S5[24] - No Connect */ + GPIO_NC, /* GPIO_S5[25] - No Connect */ + GPIO_NC, /* GPIO_S5[26] - No Connect */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[27] - EXP_GPIO1 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[28] - EXP_GPIO2 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[29] - EXP_GPIO3 */ + GPIO_FUNC(0, PULL_DISABLE, 10K), /* GPIO_S5[30] - EXP_GPIO4 */ + GPIO_NC, /* GPIO_S5[31] - No Connect */ + GPIO_NC, /* GPIO_S5[32] - No Connect */ + GPIO_NC, /* GPIO_S5[33] - No Connect */ + GPIO_NC, /* GPIO_S5[34] - No Connect */ + GPIO_NC, /* GPIO_S5[35] - No Connect */ + GPIO_NC, /* GPIO_S5[36] - No Connect */ + GPIO_NC, /* GPIO_S5[37] - No Connect */ + GPIO_NC, /* GPIO_S5[38] - No Connect */ + GPIO_NC, /* GPIO_S5[39] - No Connect */ + GPIO_NC, /* GPIO_S5[40] - No Connect */ + GPIO_NC, /* GPIO_S5[41] - No Connect */ + GPIO_NC, /* GPIO_S5[42] - No Connect */ + GPIO_NC, /* GPIO_S5[43] - No Connect */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/esd/atom15/irqroute.c b/src/mainboard/esd/atom15/irqroute.c new file mode 100644 index 0000000..db8c512 --- /dev/null +++ b/src/mainboard/esd/atom15/irqroute.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/esd/atom15/irqroute.h b/src/mainboard/esd/atom15/irqroute.h new file mode 100644 index 0000000..f866069 --- /dev/null +++ b/src/mainboard/esd/atom15/irqroute.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/intel/fsp_baytrail/baytrail/irq.h> +#include <soc/intel/fsp_baytrail/baytrail/pci_devs.h> + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 3), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/esd/atom15/mainboard.c b/src/mainboard/esd/atom15/mainboard.c new file mode 100644 index 0000000..70f96fc --- /dev/null +++ b/src/mainboard/esd/atom15/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c new file mode 100644 index 0000000..2e6c9e0 --- /dev/null +++ b/src/mainboard/esd/atom15/romstage.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baytrail/romstage.h> +#include <drivers/intel/fsp1_0/fsp_util.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <baytrail/gpio.h> +#include "chip.h" + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry() +{ + +} + +/** + * Get function disables - most of these will be done automatically + * @param fd_mask + * @param fd2_mask + */ +void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +{ + +} + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ +void late_mainboard_romstage_entry() +{ + + configure_ssus_gpio(27, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(28, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(29, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + configure_ssus_gpio(30, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + + printk(0, "SW450: %d %d %d %d\n", + read_ssus_gpio(27), + read_ssus_gpio(28), + read_ssus_gpio(29), + read_ssus_gpio(30) ); + +} + +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + u8 use_xhci = UpdData->PcdEnableXhci; + + /* Update XHCI UPD value if required */ + get_option(&use_xhci, "use_xhci_over_ehci"); + if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { + UpdData->PcdEnableXhci = use_xhci; + printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", + UpdData->PcdEnableXhci?"Enabled":"Disabled"); + } + + return; +}

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Patch set updated for coreboot: northbridge/amd/amdht: Reduce excessive romstage array size
by Timothy Pearson 03 Dec '15

03 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12573 -gerrit commit 2622d7c017ba87392269729dca32caf9f7018a3e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Nov 16 11:48:38 2015 -0600 northbridge/amd/amdht: Reduce excessive romstage array size Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/ht_wrapper.c | 66 +++++++++++++++++++++------------- 1 file changed, 41 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 18c0ac4..32cf175 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -90,28 +90,44 @@ static const char * event_class_string_decodes[] = { [HT_EVENT_CLASS_INFO] = "INFO" }; -static const char * event_string_decodes[] = { - [HT_EVENT_COH_EVENTS] = "HT_EVENT_COH_EVENTS", - [HT_EVENT_COH_NO_TOPOLOGY] = "HT_EVENT_COH_NO_TOPOLOGY", - [HT_EVENT_COH_LINK_EXCEED] = "HT_EVENT_COH_LINK_EXCEED", - [HT_EVENT_COH_FAMILY_FEUD] = "HT_EVENT_COH_FAMILY_FEUD", - [HT_EVENT_COH_NODE_DISCOVERED] = "HT_EVENT_COH_NODE_DISCOVERED", - [HT_EVENT_COH_MPCAP_MISMATCH] = "HT_EVENT_COH_MPCAP_MISMATCH", - [HT_EVENT_NCOH_EVENTS] = "HT_EVENT_NCOH_EVENTS", - [HT_EVENT_NCOH_BUID_EXCEED] = "HT_EVENT_NCOH_BUID_EXCEED", - [HT_EVENT_NCOH_LINK_EXCEED] = "HT_EVENT_NCOH_LINK_EXCEED", - [HT_EVENT_NCOH_BUS_MAX_EXCEED] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", - [HT_EVENT_NCOH_CFG_MAP_EXCEED] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", - [HT_EVENT_NCOH_DEVICE_FAILED] = "HT_EVENT_NCOH_DEVICE_FAILED", - [HT_EVENT_NCOH_AUTO_DEPTH] = "HT_EVENT_NCOH_AUTO_DEPTH", - [HT_EVENT_OPT_EVENTS] = "HT_EVENT_OPT_EVENTS", - [HT_EVENT_OPT_REQUIRED_CAP_RETRY] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", - [HT_EVENT_OPT_REQUIRED_CAP_GEN3] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", - [HT_EVENT_HW_EVENTS] = "HT_EVENT_HW_EVENTS", - [HT_EVENT_HW_SYNCHFLOOD] = "HT_EVENT_HW_SYNCHFLOOD", - [HT_EVENT_HW_HTCRC] = "HT_EVENT_HW_HTCRC" +typedef struct { + uint32_t code; + const char * string; +} event_string_decode_t; + +static const event_string_decode_t event_string_decodes[] = { + { HT_EVENT_COH_EVENTS, "HT_EVENT_COH_EVENTS" }, + { HT_EVENT_COH_NO_TOPOLOGY, "HT_EVENT_COH_NO_TOPOLOGY" }, + { HT_EVENT_COH_LINK_EXCEED, "HT_EVENT_COH_LINK_EXCEED" }, + { HT_EVENT_COH_FAMILY_FEUD, "HT_EVENT_COH_FAMILY_FEUD" }, + { HT_EVENT_COH_NODE_DISCOVERED, "HT_EVENT_COH_NODE_DISCOVERED" }, + { HT_EVENT_COH_MPCAP_MISMATCH, "HT_EVENT_COH_MPCAP_MISMATCH" }, + { HT_EVENT_NCOH_EVENTS, "HT_EVENT_NCOH_EVENTS" }, + { HT_EVENT_NCOH_BUID_EXCEED, "HT_EVENT_NCOH_BUID_EXCEED" }, + { HT_EVENT_NCOH_LINK_EXCEED, "HT_EVENT_NCOH_LINK_EXCEED" }, + { HT_EVENT_NCOH_BUS_MAX_EXCEED, "HT_EVENT_NCOH_BUS_MAX_EXCEED" }, + { HT_EVENT_NCOH_CFG_MAP_EXCEED, "HT_EVENT_NCOH_CFG_MAP_EXCEED" }, + { HT_EVENT_NCOH_DEVICE_FAILED, "HT_EVENT_NCOH_DEVICE_FAILED" }, + { HT_EVENT_NCOH_AUTO_DEPTH, "HT_EVENT_NCOH_AUTO_DEPTH" }, + { HT_EVENT_OPT_EVENTS, "HT_EVENT_OPT_EVENTS" }, + { HT_EVENT_OPT_REQUIRED_CAP_RETRY, "HT_EVENT_OPT_REQUIRED_CAP_RETRY" }, + { HT_EVENT_OPT_REQUIRED_CAP_GEN3, "HT_EVENT_OPT_REQUIRED_CAP_GEN3" }, + { HT_EVENT_HW_EVENTS, "HT_EVENT_HW_EVENTS" }, + { HT_EVENT_HW_SYNCHFLOOD, "HT_EVENT_HW_SYNCHFLOOD" }, + { HT_EVENT_HW_HTCRC, "HT_EVENT_HW_HTCRC" } }; +static const char * event_string_decode(uint32_t event) { + uint32_t i; + for (i = 0; i < ARRAY_SIZE(event_string_decodes); i++) + if (event_string_decodes[i].code == event) + break; + if (i == ARRAY_SIZE(event_string_decodes)) + return "ERROR: Unmatched event code! " + "Did you forget to update event_string_decodes[]?"; + return event_string_decodes[i].string; +} + /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) */ @@ -146,7 +162,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: case HT_EVENT_COH_FAMILY_FEUD: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); break; case HT_EVENT_COH_NODE_DISCOVERED: { @@ -163,11 +179,11 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_NCOH_LINK_EXCEED: case HT_EVENT_NCOH_BUS_MAX_EXCEED: case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); break; case HT_EVENT_NCOH_DEVICE_FAILED: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", evt->node, evt->link, evt->depth, evt->attemptedBUID); @@ -176,7 +192,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) } case HT_EVENT_NCOH_AUTO_DEPTH: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; printk(log_level, ": node %d link %d depth: %d", evt->node, evt->link, evt->depth); @@ -189,7 +205,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_HW_EVENTS: case HT_EVENT_HW_SYNCHFLOOD: case HT_EVENT_HW_HTCRC: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decode(event)); break; default: printk(log_level, "HT_EVENT_UNKNOWN");

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Patch set updated for coreboot: util/board_status: Fix a couple of ugly wiki lines
by Timothy Pearson 03 Dec '15

03 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12631 -gerrit commit 90197c6003c56d587e3f328774202fd1d65ff9cc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Dec 2 18:07:22 2015 -0600 util/board_status: Fix a couple of ugly wiki lines Examples from the KGPE-D16 entry: AMD SR5650 AMD SB700 AMD SB700 DISABLE ISA DMA AMD SUBTYPE SP5100 AMD_SOCKET_G34_NON_AGESA Should be: AMD SR5650 AMD SB700 AMD SUBTYPE SP5100 AMD Opteron™ Magny-Cours/Interlagos Change-Id: I3881a27060c0cd66a7228d201f477e89f364daca Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/board_status/to-wiki/towiki.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index e46d606..922e470 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -221,7 +221,7 @@ EOF northbridge="$(sed -n "/^[[:space:]]*select NORTHBRIDGE_/ s,^[[:space:]]*select NORTHBRIDGE_,,p" "$vendor_board_dir/Kconfig")" northbridge_nice="$(echo "$northbridge"|sed 's,AMD_AGESA_FAMILY$[0-9a-fA-F]*$$.*$,AMD Family \1h\2 (AGESA),g;s,AMD_PI_$.*$,AMD \1 (PI),g;s,INTEL_FSP_$.*$,Intel® \1 (FSP),g;s,AMD_FAMILY$[0-9a-fA-F]*$,AMD Family \1h,g;s,AMD_AMDFAM$[0-9a-fA-F]*$,AMD Family \1h,g;s,_, ,g;s,INTEL,Intel®,g;')" - southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_ISA_DMA_INIT)" + southbridge="$(sed -n "/[[:space:]]*select SOUTHBRIDGE_/ s,[[:space:]]*select SOUTHBRIDGE_$[^ ]*$.*$,\1,p" "$vendor_board_dir/Kconfig"|grep -v SKIP_|grep -v DISABLE_)" southbridge_nice="$(echo "$southbridge"|sed 's,_, ,g;s,INTEL,Intel®,g')" superio="$(sed -n "/[[:space:]]*select SUPERIO_/ s,[[:space:]]*select SUPERIO_,,p" "$vendor_board_dir/Kconfig"|grep -v OVERRIDE_FANCTL)" superio_nice="$(echo "$superio"|sed 's,_, ,g;s,WINBOND,Winbond™,g;s,ITE,ITE™,g;s,SMSC,SMSC®,g;s,NUVOTON,Nuvoton ,g')" @@ -242,7 +242,7 @@ EOF AMD_SOCKET_S1G1) cpu_nice="AMD Turion™ / X2 Sempron™"; socket_nice="Socket S1G1";; - AMD_SOCKET_G34) + AMD_SOCKET_G34|AMD_SOCKET_G34_NON_AGESA) cpu_nice="AMD Opteron™ Magny-Cours/Interlagos"; socket_nice="Socket G34";; AMD_SOCKET_C32|AMD_SOCKET_C32_NON_AGESA)

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Patch merged into coreboot/master: google/chell: update dptf TSR1 & TSR2 critial points
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 1a8e43e4e3e081e8e6c9037bbef4a7a18a181309 Author: Wisley <wisley.chen(a)quantatw.com> Date: Tue Nov 24 20:12:36 2015 +0800 google/chell: update dptf TSR1 & TSR2 critial points update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie(a)chromium.org> Original-Tested-by: Chen Wisley <wisley.chen(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12604 for details. -gerrit

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Patch merged into coreboot/master: google/oak: Initialize the necessary pins
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 9d48e1732ad857a16fc60e0058894cbe01aca0bf Author: Biao Huang <biao.huang(a)mediatek.com> Date: Fri Jul 31 17:10:56 2015 +0800 google/oak: Initialize the necessary pins BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12605 for details. -gerrit

1 0

Patch merged into coreboot/master: google/oak: Implement the code which reads GPIOs for ChromeOS.
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 65873ca934937b414c65876f83bfb3b269594b80 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Jul 31 17:10:57 2015 +0800 google/oak: Implement the code which reads GPIOs for ChromeOS. BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12606 for details. -gerrit

1 0

Patch merged into coreboot/master: google/oak: Add board_id() and ram_code() implementation
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 86933f89c435268db6fb1d9247283c42a862ebc9 Author: CC Ma <cc.ma(a)mediatek.com> Date: Fri Jul 31 17:10:58 2015 +0800 google/oak: Add board_id() and ram_code() implementation BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12607 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Update mainboard for EVT
by gerrit＠coreboot.org 03 Dec '15

03 Dec '15

the following patch was just integrated into master: commit 4938feaee5b3b661bb73687b2625a73413084a53 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Nov 21 18:43:18 2015 -0800 google/chell: Update mainboard for EVT - Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12598 for details. -gerrit

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coreboot-gerrit December 2015