coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/fsp1_1: Add accurate print for full fsp version
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12594 -gerrit commit f7a7b7da799a6fee40c0fc92b9c58f936ca35100 Author: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Date: Mon Nov 2 17:12:10 2015 +0530 intel/fsp1_1: Add accurate print for full fsp version Adding print for full fsp revision which includes: 0:7 - Build number 8:15 - Revision 16:23 - Minor version 24:31 - Major version BRANCH=NONE BUG=chrome-os-partner:46050 TEST=Built for kunimitsu and tested fsp revision is printed properly. Change-Id: If2739e7cccd97e4b39da503a9d61222cde03bc95 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c49be46f8d2085a620abac74126de5c3b634e649 Original-Change-Id: I2223cce22fb3d39faa37902d415d5fdbe321add6 Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310173 Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma(a)intel.com> Original-Tested-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/fsp_util.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index a4b623d..21239bd 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -112,7 +112,9 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header) fsp_header->ImageId[6], fsp_header->ImageId[7]); printk(BIOS_INFO, "FSP Header Version: %d\n", fsp_header->HeaderRevision); - printk(BIOS_INFO, "FSP Revision: %d.%d\n", + printk(BIOS_INFO, "FSP Revision: %d.%d.%d.%d\n", + (u8)((fsp_header->ImageRevision >> 24) & 0xff), + (u8)((fsp_header->ImageRevision >> 16) & 0xff), (u8)((fsp_header->ImageRevision >> 8) & 0xff), (u8)(fsp_header->ImageRevision & 0xff)); #if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS)

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New patch to review for coreboot: google/lars: SPD change for Proto board
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12593 -gerrit commit e6debd0209c8a833707cca1f3ad117452a48f2d3 Author: david <david_wu(a)quantatw.com> Date: Mon Nov 23 20:24:54 2015 +0800 google/lars: SPD change for Proto board Update Memory ID for Proto board Update detection of single/dual channel memory to use SPD Index (Memory ID) Remove boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Build and Boot Lars (Proto) Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8 Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f Original-Signed-off-by: David Wu <David_Wu(a)quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313903 Original-Commit-Ready: David Wu <david_wu(a)quantatw.com> Original-Tested-by: David Wu <david_wu(a)quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- src/mainboard/google/lars/boardid.h | 27 --------------------------- src/mainboard/google/lars/spd/Makefile.inc | 8 ++++---- src/mainboard/google/lars/spd/spd.c | 27 ++++++++------------------- src/mainboard/google/lars/spd/spd.h | 1 + 4 files changed, 13 insertions(+), 50 deletions(-) diff --git a/src/mainboard/google/lars/boardid.h b/src/mainboard/google/lars/boardid.h deleted file mode 100644 index 0c6de8b..0000000 --- a/src/mainboard/google/lars/boardid.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef _BOARDID_H_ -#define _BOARDID_H_ - -#define SCRD_SKU1 0x3 -#define SCRD_SKU2 0x4 -#define SCRD_SKU3 0x1 -#define SCRD_SKU4 0x2 -#define SCRD_SKU5 0x5 -#define SCRD_SKU6 0x6 - -#endif diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc index cbe1c3d..4b9c376 100644 --- a/src/mainboard/google/lars/spd/Makefile.inc +++ b/src/mainboard/google/lars/spd/Makefile.inc @@ -18,10 +18,10 @@ romstage-y += spd.c SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000 -SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001 -SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010 -SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866 # 0b0011 +SPD_SOURCES = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0000 Single Channel 2GB +SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0001 Dual Channel 8GB +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866 # 0b0010 Dual Channel 4GB +SPD_SOURCES += empty # 0b0011 SPD_SOURCES += empty # 0b0100 SPD_SOURCES += empty # 0b0101 SPD_SOURCES += empty # 0b0110 diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c index d352969..b8d8cd0 100644 --- a/src/mainboard/google/lars/spd/spd.c +++ b/src/mainboard/google/lars/spd/spd.c @@ -15,14 +15,12 @@ */ #include <arch/byteorder.h> -#include <boardid.h> #include <cbfs.h> #include <console/console.h> #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> -#include "../boardid.h" #include "spd.h" static void mainboard_print_spd_info(uint8_t spd[]) @@ -81,17 +79,11 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) { char *spd_file; size_t spd_file_len; - int spd_index, sku_id; + int spd_index, spd_span; spd_index = pei_data->mem_cfg_id; - /* - * XXX: This is incorrect usage.The Board ID should be the revision ID - * and not SKU ID but on SCRD it indicates SKU. - */ - sku_id = board_id(); printk(BIOS_INFO, "SPD index %d\n", spd_index); - printk(BIOS_INFO, "Board ID %d\n", sku_id); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -110,16 +102,13 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) } /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - /* - * XXX: This is incorrect usage. mem_cfg should be used here instead of - * SKU ID. The current implementation of mem_config does not - * support channel population. - */ - - if (sku_id != SCRD_SKU1) - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); + spd_span = spd_index * SPD_LEN; + memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN); + + if (spd_index != HYNIX_SINGLE_CHAN) { + memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN); + printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n"); + } /* Make sure a valid SPD was found */ if (pei_data->spd_data[0][0][0] == 0) diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h index babadd2..c4b2b56 100644 --- a/src/mainboard/google/lars/spd/spd.h +++ b/src/mainboard/google/lars/spd/spd.h @@ -30,4 +30,5 @@ #define SPD_PART_LEN 18 #define SPD_MANU_OFF 148 +#define HYNIX_SINGLE_CHAN 0x0 #endif

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New patch to review for coreboot: intel/kunimitsu: Updated Micron SPD data
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12592 -gerrit commit ef3f8b4deed7a0d2cee0510b8074a38238add8d2 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Nov 6 13:18:27 2015 -0800 intel/kunimitsu: Updated Micron SPD data Updated Micron SPD data to correct values BUG=none BRANCH=none TEST=Tested on FAB 4 with Micron Dimm CQ-DEPEND=CL:312546 Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735 Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313003 Original-Commit-Ready: Freddy Paul <freddy.paul(a)intel.com> Original-Tested-by: Freddy Paul <freddy.paul(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- .../intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex b/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex index 2938c3b..e8d901c 100644 --- a/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex +++ b/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex @@ -1,13 +1,13 @@ -91 20 F1 03 04 12 05 02 03 11 01 08 09 00 00 05 +91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 00 05 78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 00 21 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2C 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 D3 41 +45 44 46 41 31 36 34 41 32 4D 41 2D 4A 44 2D 46 +20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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New patch to review for coreboot: intel/kunimitsu: FAB 4 update for Rcomp Target table
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12591 -gerrit commit 8eaf6d382e21afde436ec35f380dd036fc0334d0 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Nov 2 16:58:22 2015 -0800 intel/kunimitsu: FAB 4 update for Rcomp Target table Changed index 3 to be an exception of the default Rcomp Value BUG=None BRANCH=None TEST=Tested on FAB 4 SKU 1 Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622 Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312715 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Freddy Paul <freddy.paul(a)intel.com> --- src/mainboard/intel/kunimitsu/pei_data.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c index deb488e..3b0237e 100644 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ b/src/mainboard/intel/kunimitsu/pei_data.c @@ -23,6 +23,7 @@ /* PCH_MEM_CFG[3:0] */ #define MAX_MEMORY_CONFIG 0x10 #define RCOMP_TARGET_PARAMS 0x5 +#define K4E6E304EE_MEM_ID 0x3 void mainboard_fill_pei_data(struct pei_data *pei_data) { @@ -41,19 +42,24 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) const u16 RcompResistor[3] = { 200, 81, 162 }; /* Rcomp target */ - static const u16 RcompTarget[MAX_MEMORY_CONFIG][RCOMP_TARGET_PARAMS] = { - { 100, 40, 40, 23, 40 }, - { 100, 40, 40, 23, 40 }, - { 100, 40, 40, 23, 40 }, - /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ - { 100, 40, 40, 21, 40 }, }; + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ + static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 21, 40 }; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); memcpy(pei_data->RcompResistor, RcompResistor, sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, &RcompTarget[pei_data->mem_cfg_id][0], - sizeof(RcompTarget[pei_data->mem_cfg_id])); + if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) { + memcpy(pei_data->RcompTarget, StrengthendRcompTarget, + sizeof(StrengthendRcompTarget)); + } else { + memcpy(pei_data->RcompTarget, RcompTarget, + sizeof(RcompTarget)); + } }

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New patch to review for coreboot: intel/Kunimitsu: FAB 4 SPD changes
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12590 -gerrit commit 0fdd5c7872fc5d5704a913773e05cddf0115d41f Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Tue Oct 27 13:49:14 2015 -0700 intel/Kunimitsu: FAB 4 SPD changes Updated Memory IDs and SKU IDs for FAB 4 Updated detection of single/dual channel memory to use SPD Index (Memory ID) Added spd files for new dimms Removed boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Tested on FAB4 SKU1 and SKU3 Change-Id: I60403c0e636ea28797d94cff9431af921631323e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4 Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312546 Original-Commit-Ready: Freddy Paul <freddy.paul(a)intel.com> Original-Tested-by: Freddy Paul <freddy.paul(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/mainboard/intel/kunimitsu/boardid.h | 27 --------------------- src/mainboard/intel/kunimitsu/spd/Makefile.inc | 16 ++++++------- .../hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex | 16 +++++++++++++ .../hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex | 16 +++++++++++++ .../spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex | 16 +++++++++++++ src/mainboard/intel/kunimitsu/spd/spd.c | 28 +++++++--------------- src/mainboard/intel/kunimitsu/spd/spd.h | 3 +++ 7 files changed, 68 insertions(+), 54 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/boardid.h b/src/mainboard/intel/kunimitsu/boardid.h deleted file mode 100644 index 0c6de8b..0000000 --- a/src/mainboard/intel/kunimitsu/boardid.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef _BOARDID_H_ -#define _BOARDID_H_ - -#define SCRD_SKU1 0x3 -#define SCRD_SKU2 0x4 -#define SCRD_SKU3 0x1 -#define SCRD_SKU4 0x2 -#define SCRD_SKU5 0x5 -#define SCRD_SKU6 0x6 - -#endif diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index cdb84ab..6944664 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -18,14 +18,14 @@ romstage-y += spd.c SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0000 -SPD_SOURCES += hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866 # 0b0001 -SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF-1G-1866 # 0b0010 -SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF-2G-1866 # 0b0011 -SPD_SOURCES += empty # 0b0100 -SPD_SOURCES += empty # 0b0101 -SPD_SOURCES += empty # 0b0110 -SPD_SOURCES += empty # 0b0111 +SPD_SOURCES = hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0000 Dual Channel 4GB +SPD_SOURCES += hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866 # 0b0001 Single Channel 2GB +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF-1G-1866 # 0b0010 Dual Channel 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EE-EGCF-2G-1866 # 0b0011 Dual Channel 8GB +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCF-1G-1866 # 0b0100 Single Channel 4GB +SPD_SOURCES += mic_dimm_EDF8132A3MA-JD-F-1G-1866 # 0b0101 Single Channel 4GB SPD FILE NOT HERE YET +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866 # 0b0110 Dual Channel 4GB SPD FILE NOT HERE YET +SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866 # 0b0111 Dual Channel 8GB SPD FILE NOT HERE YET SPD_SOURCES += empty # 0b1000 SPD_SOURCES += empty # 0b1001 SPD_SOURCES += empty # 0b1010 diff --git a/src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex b/src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex new file mode 100644 index 0000000..a8e0c26 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 4A 54 42 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex b/src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex new file mode 100644 index 0000000..f777127 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 42 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex b/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex new file mode 100644 index 0000000..2938c3b --- /dev/null +++ b/src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 12 05 02 03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 21 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c index d352969..faf6791 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ b/src/mainboard/intel/kunimitsu/spd/spd.c @@ -15,14 +15,12 @@ */ #include <arch/byteorder.h> -#include <boardid.h> #include <cbfs.h> #include <console/console.h> #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> -#include "../boardid.h" #include "spd.h" static void mainboard_print_spd_info(uint8_t spd[]) @@ -81,17 +79,11 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) { char *spd_file; size_t spd_file_len; - int spd_index, sku_id; + int spd_index, spd_span; spd_index = pei_data->mem_cfg_id; - /* - * XXX: This is incorrect usage.The Board ID should be the revision ID - * and not SKU ID but on SCRD it indicates SKU. - */ - sku_id = board_id(); printk(BIOS_INFO, "SPD index %d\n", spd_index); - printk(BIOS_INFO, "Board ID %d\n", sku_id); /* Load SPD data from CBFS */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -110,16 +102,14 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) } /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - /* - * XXX: This is incorrect usage. mem_cfg should be used here instead of - * SKU ID. The current implementation of mem_config does not - * support channel population. - */ - - if (sku_id != SCRD_SKU1) - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); + spd_span = spd_index * SPD_LEN; + memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN); + + if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN + && spd_index != MIC_SINGLE_CHAN) { + memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN); + printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n"); + } /* Make sure a valid SPD was found */ if (pei_data->spd_data[0][0][0] == 0) diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index babadd2..cdff9ce 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -30,4 +30,7 @@ #define SPD_PART_LEN 18 #define SPD_MANU_OFF 148 +#define HYNIX_SINGLE_CHAN 0x1 +#define SAMSUNG_SINGLE_CHAN 0x4 +#define MIC_SINGLE_CHAN 0x5 #endif

1 0

New patch to review for coreboot: mediatek/mt8173: Add PMIC wrapper driver
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12589 -gerrit commit f63174be68ed910f5a62899d28043c0d3dc90e04 Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Fri Jul 31 17:10:52 2015 +0800 mediatek/mt8173: Add PMIC wrapper driver BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Id1e9244e33e34c2c30d7c87cc277ecb7524dfb09 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b21abfdaac4eeb2b65d4c0269ca0b9beff4b5e2f Original-Change-Id: I84de32de3a09e7857b0695759b49d4db5fde87ec Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292668 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Makefile.inc | 2 + src/soc/mediatek/mt8173/include/soc/pmic_wrap.h | 255 ++++++++++++ src/soc/mediatek/mt8173/pmic_wrap.c | 493 ++++++++++++++++++++++++ 3 files changed, 750 insertions(+) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 0d7957e..54b04bd 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -28,6 +28,8 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif +bootblock-y += pmic_wrap.c + ################################################################################ romstage-y += cbfs.c diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h new file mode 100644 index 0000000..82ff07c --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h @@ -0,0 +1,255 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOC_MEDIATEK_MT8173_PMIC_WRAP_H +#define SOC_MEDIATEK_MT8173_PMIC_WRAP_H + +#include <soc/addressmap.h> +#include <types.h> + +/* external API */ +s32 pwrap_read(u16 adr, u16 *rdata); +s32 pwrap_write(u16 adr, u16 wdata); +s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check); +s32 pwrap_init(void); + +static struct mt8173_pwrap_regs * const mt8173_pwrap = (void *)PMIC_WRAP_BASE; + +enum { + WACS2 = 1 << 4 +}; + +enum { + DEW_BASE = 0xBC00 +}; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_WRP_CKPDN = PMIC_BASE + 0x011A, // 0x0056 + PMIC_WRP_RST_CON = PMIC_BASE + 0x0120, // 0x005C + PMIC_TOP_CKCON2 = PMIC_BASE + 0x012A, + PMIC_TOP_CKCON3 = PMIC_BASE + 0x01D4 +}; + +/* timeout setting */ +enum { + TIMEOUT_READ_US = 255, + TIMEOUT_WAIT_IDLE_US = 255 +}; + +/* PMIC_WRAP registers */ +struct mt8173_pwrap_regs { + u32 mux_sel; + u32 wrap_en; + u32 dio_en; + u32 sidly; + u32 rddmy; + u32 si_ck_con; + u32 cshext_write; + u32 cshext_read; + u32 cslext_start; + u32 cslext_end; + u32 staupd_prd; + u32 staupd_grpen; + u32 reserved[4]; + u32 staupd_man_trig; + u32 staupd_sta; + u32 wrap_sta; + u32 harb_init; + u32 harb_hprio; + u32 hiprio_arb_en; + u32 harb_sta0; + u32 harb_sta1; + u32 man_en; + u32 man_cmd; + u32 man_rdata; + u32 man_vldclr; + u32 wacs0_en; + u32 init_done0; + u32 wacs0_cmd; + u32 wacs0_rdata; + u32 wacs0_vldclr; + u32 wacs1_en; + u32 init_done1; + u32 wacs1_cmd; + u32 wacs1_rdata; + u32 wacs1_vldclr; + u32 wacs2_en; + u32 init_done2; + u32 wacs2_cmd; + u32 wacs2_rdata; + u32 wacs2_vldclr; + u32 int_en; + u32 int_flg_raw; + u32 int_flg; + u32 int_clr; + u32 sig_adr; + u32 sig_mode; + u32 sig_value; + u32 sig_errval; + u32 crc_en; + u32 timer_en; + u32 timer_sta; + u32 wdt_unit; + u32 wdt_src_en; + u32 wdt_flg; + u32 debug_int_sel; + u32 dvfs_adr0; + u32 dvfs_wdata0; + u32 dvfs_adr1; + u32 dvfs_wdata1; + u32 dvfs_adr2; + u32 dvfs_wdata2; + u32 dvfs_adr3; + u32 dvfs_wdata3; + u32 dvfs_adr4; + u32 dvfs_wdata4; + u32 dvfs_adr5; + u32 dvfs_wdata5; + u32 dvfs_adr6; + u32 dvfs_wdata6; + u32 dvfs_adr7; + u32 dvfs_wdata7; + u32 spminf_sta; + u32 cipher_key_sel; + u32 cipher_iv_sel; + u32 cipher_en; + u32 cipher_rdy; + u32 cipher_mode; + u32 cipher_swrst; + u32 dcm_en; + u32 dcm_dbc_prd; +}; + +check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148); + +enum { + RDATA_WACS_RDATA_SHIFT = 0, + RDATA_WACS_FSM_SHIFT = 16, + RDATA_WACS_REQ_SHIFT = 19, + RDATA_SYNC_IDLE_SHIFT, + RDATA_INIT_DONE_SHIFT, + RDATA_SYS_IDLE_SHIFT, +}; + +enum { + RDATA_WACS_RDATA_MASK = 0xffff, + RDATA_WACS_FSM_MASK = 0x7, + RDATA_WACS_REQ_MASK = 0x1, + RDATA_SYNC_IDLE_MASK = 0x1, + RDATA_INIT_DONE_MASK = 0x1, + RDATA_SYS_IDLE_MASK = 0x1, +}; + +/* WACS_FSM */ +enum { + WACS_FSM_IDLE = 0x00, + WACS_FSM_REQ = 0x02, + WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */ + WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag + * clearing */ + WACS_INIT_DONE = 0x01, + WACS_SYNC_IDLE = 0x01, + WACS_SYNC_BUSY = 0x00 +}; + +/* dewrapper regsister */ +enum { + DEW_EVENT_OUT_EN = DEW_BASE + 0x0, + DEW_DIO_EN = DEW_BASE + 0x2, + DEW_EVENT_SRC_EN = DEW_BASE + 0x4, + DEW_EVENT_SRC = DEW_BASE + 0x6, + DEW_EVENT_FLAG = DEW_BASE + 0x8, + DEW_READ_TEST = DEW_BASE + 0xA, + DEW_WRITE_TEST = DEW_BASE + 0xC, + DEW_CRC_EN = DEW_BASE + 0xE, + DEW_CRC_VAL = DEW_BASE + 0x10, + DEW_MON_GRP_SEL = DEW_BASE + 0x12, + DEW_MON_FLAG_SEL = DEW_BASE + 0x14, + DEW_EVENT_TEST = DEW_BASE + 0x16, + DEW_CIPHER_KEY_SEL = DEW_BASE + 0x18, + DEW_CIPHER_IV_SEL = DEW_BASE + 0x1A, + DEW_CIPHER_LOAD = DEW_BASE + 0x1C, + DEW_CIPHER_START = DEW_BASE + 0x1E, + DEW_CIPHER_RDY = DEW_BASE + 0x20, + DEW_CIPHER_MODE = DEW_BASE + 0x22, + DEW_CIPHER_SWRST = DEW_BASE + 0x24, + DEW_CIPHER_IV0 = DEW_BASE + 0x26, + DEW_CIPHER_IV1 = DEW_BASE + 0x28, + DEW_CIPHER_IV2 = DEW_BASE + 0x2A, + DEW_CIPHER_IV3 = DEW_BASE + 0x2C, + DEW_CIPHER_IV4 = DEW_BASE + 0x2E, + DEW_CIPHER_IV5 = DEW_BASE + 0x30 +}; + +/* dewrapper defaule value */ +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a +}; + +enum pmic_regck { + REG_CLOCK_18MHZ, + REG_CLOCK_26MHZ, + REG_CLOCK_SAFE_MODE +}; + +/* manual commnd */ +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, + OP_OUTD = 0x9, + OP_INS = 0xC, + OP_IND = 0xD +}; + +/* error information flag */ +enum { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32 +}; + +#endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */ diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c new file mode 100644 index 0000000..412eae5 --- /dev/null +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -0,0 +1,493 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/infracfg.h> +#include <soc/pmic_wrap.h> +#include <timer.h> + +#define PWRAPTAG "[PWRAP] " +#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg) +#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \ + __LINE__, ## arg) + +/* define macro and inline function (for do while loop) */ + +typedef u32 (*loop_condition_fp)(u32); + +static inline u32 wait_for_fsm_vldclr(u32 x) +{ + return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_WFVLDCLR; +} + +static inline u32 wait_for_sync(u32 x) +{ + return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) != + WACS_SYNC_IDLE; +} + +static inline u32 wait_for_idle_and_sync(u32 x) +{ + return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) & + RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE)); +} + +static inline u32 wait_for_cipher_ready(u32 x) +{ + return x != 3; +} + +static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, + void *wacs_vldclr_register, + u32 *read_reg) +{ + u32 reg_rdata; + + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32((wacs_register)); + /* if last read command timeout,clear vldclr bit + read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; + write:FSM_REQ-->idle */ + switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & + RDATA_WACS_FSM_MASK)) { + case WACS_FSM_WFVLDCLR: + write32(wacs_vldclr_register, 1); + pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); + break; + case WACS_FSM_WFDLE: + pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n"); + break; + case WACS_FSM_REQ: + pwrap_err("WACS_FSM = WACS_FSM_REQ\n"); + break; + default: + break; + } + + if (stopwatch_expired(&sw)) + return E_PWR_WAIT_IDLE_TIMEOUT; + + } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_IDLE); /* IDLE State */ + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, + void *wacs_register, u32 *read_reg) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = read32((wacs_register)); + + if (stopwatch_expired(&sw)) { + pwrap_err("timeout when waiting for idle\n"); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + } while (fp(reg_rdata)); /* IDLE State */ + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check) +{ + u32 reg_rdata = 0; + u32 wacs_write = 0; + u32 wacs_adr = 0; + u32 wacs_cmd = 0; + u32 return_value = 0; + + if (init_check) { + reg_rdata = read32(&mt8173_pwrap->wacs2_rdata); + /* Prevent someone to used pwrap before pwrap init */ + if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & + RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + pwrap_err("initialization isn't finished \n"); + return E_PWR_NOT_INIT_DONE; + } + } + reg_rdata = 0; + /* Check IDLE in advance */ + return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US, + &mt8173_pwrap->wacs2_rdata, + &mt8173_pwrap->wacs2_vldclr, + 0); + if (return_value != 0) { + pwrap_err("wait_for_fsm_idle fail,return_value=%d\n", + return_value); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + wacs_write = write << 31; + wacs_adr = (adr >> 1) << 16; + wacs_cmd = wacs_write | wacs_adr | wdata; + + write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd); + if (write == 0) { + if (NULL == rdata) { + pwrap_err("rdata is a NULL pointer\n"); + return E_PWR_INVALID_ARG; + } + return_value = wait_for_state_ready(wait_for_fsm_vldclr, + TIMEOUT_READ_US, + &mt8173_pwrap->wacs2_rdata, + &reg_rdata); + if (return_value != 0) { + pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n", + return_value); + return E_PWR_WAIT_IDLE_TIMEOUT_READ; + } + *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) + & RDATA_WACS_RDATA_MASK); + write32(&mt8173_pwrap->wacs2_vldclr, 1); + } + + return 0; +} + +/* external API for pmic_wrap user */ + +s32 pwrap_read(u16 adr, u16 *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 1); +} + +s32 pwrap_write(u16 adr, u16 wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 1); +} + +static s32 pwrap_read_nochk(u16 adr, u16 *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 0); +} + +static s32 pwrap_write_nochk(u16 adr, u16 wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 0); +} + +/* call it in pwrap_init,mustn't check init done */ +static s32 pwrap_init_dio(u32 dio_en) +{ + u16 rdata = 0; + u32 return_value = 0; + + pwrap_write_nochk(DEW_DIO_EN, dio_en); + + /* Check IDLE in advance */ + return_value = + wait_for_state_ready(wait_for_idle_and_sync, + TIMEOUT_WAIT_IDLE_US, + &mt8173_pwrap->wacs2_rdata, + 0); + if (return_value != 0) { + pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); + return return_value; + } + write32(&mt8173_pwrap->dio_en, dio_en); + /* Read Test */ + pwrap_read_nochk(DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + pwrap_err("fail,dio_en = %#x, READ_TEST rdata=%#x\n", dio_en, + rdata); + return E_PWR_READ_TEST_FAIL; + } + + return 0; +} + +/* + * pwrap_init_sidly - configure serial input delay + * + * This configures the serial input delay. We can configure 0, 2, 4 or 6ns + * delay. Do a read test with all possible values and chose the best delay. + */ +static s32 pwrap_init_sidly(void) +{ + u16 rdata; + u32 i; + u32 pass = 0; + u32 sidly = 0; + + for (i = 0; i < 4; i++) { + write32(&mt8173_pwrap->sidly, i); + pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0); + if (rdata == DEFAULT_VALUE_READ_TEST) + pass |= 1 << i; + } + + /* + * Config SIDLY according to results + * Pass range should be continuously or return failed + */ + switch (pass) { + /* only 1 pass, choose it */ + case 1 << 0: + sidly = 0; + break; + case 1 << 1: + sidly = 1; + break; + case 1 << 2: + sidly = 2; + break; + case 1 << 3: + sidly = 3; + break; + /* two pass, choose the one on SIDLY boundary */ + case (1 << 0) | (1 << 1): + sidly = 0; + break; + case (1 << 1) | (1 << 2): /* no boundary, choose smaller one */ + sidly = 1; + break; + case (1 << 2) | (1 << 3): + sidly = 3; + break; + /* three pass, choose the middle one */ + case (1 << 0) | (1 << 1) | (1 << 2): + sidly = 1; + break; + case (1 << 1) | (1 << 2) | (1 << 3): + sidly = 2; + break; + /* four pass, choose the smaller middle one */ + case (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3): + sidly = 1; + break; + /* pass range not continuous, should not happen */ + default: + die("sidly pass range not continuous\n"); + } + + write32(&mt8173_pwrap->sidly, sidly); + + return 0; +} + +static s32 pwrap_reset_spislv(void) +{ + u32 ret = 0; + u32 return_value = 0; + + write32(&mt8173_pwrap->hiprio_arb_en, 0); + write32(&mt8173_pwrap->wrap_en, 0); + write32(&mt8173_pwrap->mux_sel, 1); + write32(&mt8173_pwrap->man_en, 1); + write32(&mt8173_pwrap->dio_en, 0); + + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); + /* to reset counter */ + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); + /* + * In order to pull CSN signal to PMIC, + * PMIC will count it then reset spi slave + */ + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + + return_value = wait_for_state_ready(wait_for_sync, + TIMEOUT_WAIT_IDLE_US, + &mt8173_pwrap->wacs2_rdata, 0); + if (return_value != 0) { + pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); + ret = E_PWR_TIMEOUT; + } + + write32(&mt8173_pwrap->man_en, 0); + write32(&mt8173_pwrap->mux_sel, 0); + + return ret; +} + +static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel) +{ + u16 wdata = 0; + u16 rdata = 0; + + /* Set reg clk freq */ + pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata); + + if (regck_sel == REG_CLOCK_18MHZ) + wdata = (rdata & (~(0x3 << 10))) | (0x1 << 10); + else + wdata = rdata & (~(0x3 << 10)); + + pwrap_write_nochk(PMIC_TOP_CKCON2, wdata); + pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata); + if (rdata != wdata) { + pwrap_err("pwrap_init_reg_clock,rdata=%#x\n", rdata); + return E_PWR_INIT_REG_CLOCK; + } + /* Config SPI Waveform according to reg clk */ + switch (regck_sel) { + case REG_CLOCK_18MHZ: + write32(&mt8173_pwrap->rddmy, 0xc); + write32(&mt8173_pwrap->cshext_write, 0x0); + write32(&mt8173_pwrap->cshext_read, 0x4); + write32(&mt8173_pwrap->cslext_start, 0x0); + write32(&mt8173_pwrap->cslext_end, 0x4); + break; + case REG_CLOCK_26MHZ: + write32(&mt8173_pwrap->rddmy, 0xc); + write32(&mt8173_pwrap->cshext_write, 0x0); + write32(&mt8173_pwrap->cshext_read, 0x4); + write32(&mt8173_pwrap->cslext_start, 0x2); + write32(&mt8173_pwrap->cslext_end, 0x2); + break; + default: + write32(&mt8173_pwrap->rddmy, 0xf); + write32(&mt8173_pwrap->cshext_write, 0xf); + write32(&mt8173_pwrap->cshext_read, 0xf); + write32(&mt8173_pwrap->cslext_start, 0xf); + write32(&mt8173_pwrap->cslext_end, 0xf); + break; + } + + return 0; +} + +s32 pwrap_init(void) +{ + s32 sub_return = 0; + s32 sub_return1 = 0; + u16 rdata = 0x0; + + setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + /* add 1us delay for toggling SW reset */ + udelay(1); + /* clear reset bit */ + clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + + /* Enable DCM */ + write32(&mt8173_pwrap->dcm_en, 3); + write32(&mt8173_pwrap->dcm_dbc_prd, 0); + + /* Reset SPISLV */ + sub_return = pwrap_reset_spislv(); + if (sub_return != 0) { + pwrap_err("error,pwrap_reset_spislv fail,sub_return=%#x\n", + sub_return); + return E_PWR_INIT_RESET_SPI; + } + /* Enable WACS2 */ + write32(&mt8173_pwrap->wrap_en, 1); + write32(&mt8173_pwrap->hiprio_arb_en, WACS2); + write32(&mt8173_pwrap->wacs2_en, 1); + + /* SIDLY setting */ + sub_return = pwrap_init_sidly(); + if (sub_return != 0) { + pwrap_err("error,pwrap_init_sidly fail,sub_return=%#x\n", + sub_return); + return E_PWR_INIT_SIDLY; + } + /* + * SPI Waveform Configuration + * 18MHz/26MHz/safe mode/ + */ + sub_return = pwrap_init_reg_clock(REG_CLOCK_26MHZ); + if (sub_return != 0) { + pwrap_err("error,pwrap_init_reg_clock fail,sub_return=%#x\n", + sub_return); + return E_PWR_INIT_REG_CLOCK; + } + /* + * Enable PMIC + */ + pwrap_read_nochk(PMIC_WRP_CKPDN, &rdata); + sub_return = pwrap_write_nochk(PMIC_WRP_CKPDN, rdata & 0x50); + /* clear dewrap reset bit */ + sub_return1 = pwrap_write_nochk(PMIC_WRP_RST_CON, 0); + if ((sub_return != 0) || (sub_return1 != 0)) { + pwrap_err("Enable PMIC fail, sub_return=%#x sub_return1=%#x\n", + sub_return, sub_return1); + return E_PWR_INIT_ENABLE_PMIC; + } + /* Enable DIO mode */ + sub_return = pwrap_init_dio(1); + if (sub_return != 0) { + pwrap_err("pwrap_init_dio error code=%#x, sub_return=%#x\n", + 0x11, sub_return); + return E_PWR_INIT_DIO; + } + + /* + * Write test using WACS2, + * make sure the read/write function ready + */ + sub_return = pwrap_write_nochk(DEW_WRITE_TEST, WRITE_TEST_VALUE); + sub_return1 = pwrap_read_nochk(DEW_WRITE_TEST, &rdata); + if ((rdata != WRITE_TEST_VALUE) || (sub_return != 0) + || (sub_return1 != 0)) { + pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n", + rdata, sub_return, sub_return1); + return E_PWR_INIT_WRITE_TEST; + } + + /* Signature Checking - Using CRC + * should be the last to modify WRITE_TEST + */ + sub_return = pwrap_write_nochk(DEW_CRC_EN, 0x1); + if (sub_return != 0) { + pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return); + return E_PWR_INIT_ENABLE_CRC; + } + write32(&mt8173_pwrap->crc_en, 0x1); + write32(&mt8173_pwrap->sig_mode, 0x0); + write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL); + + /* PMIC_WRAP enables */ + write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff); + write32(&mt8173_pwrap->wacs0_en, 0x1); + write32(&mt8173_pwrap->wacs1_en, 0x1); + + /* + * switch event pin from usbdl mode to normal mode for pmic interrupt, + * NEW@MT6397 + */ + pwrap_read_nochk(PMIC_TOP_CKCON3, &rdata); + sub_return = pwrap_write_nochk(PMIC_TOP_CKCON3, (rdata & 0x0007)); + if (sub_return != 0) + pwrap_err("!!switch event pin fail,sub_return=%d\n", + sub_return); + + /* Initialization Done */ + write32(&mt8173_pwrap->init_done2, 0x1); + write32(&mt8173_pwrap->init_done0, 0x1); + write32(&mt8173_pwrap->init_done1, 0x1); + + return 0; +}

1 0

New patch to review for coreboot: mediatek/mt8173: Add PLL driver
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12588 -gerrit commit 0eda85491ad206422b2a0b0047733d035cdf33a2 Author: James Liao <jamesjj.liao(a)mediatek.com> Date: Fri Jul 31 17:10:53 2015 +0800 mediatek/mt8173: Add PLL driver Add PLL init code. BRANCH=none BUG=none TEST=none Change-Id: I2dcea8cdea1a3812bd8b84b7e8d961e7f8d4d953 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e6e2eecb2fad30db018685b61912103f5e2cd524 Original-Change-Id: Id67d8033f3b2a267a140d7d73daa5727bc032272 Original-Signed-off-by: James Liao <jamesjj.liao(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292670 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/Makefile.inc | 1 + src/soc/mediatek/mt8173/bootblock.c | 5 + src/soc/mediatek/mt8173/include/soc/pll.h | 291 +++++++++++++++++++ src/soc/mediatek/mt8173/pll.c | 460 ++++++++++++++++++++++++++++++ 4 files changed, 757 insertions(+) diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 74a7618..0d7957e 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -21,6 +21,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) bootblock-y += bootblock.c bootblock-y += cbfs.c +bootblock-y += pll.c bootblock-y += timer.c ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index 232a655..aaa7f61 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -18,7 +18,12 @@ */ #include <bootblock_common.h> +#include <soc/pll.h> void bootblock_soc_init(void) { + mt_pll_init(); + + /* post init pll */ + mt_pll_post_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h new file mode 100644 index 0000000..b09ad41 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOC_MEDIATEK_MT8173_PLL_H +#define SOC_MEDIATEK_MT8173_PLL_H + +#include <soc/addressmap.h> + +struct mt8173_topckgen_regs { + u32 clk_mode; + u32 dcm_cfg; + u32 reserved1[6]; + u32 tst_sel_0; /* 0x020 */ + u32 tst_sel_1; + u32 tst_sel_2; + u32 reserved2[5]; + u32 clk_cfg_0; /* 0x040 */ + u32 clk_cfg_0_set; + u32 clk_cfg_0_clr; + u32 reserved3[1]; + u32 clk_cfg_1; /* 0x050 */ + u32 clk_cfg_1_set; + u32 clk_cfg_1_clr; + u32 reserved4[1]; + u32 clk_cfg_2; /* 0x060 */ + u32 clk_cfg_2_set; + u32 clk_cfg_2_clr; + u32 reserved5[1]; + u32 clk_cfg_3; /* 0x070 */ + u32 clk_cfg_3_set; + u32 clk_cfg_3_clr; + u32 reserved6[1]; + u32 clk_cfg_4; /* 0x080 */ + u32 clk_cfg_4_set; + u32 clk_cfg_4_clr; + u32 reserved7[1]; + u32 clk_cfg_5; /* 0x090 */ + u32 clk_cfg_5_set; + u32 clk_cfg_5_clr; + u32 reserved8[1]; + u32 clk_cfg_6; /* 0x0a0 */ + u32 clk_cfg_6_set; + u32 clk_cfg_6_clr; + u32 reserved9[1]; + u32 clk_cfg_7; /* 0x0b0 */ + u32 clk_cfg_7_set; + u32 clk_cfg_7_clr; + u32 reserved10[1]; + u32 clk_cfg_12; /* 0x0c0 */ + u32 clk_cfg_12_set; + u32 clk_cfg_12_clr; + u32 reserved11[1]; + u32 clk_cfg_13; /* 0x0d0 */ + u32 clk_cfg_13_set; + u32 clk_cfg_13_clr; + u32 reserved12[9]; + u32 clk_cfg_8; /* 0x100 */ + u32 clk_cfg_9; + u32 clk_cfg_10; + u32 clk_cfg_11; + u32 reserved13[4]; + u32 clk_auddiv_0; /* 0x120 */ + u32 clk_auddiv_1; + u32 clk_auddiv_2; + u32 clk_auddiv_3; + u32 clk_mjcdiv_0; + u32 reserved14[51]; + u32 clk_scp_cfg_0; /* 0x200 */ + u32 clk_scp_cfg_1; + u32 reserved15[2]; + u32 clk_misc_cfg_0; /* 0x210 */ + u32 clk_misc_cfg_1; + u32 clk_misc_cfg_2; + u32 reserved16[1]; + u32 clk26cali_0; /* 0x220 */ + u32 clk26cali_1; + u32 clk26cali_2; + u32 cksta_reg; + u32 test_mode_cfg; + u32 reserved17[53]; + u32 mbist_cfg_0; /* 0x308 */ + u32 mbist_cfg_1; + u32 reset_deglitch_key; + u32 mbist_cfg_3; /* 0x314 */ +}; + +check_member(mt8173_topckgen_regs, clk_cfg_0, 0x40); +check_member(mt8173_topckgen_regs, clk_cfg_8, 0x100); +check_member(mt8173_topckgen_regs, clk_scp_cfg_0, 0x200); +check_member(mt8173_topckgen_regs, mbist_cfg_3, 0x314); + +struct mt8173_apmixed_regs { + u32 ap_pll_con0; + u32 reserved1[1]; + u32 ap_pll_con2; /* 0x008 */ + u32 ap_pll_con3; + u32 ap_pll_con4; + u32 ap_pll_con5; + u32 ap_pll_con6; + u32 ap_pll_con7; + u32 clksq_stb_con0; + u32 pll_pwr_con0; + u32 pll_pwr_con1; + u32 pll_iso_con0; + u32 pll_iso_con1; + u32 pll_stb_con0; + u32 div_stb_con0; + u32 pll_chg_con0; + u32 pll_test_con0; + u32 pll_test_con1; /* 0x044 */ + u32 reserved2[110]; + u32 armca15pll_con0; /* 0x200 */ + u32 armca15pll_con1; + u32 armca15pll_con2; + u32 armca15pll_pwr_con0; + u32 armca7pll_con0; + u32 armca7pll_con1; + u32 armca7pll_con2; + u32 armca7pll_pwr_con0; + u32 mainpll_con0; + u32 mainpll_con1; + u32 mainpll_con2; + u32 mainpll_pwr_con0; + u32 univpll_con0; + u32 univpll_con1; + u32 univpll_con2; + u32 univpll_pwr_con0; + u32 mmpll_con0; + u32 mmpll_con1; + u32 mmpll_con2; + u32 mmpll_pwr_con0; + u32 msdcpll_con0; + u32 msdcpll_con1; + u32 msdcpll_con2; + u32 msdcpll_pwr_con0; + u32 vencpll_con0; + u32 vencpll_con1; + u32 vencpll_con2; + u32 vencpll_pwr_con0; + u32 tvdpll_con0; + u32 tvdpll_con1; + u32 tvdpll_con2; + u32 tvdpll_pwr_con0; + u32 mpll_con0; + u32 mpll_con1; + u32 mpll_con2; + u32 mpll_pwr_con0; + u32 vcodecpll_con0; + u32 vcodecpll_con1; + u32 vcodecpll_con2; + u32 vcodecpll_pwr_con0; + u32 apll1_con0; + u32 apll1_con1; + u32 apll1_con2; + u32 apll1_con3; + u32 apll1_pwr_con0; + u32 apll2_con0; + u32 apll2_con1; + u32 apll2_con2; + u32 apll2_con3; + u32 apll2_pwr_con0; + u32 reserved3[2]; + u32 lvdspll_con0; /* 0x2d0 */ + u32 lvdspll_con1; + u32 lvdspll_con2; + u32 lvdspll_pwr_con0; + u32 lvdspll_ssc_con0; + u32 lvdspll_ssc_con1; + u32 lvdspll_ssc_con2; + u32 reserved4[1]; + u32 msdcpll2_con0; /* 0x2f0 */ + u32 msdcpll2_con1; + u32 msdcpll2_con2; + u32 msdcpll2_pwr_con0; /* 0x2fc */ +}; + +check_member(mt8173_apmixed_regs, ap_pll_con2, 0x8); +check_member(mt8173_apmixed_regs, armca15pll_con0, 0x200); +check_member(mt8173_apmixed_regs, msdcpll2_pwr_con0, 0x2fc); + +static struct mt8173_topckgen_regs *const mt8173_topckgen = (void *)CKSYS_BASE; +static struct mt8173_apmixed_regs *const mt8173_apmixed = (void *)APMIXED_BASE; + +/* PLL rate */ +enum { + ARMCA15PLL_HZ = 851500 * KHz, + ARMCA7PLL_HZ = 1105 * MHz, + MAINPLL_HZ = 1092 * MHz, + UNIVPLL_HZ = 1248 * MHz, + MMPLL_HZ = 455 * MHz, + MSDCPLL_HZ = 800 * MHz, + VENCPLL_HZ = 660 * MHz, + TVDPLL_HZ = 1782 * MHz, + MPLL_HZ = 1456 * MHz, + VCODECPLL_HZ = 1104 * MHz, + LVDSPLL_HZ = 150 * MHz, + MSDCPLL2_HZ = 800 * MHz, + APLL1_HZ = 180633600, + APLL2_HZ = 196608 * KHz, +}; + +/* top_div rate */ +enum { + AD_HDMITX_CLK_HZ = TVDPLL_HZ / 12, + AD_LVDSPLL_CK_HZ = LVDSPLL_HZ, + APLL1_CK_HZ = APLL1_HZ, + APLL2_CK_HZ = APLL2_HZ, + CLK26M_HZ = 26 * MHz, + CLKRTC_EXT_HZ = 32 * KHz, + MMPLL_CK_HZ = MMPLL_HZ, + MSDCPLL_D4_HZ = MSDCPLL_HZ / 4, + SYSPLL1_D2_HZ = MAINPLL_HZ / 4, + SYSPLL1_D4_HZ = MAINPLL_HZ / 8, + SYSPLL2_D2_HZ = MAINPLL_HZ / 6, + SYSPLL3_D2_HZ = MAINPLL_HZ / 10, + SYSPLL3_D4_HZ = MAINPLL_HZ / 20, + SYSPLL_D2_HZ = MAINPLL_HZ / 2, + TVDPLL_D2_HZ = TVDPLL_HZ / 2, + UNIVPLL1_D2_HZ = UNIVPLL_HZ / 4, + UNIVPLL1_D8_HZ = UNIVPLL_HZ / 16, + UNIVPLL2_D2_HZ = UNIVPLL_HZ / 6, + UNIVPLL2_D4_HZ = UNIVPLL_HZ / 12, + UNIVPLL3_D2_HZ = UNIVPLL_HZ / 10, + UNIVPLL_D52_HZ = UNIVPLL_HZ / 52, + VCODECPLL_CK_HZ = VCODECPLL_HZ / 3, + VENCPLL_D2_HZ = VENCPLL_HZ / 2, +}; + +/* top_mux rate */ +enum { + AXI_HZ = UNIVPLL2_D2_HZ, + MEM_HZ = CLK26M_HZ, + DDRPHYCFG_HZ = CLK26M_HZ, + MM_HZ = VENCPLL_D2_HZ, + PWM_HZ = CLK26M_HZ, + VDEC_HZ = VCODECPLL_CK_HZ, + VENC_HZ = VCODECPLL_CK_HZ, + MFG_HZ = MMPLL_CK_HZ, + CAMTG_HZ = CLK26M_HZ, + UART_HZ = CLK26M_HZ, + SPI_HZ = SYSPLL3_D2_HZ, + USB20_HZ = UNIVPLL1_D8_HZ, + MSDC30_2_HZ = MSDCPLL_D4_HZ, + MSDC30_3_HZ = MSDCPLL_D4_HZ, + AUDIO_HZ = CLK26M_HZ, + AUD_INTBUS_HZ = SYSPLL1_D4_HZ, + PMICSPI_HZ = CLK26M_HZ, + SCP_HZ = SYSPLL1_D2_HZ, + ATB_HZ = CLK26M_HZ, + VENC_LT_HZ = UNIVPLL1_D2_HZ, + DPI0_HZ = TVDPLL_D2_HZ, + IRDA_HZ = UNIVPLL2_D4_HZ, + CCI400_HZ = SYSPLL_D2_HZ, + AUD_1_HZ = APLL1_CK_HZ, + AUD_2_HZ = APLL2_CK_HZ, + MEM_MFG_IN_HZ = MMPLL_CK_HZ, + AXI_MFG_IN_HZ = AXI_HZ, + SCAM_HZ = SYSPLL3_D2_HZ, + SPINFI_IFR_HZ = CLK26M_HZ, + HDMI_HZ = AD_HDMITX_CLK_HZ, + DPILVDS_HZ = AD_LVDSPLL_CK_HZ, + MSDC50_2_H_HZ = SYSPLL2_D2_HZ, + HDCP_HZ = SYSPLL3_D4_HZ, + HDCP_24M_HZ = UNIVPLL_D52_HZ, + RTC_HZ = CLKRTC_EXT_HZ, + USB30_HZ = UNIVPLL3_D2_HZ, + MSDC50_0_H_HZ = SYSPLL2_D2_HZ, + MSDC50_0_HZ = MSDCPLL_D4_HZ, + MSDC30_1_HZ = MSDCPLL_D4_HZ, +}; + +void mt_pll_post_init(void); +void mt_pll_init(void); + +#endif /* SOC_MEDIATEK_MT8173_PLL_H */ diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c new file mode 100644 index 0000000..f1ea9a9 --- /dev/null +++ b/src/soc/mediatek/mt8173/pll.c @@ -0,0 +1,460 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <stddef.h> + +#include <soc/addressmap.h> +#include <soc/infracfg.h> +#include <soc/pll.h> + +#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l)) + +enum mux_id { + TOP_AXI_SEL, + TOP_MEM_SEL, + TOP_DDRPHYCFG_SEL, + TOP_MM_SEL, + TOP_PWM_SEL, + TOP_VDEC_SEL, + TOP_VENC_SEL, + TOP_MFG_SEL, + TOP_CAMTG_SEL, + TOP_UART_SEL, + TOP_SPI_SEL, + TOP_USB20_SEL, + TOP_USB30_SEL, + TOP_MSDC50_0_H_SEL, + TOP_MSDC50_0_SEL, + TOP_MSDC30_1_SEL, + TOP_MSDC30_2_SEL, + TOP_MSDC30_3_SEL, + TOP_AUDIO_SEL, + TOP_AUD_INTBUS_SEL, + TOP_PMICSPI_SEL, + TOP_SCP_SEL, + TOP_ATB_SEL, + TOP_VENC_LT_SEL, + TOP_DPI0_SEL, + TOP_IRDA_SEL, + TOP_CCI400_SEL, + TOP_AUD_1_SEL, + TOP_AUD_2_SEL, + TOP_MEM_MFG_IN_SEL, + TOP_AXI_MFG_IN_SEL, + TOP_SCAM_SEL, + TOP_SPINFI_IFR_SEL, + TOP_HDMI_SEL, + TOP_DPILVDS_SEL, + TOP_MSDC50_2_H_SEL, + TOP_HDCP_SEL, + TOP_HDCP_24M_SEL, + TOP_RTC_SEL, + TOP_NR_MUX +}; + +#define TOPCKGEN_REG(x) (CKSYS_BASE + offsetof(struct mt8173_topckgen_regs, x)) +#define APMIXED_REG(x) (APMIXED_BASE + offsetof(struct mt8173_apmixed_regs, x)) + +struct mux { + void *reg; + u8 mux_shift; + u8 mux_width; +}; + +#define MUX(_id, _reg, _mux_shift, _mux_width) \ + [_id] = { \ + .reg = (void *)TOPCKGEN_REG(_reg), \ + .mux_shift = _mux_shift, \ + .mux_width = _mux_width, \ + } + +static const struct mux muxes[] = { + /* CLK_CFG_0 */ + MUX(TOP_AXI_SEL, clk_cfg_0, 0, 3), + MUX(TOP_MEM_SEL, clk_cfg_0, 8, 1), + MUX(TOP_DDRPHYCFG_SEL, clk_cfg_0, 16, 1), + MUX(TOP_MM_SEL, clk_cfg_0, 24, 4), + /* CLK_CFG_1 */ + MUX(TOP_PWM_SEL, clk_cfg_1, 0, 2), + MUX(TOP_VDEC_SEL, clk_cfg_1, 8, 4), + MUX(TOP_VENC_SEL, clk_cfg_1, 16, 4), + MUX(TOP_MFG_SEL, clk_cfg_1, 24, 4), + /* CLK_CFG_2 */ + MUX(TOP_CAMTG_SEL, clk_cfg_2, 0, 3), + MUX(TOP_UART_SEL, clk_cfg_2, 8, 1), + MUX(TOP_SPI_SEL, clk_cfg_2, 16, 3), + MUX(TOP_USB20_SEL, clk_cfg_2, 24, 2), + /* CLK_CFG_3 */ + MUX(TOP_USB30_SEL, clk_cfg_3, 0, 2), + MUX(TOP_MSDC50_0_H_SEL, clk_cfg_3, 8, 3), + MUX(TOP_MSDC50_0_SEL, clk_cfg_3, 16, 4), + MUX(TOP_MSDC30_1_SEL, clk_cfg_3, 24, 3), + /* CLK_CFG_4 */ + MUX(TOP_MSDC30_2_SEL, clk_cfg_4, 0, 3), + MUX(TOP_MSDC30_3_SEL, clk_cfg_4, 8, 4), + MUX(TOP_AUDIO_SEL, clk_cfg_4, 16, 2), + MUX(TOP_AUD_INTBUS_SEL, clk_cfg_4, 24, 3), + /* CLK_CFG_5 */ + MUX(TOP_PMICSPI_SEL, clk_cfg_5, 0, 3), + MUX(TOP_SCP_SEL, clk_cfg_5, 8, 3), + MUX(TOP_ATB_SEL, clk_cfg_5, 16, 2), + MUX(TOP_VENC_LT_SEL, clk_cfg_5, 24, 4), + /* CLK_CFG_6 */ + MUX(TOP_DPI0_SEL, clk_cfg_6, 0, 3), + MUX(TOP_IRDA_SEL, clk_cfg_6, 8, 2), + MUX(TOP_CCI400_SEL, clk_cfg_6, 16, 3), + MUX(TOP_AUD_1_SEL, clk_cfg_6, 24, 2), + /* CLK_CFG_7 */ + MUX(TOP_AUD_2_SEL, clk_cfg_7, 0, 2), + MUX(TOP_MEM_MFG_IN_SEL, clk_cfg_7, 8, 2), + MUX(TOP_AXI_MFG_IN_SEL, clk_cfg_7, 16, 2), + MUX(TOP_SCAM_SEL, clk_cfg_7, 24, 2), + /* CLK_CFG_12 */ + MUX(TOP_SPINFI_IFR_SEL, clk_cfg_12, 0, 3), + MUX(TOP_HDMI_SEL, clk_cfg_12, 8, 2), + MUX(TOP_DPILVDS_SEL, clk_cfg_12, 24, 3), + /* CLK_CFG_13 */ + MUX(TOP_MSDC50_2_H_SEL, clk_cfg_13, 0, 3), + MUX(TOP_HDCP_SEL, clk_cfg_13, 8, 2), + MUX(TOP_HDCP_24M_SEL, clk_cfg_13, 16, 2), + MUX(TOP_RTC_SEL, clk_cfg_13, 24, 2), +}; + +static void mux_set_sel(const struct mux *mux, u32 sel) +{ + u32 mask = GENMASK(mux->mux_width - 1, 0); + u32 val = read32(mux->reg); + + val &= ~(mask << mux->mux_shift); + val |= (sel & mask) << mux->mux_shift; + write32(mux->reg, val); +} + +#define PLL_PWR_ON (1 << 0) +#define PLL_EN (1 << 0) +#define PLL_ISO (1 << 1) +#define PLL_RSTB (1 << 24) +#define PLL_PCW_CHG (1 << 31) +#define PLL_POSTDIV_MASK 0x7 +#define PCW_INTEGER_BITS 7 + +enum pll_id { + APMIXED_ARMCA15PLL, + APMIXED_ARMCA7PLL, + APMIXED_MAINPLL, + APMIXED_UNIVPLL, + APMIXED_MMPLL, + APMIXED_MSDCPLL, + APMIXED_VENCPLL, + APMIXED_TVDPLL, + APMIXED_MPLL, + APMIXED_VCODECPLL, + APMIXED_APLL1, + APMIXED_APLL2, + APMIXED_LVDSPLL, + APMIXED_MSDCPLL2, + APMIXED_NR_PLL +}; + +const u32 pll_div_rate[] = { + 3UL * GHz, + 1 * GHz, + 500 * MHz, + 250 * MHz, + 125 * MHz, + 0, +}; + +const u32 univpll_div_rate[] = { + 3UL * GHz, + 1500 * MHz, + 750 * MHz, + 375 * MHz, + 187500 * KHz, + 0, +}; + +const u32 mmpll_div_rate[] = { + 3UL * GHz, + 1 * GHz, + 702 * MHz, + 253500 * KHz, + 126750 * KHz, + 0, +}; + +struct pll { + void *reg; + void *pwr_reg; + u32 rstb; + u8 pcwbits; + void *div_reg; + u8 div_shift; + void *pcw_reg; + u8 pcw_shift; + const u32 *div_rate; +}; + +#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, \ + _pcw_reg, _pcw_shift, _div_rate) \ + [_id] = { \ + .reg = (void *)APMIXED_REG(_reg), \ + .pwr_reg = (void *)APMIXED_REG(_pwr_reg), \ + .rstb = _rstb, \ + .pcwbits = _pcwbits, \ + .div_reg = (void *)APMIXED_REG(_div_reg), \ + .div_shift = _div_shift, \ + .pcw_reg = (void *)APMIXED_REG(_pcw_reg), \ + .pcw_shift = _pcw_shift, \ + .div_rate = _div_rate, \ + } + +static const struct pll plls[] = { + PLL(APMIXED_ARMCA15PLL, armca15pll_con0, armca15pll_pwr_con0, 0, 21, + armca15pll_con1, 24, armca15pll_con1, 0, pll_div_rate), + PLL(APMIXED_ARMCA7PLL, armca7pll_con0, armca7pll_pwr_con0, PLL_RSTB, 21, + armca7pll_con1, 24, armca7pll_con1, 0, pll_div_rate), + PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_pwr_con0, PLL_RSTB, 21, + mainpll_con0, 4, mainpll_con1, 0, pll_div_rate), + PLL(APMIXED_UNIVPLL, univpll_con0, univpll_pwr_con0, PLL_RSTB, 7, + univpll_con0, 4, univpll_con1, 14, univpll_div_rate), + PLL(APMIXED_MMPLL, mmpll_con0, mmpll_pwr_con0, 0, 21, + mmpll_con1, 24, mmpll_con1, 0, mmpll_div_rate), + PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_pwr_con0, 0, 21, + msdcpll_con0, 4, msdcpll_con1, 0, pll_div_rate), + PLL(APMIXED_VENCPLL, vencpll_con0, vencpll_pwr_con0, 0, 21, + vencpll_con0, 4, vencpll_con1, 0, pll_div_rate), + PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_pwr_con0, 0, 21, + tvdpll_con0, 4, tvdpll_con1, 0, pll_div_rate), + PLL(APMIXED_MPLL, mpll_con0, mpll_pwr_con0, 0, 21, + mpll_con0, 4, mpll_con1, 0, pll_div_rate), + PLL(APMIXED_VCODECPLL, vcodecpll_con0, vcodecpll_pwr_con0, 0, 21, + vcodecpll_con0, 4, vcodecpll_con1, 0, pll_div_rate), + PLL(APMIXED_APLL1, apll1_con0, apll1_pwr_con0, 0, 31, + apll1_con0, 4, apll1_con1, 0, pll_div_rate), + PLL(APMIXED_APLL2, apll2_con0, apll2_pwr_con0, 0, 31, + apll2_con0, 4, apll2_con1, 0, pll_div_rate), + PLL(APMIXED_LVDSPLL, lvdspll_con0, lvdspll_pwr_con0, 0, 21, + lvdspll_con0, 4, lvdspll_con1, 0, pll_div_rate), + PLL(APMIXED_MSDCPLL2, msdcpll2_con0, msdcpll2_pwr_con0, 0, 21, + msdcpll2_con0, 4, msdcpll2_con1, 0, pll_div_rate), +}; + +static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv) +{ + u32 val; + + /* set postdiv */ + val = read32(pll->div_reg); + val &= ~(PLL_POSTDIV_MASK << pll->div_shift); + val |= postdiv << pll->div_shift; + + /* postdiv and pcw need to set at the same time if on same register */ + if (pll->div_reg != pll->pcw_reg) { + write32(pll->div_reg, val); + val = read32(pll->pcw_reg); + } + + /* set pcw */ + val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); + val |= pcw << pll->pcw_shift; + val |= PLL_PCW_CHG; + write32(pll->pcw_reg, val); +} + +static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv, + u32 freq) +{ + const u32 fin_hz = CLK26M_HZ; + const u32 *div_rate = pll->div_rate; + u32 val; + + assert(freq <= div_rate[0]); + assert(freq >= 1 * GHz / 16); + + for (val = 1; div_rate[val] != 0; val++) { + if (freq > div_rate[val]) + break; + } + val--; + *postdiv = val; + + /* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */ + val += pll->pcwbits - PCW_INTEGER_BITS; + + *pcw = ((u64)freq << val) / fin_hz; +} + +static int pll_set_rate(const struct pll *pll, u32 rate) +{ + u32 pcw = 0; + u32 postdiv; + + pll_calc_values(pll, &pcw, &postdiv, rate); + pll_set_rate_regs(pll, pcw, postdiv); + + return 0; +} + +void mt_pll_init(void) +{ + int i; + + /* reduce CLKSQ disable time */ + write32(&mt8173_apmixed->clksq_stb_con0, (0x05 << 8) | (0x01 << 0)); + /* extend PWR/ISO control timing to 1us */ + write32(&mt8173_apmixed->pll_iso_con0, (0x8 << 16) | (0x8 << 0)); + write32(&mt8173_apmixed->ap_pll_con6, 0x00000000); + + /************* + * xPLL PWR ON + **************/ + for (i = 0; i < APMIXED_NR_PLL; i++) + setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); + + udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ + + /****************** + * xPLL ISO Disable + *******************/ + for (i = 0; i < APMIXED_NR_PLL; i++) + clrbits_le32(plls[i].pwr_reg, PLL_ISO); + + /******************** + * xPLL Frequency Set + *********************/ + + pll_set_rate(&plls[APMIXED_ARMCA15PLL], ARMCA15PLL_HZ); + pll_set_rate(&plls[APMIXED_ARMCA7PLL], ARMCA7PLL_HZ); + pll_set_rate(&plls[APMIXED_MAINPLL], MAINPLL_HZ); + pll_set_rate(&plls[APMIXED_UNIVPLL], UNIVPLL_HZ); + pll_set_rate(&plls[APMIXED_MMPLL], MMPLL_HZ); + pll_set_rate(&plls[APMIXED_MSDCPLL], MSDCPLL_HZ); + pll_set_rate(&plls[APMIXED_VENCPLL], VENCPLL_HZ); + pll_set_rate(&plls[APMIXED_TVDPLL], TVDPLL_HZ); + pll_set_rate(&plls[APMIXED_MPLL], MPLL_HZ); + pll_set_rate(&plls[APMIXED_VCODECPLL], VCODECPLL_HZ); + pll_set_rate(&plls[APMIXED_LVDSPLL], LVDSPLL_HZ); + pll_set_rate(&plls[APMIXED_MSDCPLL2], MSDCPLL2_HZ); + pll_set_rate(&plls[APMIXED_APLL1], APLL1_HZ); + pll_set_rate(&plls[APMIXED_APLL2], APLL2_HZ); + + /*********************** + * xPLL Frequency Enable + ************************/ + for (i = 0; i < APMIXED_NR_PLL; i++) + setbits_le32(plls[i].reg, PLL_EN); + + udelay(40); /* wait for PLL stable (min delay is 20us) */ + + /*************** + * xPLL DIV RSTB + ****************/ + for (i = 0; i < APMIXED_NR_PLL; i++) { + if (plls[i].rstb) + setbits_le32(plls[i].reg, plls[i].rstb); + } + + /************** + * INFRA CLKMUX + ***************/ + + /* enable infrasys DCM */ + setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1); + + write32(&mt8173_topckgen->clk_mode, 0x1); + write32(&mt8173_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */ + + /************ + * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! + *************/ + + /* CLK_CFG_0 */ + mux_set_sel(&muxes[TOP_AXI_SEL], 5); /* 5: univpll2_d2 */ + mux_set_sel(&muxes[TOP_MEM_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_DDRPHYCFG_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_MM_SEL], 1); /* 1: vencpll_d2 */ + /* CLK_CFG_1 */ + mux_set_sel(&muxes[TOP_PWM_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_VDEC_SEL], 1); /* 1: vcodecpll_ck */ + mux_set_sel(&muxes[TOP_VENC_SEL], 1); /* 1: vcodecpll_ck */ + mux_set_sel(&muxes[TOP_MFG_SEL], 1); /* 1: mmpll_ck */ + /* CLK_CFG_2 */ + mux_set_sel(&muxes[TOP_CAMTG_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_UART_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_SPI_SEL], 1); /* 1: syspll3_d2 */ + mux_set_sel(&muxes[TOP_USB20_SEL], 1); /* 1: univpll1_d8 */ + /* CLK_CFG_4 */ + mux_set_sel(&muxes[TOP_MSDC30_2_SEL], 2); /* 2: msdcpll_d4 */ + mux_set_sel(&muxes[TOP_MSDC30_3_SEL], 5); /* 5: msdcpll_d4 */ + mux_set_sel(&muxes[TOP_AUDIO_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_AUD_INTBUS_SEL], 1); /* 1: syspll1_d4 */ + /* CLK_CFG_5 */ + mux_set_sel(&muxes[TOP_PMICSPI_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_SCP_SEL], 1); /* 1: syspll1_d2 */ + mux_set_sel(&muxes[TOP_ATB_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_VENC_LT_SEL], 6); /* 6: univpll1_d2 */ + /* CLK_CFG_6 */ + mux_set_sel(&muxes[TOP_DPI0_SEL], 1); /* 1: tvdpll_d2 */ + mux_set_sel(&muxes[TOP_IRDA_SEL], 1); /* 1: univpll2_d4 */ + mux_set_sel(&muxes[TOP_CCI400_SEL], 5); /* 5: syspll_d2 */ + mux_set_sel(&muxes[TOP_AUD_1_SEL], 1); /* 1: apll1_ck */ + /* CLK_CFG_7 */ + mux_set_sel(&muxes[TOP_AUD_2_SEL], 1); /* 1: apll2_ck */ + mux_set_sel(&muxes[TOP_MEM_MFG_IN_SEL], 1); /* 1: mmpll_ck */ + mux_set_sel(&muxes[TOP_AXI_MFG_IN_SEL], 1); /* 1: hd_faxi_ck */ + mux_set_sel(&muxes[TOP_SCAM_SEL], 1); /* 1: syspll3_d2 */ + /* CLK_CFG_12 */ + mux_set_sel(&muxes[TOP_SPINFI_IFR_SEL], 0); /* 0: clk26m */ + mux_set_sel(&muxes[TOP_HDMI_SEL], 1); /* 1: AD_HDMITX_CLK */ + mux_set_sel(&muxes[TOP_DPILVDS_SEL], 1); /* 1: AD_LVDSPLL_CK */ + /* CLK_CFG_13 */ + mux_set_sel(&muxes[TOP_MSDC50_2_H_SEL], 2); /* 2: syspll2_d2 */ + mux_set_sel(&muxes[TOP_HDCP_SEL], 2); /* 2: syspll3_d4 */ + mux_set_sel(&muxes[TOP_HDCP_24M_SEL], 2); /* 2: univpll_d52 */ + mux_set_sel(&muxes[TOP_RTC_SEL], 1); /* 1: clkrtc_ext */ + /* CLK_CFG_3 */ + mux_set_sel(&muxes[TOP_USB30_SEL], 1); /* 1: univpll3_d2 */ + mux_set_sel(&muxes[TOP_MSDC50_0_H_SEL], 2); /* 2: syspll2_d2 */ + mux_set_sel(&muxes[TOP_MSDC50_0_SEL], 6); /* 6: msdcpll_d4 */ + mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 2); /* 2: msdcpll_d4 */ + + /* enable scpsys clock off control */ + write32(&mt8173_topckgen->clk_scp_cfg_0, + (1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) | + (1 << 1) | (1 << 0)); + write32(&mt8173_topckgen->clk_scp_cfg_1, + (1 << 4) | (1 << 2) | (1 << 0)); +} + +/* after pmic_init */ +void mt_pll_post_init(void) +{ + /* CPU clock divide by 1 */ + clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff); + + /* select ARMPLL */ + /* TODO: possibly raise ARMPLL frequency here */ + /* NOTICE: raise Vproc voltage before raise ARMPLL frequency */ + write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); +}

1 0

New patch to review for coreboot: mediatek/mt8173: Add a stub implementation of the MT8173 SoC
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12587 -gerrit commit 200c1c05ccdf49255908844fbc491b378349c121 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Fri Jul 31 17:10:40 2015 +0800 mediatek/mt8173: Add a stub implementation of the MT8173 SoC BUG=chrome-os-partner:36682 TEST=emerge-oak coreboot BRANCH=none Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292558 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 49 ++++++ src/mainboard/google/oak/Kconfig.name | 2 + src/mainboard/google/oak/Makefile.inc | 31 ++++ src/mainboard/google/oak/bootblock.c | 33 ++++ src/mainboard/google/oak/chromeos.c | 40 +++++ src/mainboard/google/oak/devicetree.cb | 24 +++ src/mainboard/google/oak/mainboard.c | 38 +++++ src/mainboard/google/oak/memlayout.ld | 1 + src/mainboard/google/oak/romstage.c | 38 +++++ src/soc/mediatek/mt8173/Kconfig | 49 ++++++ src/soc/mediatek/mt8173/Makefile.inc | 50 ++++++ src/soc/mediatek/mt8173/bootblock.c | 24 +++ src/soc/mediatek/mt8173/cbfs.c | 25 +++ src/soc/mediatek/mt8173/cbmem.c | 27 ++++ src/soc/mediatek/mt8173/include/soc/addressmap.h | 62 ++++++++ src/soc/mediatek/mt8173/include/soc/infracfg.h | 56 +++++++ src/soc/mediatek/mt8173/include/soc/mcucfg.h | 111 +++++++++++++ src/soc/mediatek/mt8173/include/soc/memlayout.ld | 53 +++++++ src/soc/mediatek/mt8173/include/soc/pericfg.h | 96 ++++++++++++ src/soc/mediatek/mt8173/include/soc/spm.h | 163 +++++++++++++++++++ src/soc/mediatek/mt8173/include/soc/timer.h | 75 +++++++++ src/soc/mediatek/mt8173/soc.c | 49 ++++++ src/soc/mediatek/mt8173/timer.c | 65 ++++++++ src/soc/mediatek/mt8173/uart.c | 189 +++++++++++++++++++++++ 24 files changed, 1350 insertions(+) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig new file mode 100644 index 0000000..a7904ca --- /dev/null +++ b/src/mainboard/google/oak/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_OAK + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8173 + select CHROMEOS_VBNV_EC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select EC_SOFTWARE_SYNC + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + select VIRTUAL_DEV_SWITCH + +config MAINBOARD_DIR + string + default google/oak + +config MAINBOARD_PART_NUMBER + string + default "oak" + +config DRAM_SIZE_MB + int + default 2048 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0 + +endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/oak/Kconfig.name b/src/mainboard/google/oak/Kconfig.name new file mode 100644 index 0000000..49e27d7 --- /dev/null +++ b/src/mainboard/google/oak/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_OAK + bool "Oak" diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc new file mode 100644 index 0000000..dbfc1db --- /dev/null +++ b/src/mainboard/google/oak/Makefile.inc @@ -0,0 +1,31 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bootblock-y += bootblock.c +bootblock-y += memlayout.ld +bootblock-y += chromeos.c + +romstage-y += chromeos.c +romstage-y += romstage.c +romstage-y += memlayout.ld + +ramstage-y += mainboard.c +ramstage-y += chromeos.c +ramstage-y += memlayout.ld + diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c new file mode 100644 index 0000000..ddd71b3 --- /dev/null +++ b/src/mainboard/google/oak/bootblock.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <bootblock_common.h> +#include <delay.h> +#include <soc/pericfg.h> + +void bootblock_mainboard_early_init(void) +{ + /* Clear UART0 power down signal */ + clrbits_le32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c new file mode 100644 index 0000000..8d45a13 --- /dev/null +++ b/src/mainboard/google/oak/chromeos.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/google/oak/devicetree.cb b/src/mainboard/google/oak/devicetree.cb new file mode 100644 index 0000000..75045c6 --- /dev/null +++ b/src/mainboard/google/oak/devicetree.cb @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/mediatek/mt8173 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c new file mode 100644 index 0000000..6e0617e --- /dev/null +++ b/src/mainboard/google/oak/mainboard.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <boardid.h> +#include <boot/coreboot_tables.h> +#include <device/device.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "oak", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/oak/memlayout.ld b/src/mainboard/google/oak/memlayout.ld new file mode 100644 index 0000000..ead7f47 --- /dev/null +++ b/src/mainboard/google/oak/memlayout.ld @@ -0,0 +1 @@ +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c new file mode 100644 index 0000000..268f15f --- /dev/null +++ b/src/mainboard/google/oak/romstage.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/cache.h> +#include <arch/cpu.h> +#include <arch/exception.h> +#include <arch/io.h> + +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <program_loading.h> +#include <romstage_handoff.h> +#include <symbols.h> + +void main(void) +{ + /* init uart baudrate when pll on */ + console_init(); + exception_init(); + + run_ramstage(); +} diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig new file mode 100644 index 0000000..0f0b134 --- /dev/null +++ b/src/soc/mediatek/mt8173/Kconfig @@ -0,0 +1,49 @@ +config SOC_MEDIATEK_MT8173 + bool + default n + select ARM64_A53_ERRATUM_843419 + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select HAVE_UART_SPECIAL + select SPI_ATOMIC_SEQUENCING + select HAVE_MONOTONIC_TIMER + select GENERIC_UDELAY + select HAS_PRECBMEM_TIMESTAMP_REGION + +if SOC_MEDIATEK_MT8173 + +config DEBUG_SOC_DRIVER + bool "The top level switch for soc driver debug message" + default n + select DEBUG_DRAM + select DEBUG_I2C + select DEBUG_PMIC + select DEBUG_PMIC_WRAP + +config DEBUG_DRAM + bool "Output verbose DRAM related debug message" + default n + help + This option enables additional DRAM related debug messages. + +config DEBUG_I2C + bool "Output verbose I2C related debug message" + default n + help + This option enables I2C related debug message. + +config DEBUG_PMIC + bool "Output verbose PMIC related debug message" + default n + help + This option enables PMIC related debug message. + +config DEBUG_PMIC_WRAP + bool "Output verbose PMIC WRAP related debug message" + default n + help + This option enables PMIC WRAP related debug message. +endif diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc new file mode 100644 index 0000000..74a7618 --- /dev/null +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2015 MediaTek Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y) + +bootblock-y += bootblock.c +bootblock-y += cbfs.c +bootblock-y += timer.c + +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_DRIVERS_UART) += uart.c +endif + +################################################################################ + +romstage-y += cbfs.c +romstage-y += timer.c + +romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += cbmem.c + +################################################################################ + +ramstage-y += cbmem.c +ramstage-y += cbfs.c +ramstage-y += soc.c +ramstage-y += timer.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include + +endif diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c new file mode 100644 index 0000000..232a655 --- /dev/null +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/mediatek/mt8173/cbfs.c b/src/soc/mediatek/mt8173/cbfs.c new file mode 100644 index 0000000..71f7ef5 --- /dev/null +++ b/src/soc/mediatek/mt8173/cbfs.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot_device.h> + +const struct region_device *boot_device_ro(void) +{ + return NULL; +} diff --git a/src/soc/mediatek/mt8173/cbmem.c b/src/soc/mediatek/mt8173/cbmem.c new file mode 100644 index 0000000..9a8ae7c --- /dev/null +++ b/src/soc/mediatek/mt8173/cbmem.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <stddef.h> +#include <symbols.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t) _dram + (CONFIG_DRAM_SIZE_MB << 20)); +} diff --git a/src/soc/mediatek/mt8173/include/soc/addressmap.h b/src/soc/mediatek/mt8173/include/soc/addressmap.h new file mode 100644 index 0000000..37a22ab --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/addressmap.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ +#define __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + VER_BASE = 0x08000000, + IO_PHYS = 0x10000000, + DDR_BASE = 0x40000000 +}; + +enum { + CKSYS_BASE = IO_PHYS, + INFRACFG_AO_BASE = IO_PHYS + 0x1000, + PERI_CON_BASE = IO_PHYS + 0x3000, + CHA_DRAMCAO_BASE = IO_PHYS + 0x4000, + GPIO_BASE = IO_PHYS + 0x5000, + SPM_BASE = IO_PHYS + 0x6000, + RGU_BASE = IO_PHYS + 0x7000, + GPT_BASE = IO_PHYS + 0x8000, + PMIC_WRAP_BASE = IO_PHYS + 0xD000, + CHA_DDRPHY_BASE = IO_PHYS + 0xF000, + CHB_DRAMCAO_BASE = IO_PHYS + 0x11000, + CHB_DDRPHY_BASE = IO_PHYS + 0x12000, + MCUCFG_BASE = IO_PHYS + 0x200000, + EMI_BASE = IO_PHYS + 0x203000, + EFUSE_BASE = IO_PHYS + 0x206000, + APMIXED_BASE = IO_PHYS + 0x209000, + CHA_DRAMCNAO_BASE = IO_PHYS + 0x20E000, + CHB_DRAMCNAO_BASE = IO_PHYS + 0x213000, + ANA_MIPI_CS1_BASE = IO_PHYS + 0x218000, + UART0_BASE = IO_PHYS + 0x1002000, + SPI_BASE = IO_PHYS + 0x100A000, + I2C_BASE = IO_PHYS + 0x1007000, + I2C_DMA_BASE = IO_PHYS + 0x1000080, + SFLASH_REG_BASE = IO_PHYS + 0x100D000, + SSUSB_MAC_BASE = IO_PHYS + 0x1270000, + SSUSB_IPPC_BASE = IO_PHYS + 0x1280700, + SSUSB_SIF_BASE = IO_PHYS + 0x1290800, +}; + +#endif /* __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H___ */ diff --git a/src/soc/mediatek/mt8173/include/soc/infracfg.h b/src/soc/mediatek/mt8173/include/soc/infracfg.h new file mode 100644 index 0000000..5761420 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/infracfg.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_INFRACFG_H__ +#define __SOC_MEDIATEK_MT8173_INFRACFG_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8173_infracfg_regs { + u32 top_ckmuxsel; + u32 reserved0; + u32 top_ckdiv1; + u32 reserved1; + u32 top_dcmctl; + u32 top_dcmdbc; + u32 reserved2[6]; + u32 infra_rst0; + u32 infra_rst1; + u32 reserved3[2]; + u32 infra_pdn0; + u32 infra_pdn1; + u32 reserved4[118]; + u32 topaxi_prot_en; + u32 topaxi_prot_sta0; + u32 topaxi_prot_sta1; /* 0x228 */ +}; + +check_member(mt8173_infracfg_regs, infra_pdn0, 0x40); +check_member(mt8173_infracfg_regs, topaxi_prot_sta1, 0x228); + +static struct mt8173_infracfg_regs *const mt8173_infracfg = + (void *)INFRACFG_AO_BASE; + +enum { + INFRA_PMIC_WRAP_RST = 1 << 7, + L2C_SRAM_PDN = 1 << 7 +}; + +#endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/mcucfg.h b/src/soc/mediatek/mt8173/include/soc/mcucfg.h new file mode 100644 index 0000000..5ac3474 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mcucfg.h @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MCUCFG_H__ +#define __SOC_MEDIATEK_MT8173_MCUCFG_H__ + +#include <soc/addressmap.h> + +struct mt8173_mcucfg_regs { + u32 mp0_ca7l_cache_config; + struct { + u32 mem_delsel0; + u32 mem_delsel1; + } mp0_cpu[4]; + u32 mp0_cache_mem_delsel0; + u32 mp0_cache_mem_delsel1; + u32 mp0_axi_config; + u32 mp0_misc_config[10]; + u32 mp0_ca7l_cfg_dis; + u32 mp0_ca7l_clken_ctrl; + u32 mp0_ca7l_rst_ctrl; + u32 mp0_ca7l_misc_config; + u32 mp0_ca7l_dbg_pwr_ctrl; + u32 mp0_rw_rsvd0; + u32 mp0_rw_rsvd1; + u32 mp0_ro_rsvd; + u32 reserved0_0[100]; + u32 mp1_cpucfg; + u32 mp1_miscdbg; + u32 reserved0_1[13]; + u32 mp1_rst_ctl; + u32 mp1_clkenm_div; + u32 reserved0_2[7]; + u32 mp1_config_res; + u32 reserved0_3[101]; + u32 mp0_rst_status; /* 0x400 */ + u32 mp0_dbg_ctrl; + u32 mp0_dbg_flag; + u32 mp0_ca7l_ir_mon; + struct { + u32 pc_lw; + u32 pc_hw; + u32 fp_arch32; + u32 sp_arch32; + u32 fp_arch64_lw; + u32 fp_arch64_hw; + u32 sp_arch64_lw; + u32 sp_arch64_hw; + } mp0_dbg_core[4]; + u32 dfd_ctrl; + u32 dfd_cnt_l; + u32 dfd_cnt_h; + u32 misccfg_mp0_rw_rsvd; + u32 misccfg_sec_vio_status0; + u32 misccfg_sec_vio_status1; + u32 reserved1[22]; + u32 misccfg_rw_rsvd; /* 0x500 */ + u32 mcusys_dbg_mon_sel_a; + u32 mcusys_dbg_mon; + u32 reserved2[61]; + u32 mcusys_config_a; /* 0x600 */ + u32 mcusys_config1_a; + u32 mcusys_gic_peribase_a; + u32 reserved3; + u32 sec_range0_start; /* 0x610 */ + u32 sec_range0_end; + u32 sec_range_enable; + u32 reserved4; + u32 int_pol_ctl[8]; /* 0x620 */ + u32 aclken_div; /* 0x640 */ + u32 pclken_div; + u32 l2c_sram_ctrl; + u32 armpll_jit_ctrl; + u32 cci_addrmap; /* 0x650 */ + u32 cci_config; + u32 cci_periphbase; + u32 cci_nevntcntovfl; + u32 cci_clk_ctrl; /* 0x660 */ + u32 cci_acel_s1_ctrl; + u32 bus_fabric_dcm_ctrl; + u32 reserved5; + u32 xgpt_ctl; /* 0x670 */ + u32 xgpt_idx; + u32 ptpod2_ctl0; + u32 ptpod2_ctl1; + u32 mcusys_revid; + u32 mcusys_rw_rsvd0; + u32 mcusys_rw_rsvd1; +}; + +check_member(mt8173_mcucfg_regs, mcusys_rw_rsvd1, 0x688); + +static struct mt8173_mcucfg_regs * const mt8173_mcucfg = (void *)MCUCFG_BASE; + +#endif /* __SOC_MEDIATEK_MT8173_MCUCFG_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld new file mode 100644 index 0000000..a703808 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM. + * It will be returned before starting the ramstage. + * SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able. + */ +#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr) +#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr) + +SECTIONS +{ + SRAM_L2C_START(0x000C0000) + BOOTBLOCK(0x000C1000, 85K) + VERSTAGE(0x000D7000, 114K) + PRERAM_CBFS_CACHE(0x000F6000, 16K) + SRAM_L2C_END(0x00100000) + + SRAM_START(0x00100000) + VBOOT2_WORK(0x00100000, 12K) + PRERAM_CBMEM_CONSOLE(0x00103000, 16K) + TIMESTAMP(0x00107000, 4K) + ROMSTAGE(0x00108000, 92K) + STACK(0x00124000, 16K) + TTB(0x00128000, 28K) + DMA_COHERENT(0x0012F000, 4K) + SRAM_END(0x00130000) + + DRAM_START(0x40000000) + POSTRAM_CBFS_CACHE(0x40100000, 1M) + RAMSTAGE(0x40200000, 256K) +} diff --git a/src/soc/mediatek/mt8173/include/soc/pericfg.h b/src/soc/mediatek/mt8173/include/soc/pericfg.h new file mode 100644 index 0000000..d2ea0de --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/pericfg.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_PERICFG_H__ +#define __SOC_MEDIATEK_MT8173_PERICFG_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8173_pericfg_regs { + u32 rst0; + u32 rst1; + u32 pdn0_set; + u32 pdn1_set; + u32 pdn0_clr; + u32 pdn1_clr; + u32 pdn0_sta; + u32 pdn1_sta; + u32 pdn_md1_set; + u32 pdn_md2_set; + u32 pdn_md1_clr; + u32 pdn_md2_clr; + u32 pdn_md1_sta; + u32 pdn_md2_sta; + u32 pdn_md_mask; + u32 reserved0[5]; + u32 dcmctl; + u32 dcmdbc; + u32 dcmfsel; + u32 cksel; + u32 reserved1[104]; + u32 axi_bus_ctl1; + u32 axi_bus_ctl2; + u32 axi_bus_ctl3; + u32 axi_si0_ctl; + u32 axi_si1_ctl; + u32 axi_mi_sta; + u32 reserved2[58]; + u32 axi_ahb_lmt_con1; + u32 axi_ahb_lmt_con2; + u32 axi_ahb_lmt_con3; + u32 axi_ahb_lmt_con4; + u32 axi_ahb_lmt_con5; + u32 axi_ahb_lmt_con6; + u32 reserved3[2]; + u32 axi_axi_lmt_con1; + u32 axi_axi_lmt_con2; + u32 axi_axi_lmt_con3; + u32 axi_axi_lmt_con4; + u32 axi_axi_lmt_con5; + u32 axi_axi_lmt_con6; + u32 axi_axi_lmt_con7; + u32 axi_axi_lmt_con8; + u32 axi_axi_lmt_con9; + u32 reserved4[47]; + u32 usb_wakeup_dec_con0; + u32 usb_wakeup_dec_con1; + u32 usb_wakeup_dec_con2; + u32 uart_ck_source_sel; + u32 reserved5[1]; + u32 usb_wakeup_dec_con3a; + u32 reserved6[58]; + u32 ssusb_rst; + u32 ssusb_pdn_set; + u32 ssusb_pdn_clr; + u32 ssusb_pdn_sta; +}; + +static struct mt8173_pericfg_regs * const mt8173_pericfg = + (void *)PERI_CON_BASE; + +/* + * UART power down control + */ + +enum { + PERICFG_UART0_PDN = 1 << 19 +}; + +#endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h new file mode 100644 index 0000000..a4d6d64 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/spm.h @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_SPM_H__ +#define __SOC_MEDIATEK_MT8173_SPM_H__ + +#include <soc/addressmap.h> +#include <stddef.h> + +enum { + SPM_PROJECT_CODE = 0xb16 +}; + +struct mt8173_spm_regs { + u32 poweron_config_set; + u32 reserved1[3]; + u32 power_on_val0; /* 0x010 */ + u32 power_on_val1; + u32 reserved2[58]; + u32 clk_settle; /* 0x100 */ + u32 reserved3[63]; + u32 ca7_cpu0_pwr_con; /* 0x200 */ + u32 ca7_dbg_pwr_con; + u32 ca7_cputop_pwr_con; + u32 reserved4; + u32 vde_pwr_con; /* 0x210 */ + u32 mfg_pwr_con; + u32 ca7_cpu1_pwr_con; /* 0x218 */ + u32 ca7_cpu2_pwr_con; + u32 ca7_cpu3_pwr_con; /* 0x220 */ + u32 reserved5[3]; + u32 ven_pwr_con; /* 0x230 */ + u32 ifr_pwr_con; + u32 isp_pwr_con; + u32 dis_pwr_con; + u32 dpy_pwr_con; /* 0x240 */ + u32 ca7_cputop_l2_pdn; /* 0x244 */ + u32 ca7_cputop_l2_sleep; + u32 reserved6[4]; + struct { /* 0x25c */ + u32 l1_pdn; + u32 reserved; + } ca7_cpu[4]; + u32 gcpu_sram_con; /* 0x27c */ + u32 dpy2_pwr_con; /* 0x280 */ + u32 md_pwr_con; + u32 reserved11[2]; + u32 mcu_pwr_con; /* 0x290 */ + u32 ifr_sramrom_con; + u32 mjc_pwr_con; + u32 audio_pwr_con; + u32 ca15_cpu_pwr_con[4]; /* 0x2a0 */ + u32 ca15_cputop_pwr_con; /* 0x2b0 */ + u32 ca15_l1_pwr_con; /* 0x2b4 */ + u32 ca15_l2_pwr_con; /* 0x2b8 */ + u32 reserved12; + u32 mfg_2d_pwr_con; /* 0x2c0 */ + u32 mfg_async_pwr_con; + u32 vpu_sram_con; + u32 reserved13[17]; + u32 pcm_con0; /* 0x310 */ + u32 pcm_con1; + u32 pcm_im_ptr; + u32 pcm_im_len; + u32 pcm_reg_data_ini; /* 0x320 */ + u32 reserved14[7]; + u32 pcm_event_vector0; /* 0x340 */ + u32 pcm_event_vector1; + u32 pcm_event_vector2; + u32 pcm_event_vector3; + u32 reserved15; + u32 pcm_mas_pause_mask; /* 0x354 */ + u32 pcm_pwr_io_en; + u32 pcm_timer_val; + u32 pcm_timer_out; + u32 reserved16[7]; + u32 pcm_reg_data[16]; /* 0x380 */ + u32 pcm_event_reg_sta; + u32 pcm_fsm_sta; + u32 pcm_im_host_rw_ptr; + u32 pcm_im_host_rw_dat; + u32 pcm_event_vector4; + u32 pcm_event_vector5; + u32 pcm_event_vector6; + u32 pcm_event_vector7; + u32 pcm_sw_int_set; + u32 pcm_sw_int_clear; + u32 reserved17[6]; + u32 clk_con; /* 0x400 */ + u32 sleep_dual_vcore_pwr_con; /* 0x404 */ + u32 sleep_ptpod2_con; + u32 reserved18[125]; + u32 apmcu_pwrctl; /* 0x600 */ + u32 ap_dvfs_con_set; + u32 ap_stanby_con; + u32 pwr_status; /* 0x60c */ + u32 pwr_status_2nd; /* 0x610 */ + u32 ap_bsi_req; + u8 reserved19[0x720 - 0x618]; + u32 sleep_timer_sta; /* 0x720 */ + u32 reserved20[15]; + u32 sleep_twam_con; /* 0x760 */ + u32 sleep_twam_status0; + u32 sleep_twam_status1; + u32 sleep_twam_status2; + u32 sleep_twam_status3; /* 0x770 */ + u32 reserved21[39]; + u32 sleep_wakeup_event_mask; /* 0x810 */ + u32 sleep_cpu_wakeup_event; + u32 sleep_md32_wakeup_event_mask; + u32 reserved22[2]; + u32 pcm_wdt_timer_val; /* 0x824 */ + u32 pcm_wdt_timer_out; + u32 reserved23; + u32 pcm_md32_mailbox; /* 0x830 */ + u32 pcm_md32_irq; + u32 reserved24[50]; + u32 sleep_isr_mask; /* 0x900 */ + u32 sleep_isr_status; + u32 reserved25[2]; + u32 sleep_isr_raw_sta; /* 0x910 */ + u32 sleep_md32_isr_raw_sta; + u32 sleep_wakeup_misc; + u32 sleep_bus_protect_rdy; + u32 sleep_subsys_idle_sta; /* 0x920 */ + u8 reserved26[0xb00 - 0x924]; + u32 pcm_reserve; /* 0xb00 */ + u32 pcm_reserve2; + u32 pcm_flags; + u32 pcm_src_req; + u32 reserved27[4]; + u32 pcm_debug_con; /* 0xb20 */ + u32 reserved28[3]; + u32 ca7_cpu_irq_mask[4]; /* 0xb30 */ + u32 ca15_cpu_irq_mask[4]; + u32 reserved29[4]; + u32 pcm_pasr_dpd[4]; /* 0xb60 */ + u8 reserved30[0xf00 - 0xb70]; + u32 sleep_ca7_wfi_en[4]; /* 0xf00 */ + u32 sleep_ca15_wfi_en[4]; +}; + +check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c); + +static struct mt8173_spm_regs * const mt8173_spm = (void *)SPM_BASE; + +#endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */ diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h new file mode 100644 index 0000000..b38feb0 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/timer.h @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_TIMER_H__ +#define __SOC_MEDIATEK_MT8173_TIMER_H__ + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8173_gpt_regs { + u32 irqen; + u32 irqsta; + u32 irqack; + u32 reserved0; + u32 gpt1_con; + u32 gpt1_clk; + u32 gpt1_cnt; + u32 gpt1_compare; + u32 gpt2_con; + u32 gpt2_clk; + u32 gpt2_cnt; + u32 gpt2_compare; + u32 gpt3_con; + u32 gpt3_clk; + u32 gpt3_cnt; + u32 gpt3_compare; + u32 gpt4_con; + u32 gpt4_clk; + u32 gpt4_cnt; + u32 gpt4_compare; + u32 gpt5_con; + u32 gpt5_clk; + u32 gpt5_cnt; + u32 gpt5_compare; + u32 gpt6_con; + u32 gpt6_clk; + u32 gpt6_cntl; + u32 gpt6_comparel; + u32 reserved1[2]; + u32 gpt6_cnth; + u32 gpt6_compareh; + u32 apxgpt_irqmask; + u32 apxgpt_irqmask1; +}; + +static struct mt8173_gpt_regs * const mt8173_gpt = (void *)GPT_BASE; + +enum { + GPT_CON_EN = 0x01, + GPT_CON_CLR = 0x02, + GPT_MODE_ONE_SHOT = 0x00, + GPT_MODE_REPEAT = 0x10, + GPT_MODE_KEEP_GO = 0x20, + GPT_MODE_FREERUN = 0x30, + GPT_SYS_CLK = 0x00, + GPT_SYS_RTC = 0x01, +}; + +#endif /* __SOC_MEDIATEK_MT8173_TIMER_H__ */ diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c new file mode 100644 index 0000000..643c622 --- /dev/null +++ b/src/soc/mediatek/mt8173/soc.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <console/console.h> +#include <device/device.h> + +#include <symbols.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, + CONFIG_DRAM_SIZE_MB * KiB); +} + +static void soc_init(device_t dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8173_ops = { + CHIP_NAME("SOC Mediatek MT8173\n") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/mediatek/mt8173/timer.c b/src/soc/mediatek/mt8173/timer.c new file mode 100644 index 0000000..d23c230 --- /dev/null +++ b/src/soc/mediatek/mt8173/timer.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +#include <soc/addressmap.h> +#include <soc/mcucfg.h> +#include <soc/timer.h> + +#define GPT4_MHZ 13 + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, read32(&mt8173_gpt->gpt4_cnt) / GPT4_MHZ); +} + +/** + * init_timer - initialize timer + */ +void init_timer(void) +{ + /* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed + * with following definition. + * + * [10: 8] Clock mode + * 100: 26Mhz / 4 + * 010: 26Mhz / 2 + * 001: 26Mhz + * [ 1: 1] Halt-on-debug enable bit + * [ 0: 0] XGPT enable bit + */ + write32(&mt8173_mcucfg->xgpt_idx, 0); + /* Set clock mode to 13Mhz and enable XGPT */ + write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8))); + + /* Disable GPT4 and clear the counter */ + clrbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_EN); + setbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_CLR); + + /* Set clock source to system clock and set clock divider to 1 */ + write32(&mt8173_gpt->gpt4_clk, GPT_SYS_CLK | 0x0); + /* Set operation mode to FREERUN mode and enable GTP4 */ + write32(&mt8173_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN); +} + diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c new file mode 100644 index 0000000..bd239c7 --- /dev/null +++ b/src/soc/mediatek/mt8173/uart.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> +#include <stdint.h> + +#include <soc/addressmap.h> + +struct mtk_uart { + union { + uint32_t thr; /* Transmit holding register. */ + uint32_t rbr; /* Receive buffer register. */ + uint32_t dll; /* Divisor latch lsb. */ + }; + union { + uint32_t ier; /* Interrupt enable register. */ + uint32_t dlm; /* Divisor latch msb. */ + }; + union { + uint32_t iir; /* Interrupt identification register. */ + uint32_t fcr; /* FIFO control register. */ + uint32_t efr; /* Enhanced feature register. */ + }; + uint32_t lcr; /* Line control register. */ + union { + uint32_t mcr; /* Modem control register. */ + uint32_t xn1; /* XON1 */ + }; + union { + uint32_t lsr; /* Line status register. */ + uint32_t xn2; /* XON2 */ + }; + union { + uint32_t msr; /* Modem status register. */ + uint32_t xf1; /* XOFF1 */ + }; + union { + uint32_t scr; /* Scratch register. */ + uint32_t xf2; /* XOFF2 */ + }; + uint32_t autobaud_en; /* Enable auto baudrate. */ + uint32_t highspeed; /* High speed UART. */ +} __attribute__ ((packed)); + +/* Peripheral Reset and Power Down registers */ +struct mtk_peri_globalcon { + uint32_t rst0; + uint32_t rst1; + uint32_t pdn0_set; + uint32_t pdn1_set; + uint32_t pdn0_clr; + uint32_t pdn1_clr; + uint32_t pdn0_sta; + uint32_t pdn1_sta; + uint32_t pdn_md1_set; + uint32_t pdn_md2_set; + uint32_t pdn_md1_clr; + uint32_t pdn_md2_clr; + uint32_t pdn_md1_sta; + uint32_t pdn_md2_sta; + uint32_t pdn_md_mask; +} __attribute__ ((packed)); + +static struct mtk_uart *const uart_ptr = (void *)UART0_BASE; + +static void mtk_uart_tx_flush(void); +static int mtk_uart_tst_byte(void); + +static void mtk_uart_init(void) +{ + /* Use a hardcoded divisor for now. */ + const unsigned uartclk = 26 * MHz; + const unsigned baudrate = CONFIG_TTYS0_BAUD; + const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */ + unsigned highspeed, quot, divisor, remainder; + + if (baudrate <= 115200) { + highspeed = 0; + quot = 16; + } else { + highspeed = 2; + quot = 4; + } + + /* Set divisor DLL and DLH */ + divisor = uartclk / (quot * baudrate); + remainder = uartclk % (quot * baudrate); + + if (remainder >= (quot / 2) * baudrate) + divisor += 1; + + mtk_uart_tx_flush(); + + /* Disable interrupts. */ + write8(&uart_ptr->ier, 0); + /* Force DTR and RTS to high. */ + write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS); + /* Set High speed UART register. */ + write8(&uart_ptr->highspeed, highspeed); + /* Set line configuration, access divisor latches. */ + write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config); + /* Set the divisor. */ + write8(&uart_ptr->dll, divisor & 0xff); + write8(&uart_ptr->dlm, (divisor >> 8) & 0xff); + /* Hide the divisor latches. */ + write8(&uart_ptr->lcr, line_config); + /* Enable FIFOs, and clear receive and transmit. */ + write8(&uart_ptr->fcr, + UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | + UART8250_FCR_CLEAR_XMIT); + +} + +static void mtk_uart_tx_byte(unsigned char data) +{ + while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE)); + write8(&uart_ptr->thr, data); +} + +static void mtk_uart_tx_flush(void) +{ + while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT)); +} + +static unsigned char mtk_uart_rx_byte(void) +{ + if (!mtk_uart_tst_byte()) + return 0; + return read8(&uart_ptr->rbr); +} + +static int mtk_uart_tst_byte(void) +{ + return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR; +} + +void uart_init(int idx) +{ + mtk_uart_init(); +} + +unsigned char uart_rx_byte(int idx) +{ + return mtk_uart_rx_byte(); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + mtk_uart_tx_byte(data); +} + +void uart_tx_flush(int idx) +{ + mtk_uart_tx_flush(); +} + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = UART0_BASE; + serial.baud = default_baudrate(); + serial.regwidth = 1; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

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New patch to review for coreboot: cbfs_spi: enable CBFS access in early romstage
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12586 -gerrit commit 4f4949db0f010349708f233a10e16255800977c1 Author: Mary Ruthven <mruthven(a)chromium.org> Date: Fri Nov 13 14:05:27 2015 -0800 cbfs_spi: enable CBFS access in early romstage Currently the CBFS mmap cannot be accessed at the beginning of romstage because it waits until DRAM is initialized. This change first loads CBFS into SRAM and then switches to using DRAM as the backing once it is initialized. BUG=chromium:210230 BRANCH=none TEST=confirm that the cbfs can be access at the beginning and end of romstage on different boards. Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83 Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796 Original-Signed-off-by: Mary Ruthven <mruthven(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312577 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/memlayout.h | 8 +++++--- src/include/symbols.h | 4 ++++ src/lib/cbfs_spi.c | 7 +++++++ src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 15 ++------------- 4 files changed, 18 insertions(+), 16 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 0344297..899836c 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -79,9 +79,11 @@ /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */ #define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4) -/* TODO: This only works if you never access CBFS in romstage before RAM is up! - * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !ENV_ROMSTAGE +#if ENV_ROMSTAGE + #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) + #define POSTRAM_CBFS_CACHE(addr, size) \ + REGION(dram_cbfs_cache, addr, size, 4) +#elif defined(__PRE_RAM__) #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) diff --git a/src/include/symbols.h b/src/include/symbols.h index 52fea48..bf875ae 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -41,6 +41,10 @@ extern u8 _stack[]; extern u8 _estack[]; #define _stack_size (_estack - _stack) +extern u8 _dram_cbfs_cache[]; +extern u8 _edram_cbfs_cache[]; +#define _dram_cbfs_cache_size (_edram_cbfs_cache - _dram_cbfs_cache) + extern u8 _cbfs_cache[]; extern u8 _ecbfs_cache[]; #define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache) diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c index 31a2e79..82c3b83 100644 --- a/src/lib/cbfs_spi.c +++ b/src/lib/cbfs_spi.c @@ -22,6 +22,7 @@ #include <boot_device.h> #include <spi_flash.h> #include <symbols.h> +#include <cbmem.h> static struct spi_flash *spi_flash_info; @@ -42,6 +43,12 @@ static const struct region_device_ops spi_ops = { static struct mmap_helper_region_device mdev = MMAP_HELPER_REGION_INIT(&spi_ops, 0, CONFIG_ROM_SIZE); +static void initialize_mdev(int unused) +{ + mmap_helper_device_init(&mdev, _dram_cbfs_cache, _dram_cbfs_cache_size); +} +ROMSTAGE_CBMEM_INIT_HOOK(initialize_mdev); + void boot_device_init(void) { int bus = CONFIG_BOOT_MEDIA_SPI_BUS; diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 60fb582..6ff2b77 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,16 +38,7 @@ SECTIONS QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) -#ifdef __PRE_RAM__ - /* - * ipq8064 is different from most other ARM platforms: it loads the - * proprietary DRAM initialization code from CBFS (as opposed to compiling - * it in into rombase). As a result CBFS needs to be used before DRAM is - * availale, which means CBFS cache must be in SRAM, which in turn means - * that PRERAM_CBFS_CACHE description can not be used here. - */ - CBFS_CACHE(0x2A044000, 93K) -#endif + PRERAM_CBFS_CACHE(0x2A044000, 93K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) SRAM_END(0x2A060000) @@ -55,8 +46,6 @@ SECTIONS DRAM_START(0x40000000) RAMSTAGE(0x40640000, 128K) SYMBOL(memlayout_cbmem_top, 0x59F80000) -#ifndef __PRE_RAM__ - CBFS_CACHE(0x59F80000, 384K) -#endif + POSTRAM_CBFS_CACHE(0x59F80000, 384K) DMA_COHERENT(0x5A000000, 2M) }

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New patch to review for coreboot: arch/arm64: introduce mmu to bootblock and romstage
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12585 -gerrit commit 7f4951843bf42c6c42aa4729c095bb2d66fd9f28 Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Fri Jul 31 17:10:49 2015 +0800 arch/arm64: introduce mmu to bootblock and romstage We need mmu interfaces in these two stages for, 1. bootblock: to support mmu initialization in bootblock 2. romstage: to be able to add dram range to mmu table BRANCH=none BUG=none TEST=build pass Change-Id: I56dea5f958a48b875579f546ba17a5dd6eaf159c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cf72736bda2233f8e0bdd7a8ca3245f1d941ee86 Original-Change-Id: I1e27c0a0a878f7bc0ff8712bee640ec3fd8dbb8b Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292665 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/armv8/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 53d0e46..f026a99 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -30,6 +30,8 @@ endif bootblock-y += cache.c bootblock-y += cache_helpers.S bootblock-y += cpu.S +bootblock-y += mmu.c + bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c bootblock-generic-ccopts += $(armv8_flags) @@ -65,6 +67,7 @@ romstage-y += cache.c romstage-y += cache_helpers.S romstage-y += cpu.S romstage-y += exception.c +romstage-y += mmu.c romstage-generic-ccopts += $(armv8_flags)

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coreboot-gerrit December 2015