coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

Patch merged into coreboot/master: nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 09830faa8d8132954f0a6033f3e0cde05be9aef8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 18:07:43 2015 -0500 nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs The existing code re-used the Family 10h XCS buffer setup on Family 15h CPUs, which set incorrect values leading to random system lockups. Use the Family 15h XCS buffer setup shown in the BKDG. Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12070 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 346fcb2894c726574eb55ff08c10fcf10f1de905 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 18:07:03 2015 -0500 cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0 Minor change to be more explicit about the binary state of the iolink detect variable. Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12069 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/12069 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/amdfam10: Fix incorrect channel buffer count configuration
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 93107bebf6bc4b550bd3a98e466dfe18389659b6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 03:39:15 2015 -0500 nb/amd/amdfam10: Fix incorrect channel buffer count configuration The secondary bus number set code incorrectly overwrote the link buffer settings in F0x[F4,D4,B4,94]. Constrain the secondary bus number set to the appropriate bits of the registers. Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12068 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Enable GART by default
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit f1436e58d292bcfd389ac786e83bb93ea6e0a086 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 19:27:40 2015 -0500 mainboard/asus/kgpe-d16: Enable GART by default Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12067 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Add Family 15h tristate enable codes
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 5edc6695f8fb129a89a80af592b8b3342377a871 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 27 23:37:38 2015 -0500 nb/amd/mct_ddr3: Add Family 15h tristate enable codes The Family 15h DRAM initialization did not set up the various tristate enable codes in the MCT. Add Family 15h tristate enable setup. This fixes multiple DIMMs on a single channel. Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12060 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See https://review.coreboot.org/12060 for details. -gerrit

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Patch merged into coreboot/master: amd/pi/00630F01: Drop HT3_SUPPORT
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit d45a3477b79df14ed13a64e580a26380ebfb2565 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 21:51:03 2015 -0700 amd/pi/00630F01: Drop HT3_SUPPORT The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented. This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT) Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12556 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/12556 for details. -gerrit

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Patch merged into coreboot/master: Makefile.inc: make sure .xcompile is removed when building tools
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 317b58234ab79be65320f0acb00b6990a8cc7b51 Author: Martin Roth <martinroth(a)google.com> Date: Sun Nov 29 11:28:26 2015 -0700 Makefile.inc: make sure .xcompile is removed when building tools Most of the toolchain build targets already ran clean-for-update, but there were a few that didn't. Add the clean to those targets. Change-Id: I7faad32ac8bb1815e0c58e7d142ca2dbfc877896 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12571 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12571 for details. -gerrit

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Patch set updated for coreboot: southbridge/amd/sr5650: Add MCFG ACPI table support
by Timothy Pearson 01 Dec '15

01 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12050 -gerrit commit 3db2dafe51bc17c4358f976d532f748c27748abc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 15:20:42 2015 -0500 southbridge/amd/sr5650: Add MCFG ACPI table support Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--- src/southbridge/amd/rs780/rs780.c | 12 ++++ src/southbridge/amd/sb700/lpc.c | 6 -- src/southbridge/amd/sb800/lpc.c | 7 +- src/southbridge/amd/sr5650/Kconfig | 9 +++ src/southbridge/amd/sr5650/ht.c | 107 ++++++++++++++++++++++++++++- src/southbridge/amd/sr5650/sr5650.c | 18 +++++ 7 files changed, 156 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c8bf8fa..b376171 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -737,16 +737,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_MMCONF_SUPPORT - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); -#endif + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT) && !IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); + } if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c82a629..6eb4295 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -349,6 +350,17 @@ void rs780_enable(device_t dev) } } +#if !IS_ENABLED(CONFIG_AMD_SB_CIMX) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* FIXME + * Leave table blank until proper contents + * are determined. + */ + return current; +} +#endif + struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("ATI RS780") .enable_dev = rs780_enable, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a71fe1f..78933fa 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -30,12 +30,6 @@ #include <cpu/amd/powernow.h> #include "sb700.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 756a0c4..18d4471 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,6 @@ #include <arch/acpi.h> #include "sb800.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig index 29017c6..f2d12ff 100644 --- a/src/southbridge/amd/sr5650/Kconfig +++ b/src/southbridge/amd/sr5650/Kconfig @@ -15,3 +15,12 @@ config SOUTHBRIDGE_AMD_SR5650 bool + +if SOUTHBRIDGE_AMD_SR5650 +config EXT_CONF_SUPPORT + bool "Enable PCI-E MMCONFIG support" + default n + help + Select to enable PCI-E MMCONFIG support on the SR5650. + +endif diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 6119985..e74d36b 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -20,7 +20,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/ioapic.h> +#include <lib.h> #include "sr5650.h" +#include "cmn.h" /* Table 6-6 Recommended Interrupt Routing Configuration */ typedef struct _apic_device_info { @@ -154,11 +156,29 @@ static void pcie_init(struct device *dev) static void sr5690_read_resource(struct device *dev) { + struct resource *res; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + } + pci_dev_read_resources(dev); /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + res = new_resource(dev, 0x1c); /* PCIe MCFG space */ + res->base = EXT_CONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_ASSIGNED | IORESOURCE_RESERVE | IORESOURCE_BRIDGE; + } compact_resources(dev); } @@ -166,7 +186,88 @@ static void sr5690_read_resource(struct device *dev) /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ static void sr5690_set_resources(struct device *dev) { - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + uint32_t reg; + device_t amd_ht_cfg_dev; + device_t amd_addr_map_dev; + resource_t res_base; + resource_t res_end; + uint32_t base; + uint32_t limit; + struct resource *res; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + + res = probe_resource(dev, 0x1c); + if (res) { + /* Find requisite AMD CPU devices */ + amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + if (!amd_ht_cfg_dev || !amd_addr_map_dev) { + printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); + } + else { + /* Set up MMCONFIG bus range */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ + pci_write_config32(dev, 0x1c, res->base); + + /* Enable MMCONFIG decoding. */ + set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + + /* Set up nonposted resource in MMIO space */ + res_base = res->base; /* Get the base address */ + res_end = resource_end(res); /* Get the limit (rounded up) */ + printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); + + /* Locate an unused MMIO resource */ + for (reg = 0xb8; reg >= 0x80; reg -= 8) { + base = pci_read_config32(amd_addr_map_dev, reg); + limit = pci_read_config32(amd_addr_map_dev, reg + 4); + if (!(base & 0x3)) + break; /* Unused resource found */ + } + + /* If an unused MMIO resource was available, set up the mapping */ + if (!(base & 0x3)) { + uint32_t sblk; + + /* Remember this resource has been stored. */ + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " <mmconfig>"); + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; + + /* Calculate the MMIO mapping base */ + base &= 0x000000f0; + base |= ((res_base >> 8) & 0xffffff00); + base |= 3; + + /* Calculate the MMIO mapping limit */ + limit &= 0x00000048; + limit |= ((res_end >> 8) & 0xffffff00); + limit |= (sblk << 4); + limit |= (1 << 7); + + /* Configure and enable MMIO mapping */ + printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); + pci_write_config32(amd_addr_map_dev, reg + 4, limit); + pci_write_config32(amd_addr_map_dev, reg, base); + } + else { + printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); + } + } + } + } + pci_dev_set_resources(dev); } diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 07b4a02..54f0071 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -796,6 +796,24 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, i free(root_level); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Report MMCONF base */ + res = probe_resource(dev, 0x1c); + if (res) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); + } + + return current; +} + static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) { uint8_t *p;

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Enable GART by default
by Timothy Pearson 01 Dec '15

01 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12067 -gerrit commit 5dd5cc5c8bef557c81dff5b7110fd6af3c70010f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 19:27:40 2015 -0500 mainboard/asus/kgpe-d16: Enable GART by default Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index b5e9f07..a05b9c3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -23,7 +23,7 @@ maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable ieee1394_controller = Enable -gart = Disable +gart = Enable experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback

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Patch set updated for coreboot: northbridge/amd/amdht: Reduce excessive romstage array size
by Timothy Pearson 01 Dec '15

01 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12573 -gerrit commit 796eee0d0e3264cdd1e3467f2e36ff62ea2d9a9d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Nov 16 11:48:38 2015 -0600 northbridge/amd/amdht: Reduce excessive romstage array size Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/ht_wrapper.c | 48 +++++++++++++++++----------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 18c0ac4..129b02d 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -91,25 +91,25 @@ static const char * event_class_string_decodes[] = { }; static const char * event_string_decodes[] = { - [HT_EVENT_COH_EVENTS] = "HT_EVENT_COH_EVENTS", - [HT_EVENT_COH_NO_TOPOLOGY] = "HT_EVENT_COH_NO_TOPOLOGY", - [HT_EVENT_COH_LINK_EXCEED] = "HT_EVENT_COH_LINK_EXCEED", - [HT_EVENT_COH_FAMILY_FEUD] = "HT_EVENT_COH_FAMILY_FEUD", - [HT_EVENT_COH_NODE_DISCOVERED] = "HT_EVENT_COH_NODE_DISCOVERED", - [HT_EVENT_COH_MPCAP_MISMATCH] = "HT_EVENT_COH_MPCAP_MISMATCH", - [HT_EVENT_NCOH_EVENTS] = "HT_EVENT_NCOH_EVENTS", - [HT_EVENT_NCOH_BUID_EXCEED] = "HT_EVENT_NCOH_BUID_EXCEED", - [HT_EVENT_NCOH_LINK_EXCEED] = "HT_EVENT_NCOH_LINK_EXCEED", - [HT_EVENT_NCOH_BUS_MAX_EXCEED] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", - [HT_EVENT_NCOH_CFG_MAP_EXCEED] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", - [HT_EVENT_NCOH_DEVICE_FAILED] = "HT_EVENT_NCOH_DEVICE_FAILED", - [HT_EVENT_NCOH_AUTO_DEPTH] = "HT_EVENT_NCOH_AUTO_DEPTH", - [HT_EVENT_OPT_EVENTS] = "HT_EVENT_OPT_EVENTS", - [HT_EVENT_OPT_REQUIRED_CAP_RETRY] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", - [HT_EVENT_OPT_REQUIRED_CAP_GEN3] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", - [HT_EVENT_HW_EVENTS] = "HT_EVENT_HW_EVENTS", - [HT_EVENT_HW_SYNCHFLOOD] = "HT_EVENT_HW_SYNCHFLOOD", - [HT_EVENT_HW_HTCRC] = "HT_EVENT_HW_HTCRC" + [(HT_EVENT_COH_EVENTS & 0xfff)] = "HT_EVENT_COH_EVENTS", + [(HT_EVENT_COH_NO_TOPOLOGY & 0xfff)] = "HT_EVENT_COH_NO_TOPOLOGY", + [(HT_EVENT_COH_LINK_EXCEED & 0xfff)] = "HT_EVENT_COH_LINK_EXCEED", + [(HT_EVENT_COH_FAMILY_FEUD & 0xfff)] = "HT_EVENT_COH_FAMILY_FEUD", + [(HT_EVENT_COH_NODE_DISCOVERED & 0xfff)] = "HT_EVENT_COH_NODE_DISCOVERED", + [(HT_EVENT_COH_MPCAP_MISMATCH & 0xfff)] = "HT_EVENT_COH_MPCAP_MISMATCH", + [(HT_EVENT_NCOH_EVENTS & 0xfff)] = "HT_EVENT_NCOH_EVENTS", + [(HT_EVENT_NCOH_BUID_EXCEED & 0xfff)] = "HT_EVENT_NCOH_BUID_EXCEED", + [(HT_EVENT_NCOH_LINK_EXCEED & 0xfff)] = "HT_EVENT_NCOH_LINK_EXCEED", + [(HT_EVENT_NCOH_BUS_MAX_EXCEED & 0xfff)] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", + [(HT_EVENT_NCOH_CFG_MAP_EXCEED & 0xfff)] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", + [(HT_EVENT_NCOH_DEVICE_FAILED & 0xfff)] = "HT_EVENT_NCOH_DEVICE_FAILED", + [(HT_EVENT_NCOH_AUTO_DEPTH & 0xfff)] = "HT_EVENT_NCOH_AUTO_DEPTH", + [(HT_EVENT_OPT_EVENTS & 0xfff)] = "HT_EVENT_OPT_EVENTS", + [(HT_EVENT_OPT_REQUIRED_CAP_RETRY & 0xfff)] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", + [(HT_EVENT_OPT_REQUIRED_CAP_GEN3 & 0xfff)] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", + [(HT_EVENT_HW_EVENTS & 0xfff)] = "HT_EVENT_HW_EVENTS", + [(HT_EVENT_HW_SYNCHFLOOD & 0xfff)] = "HT_EVENT_HW_SYNCHFLOOD", + [(HT_EVENT_HW_HTCRC & 0xfff)] = "HT_EVENT_HW_HTCRC" }; /** @@ -146,7 +146,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: case HT_EVENT_COH_FAMILY_FEUD: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); break; case HT_EVENT_COH_NODE_DISCOVERED: { @@ -163,11 +163,11 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_NCOH_LINK_EXCEED: case HT_EVENT_NCOH_BUS_MAX_EXCEED: case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); break; case HT_EVENT_NCOH_DEVICE_FAILED: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", evt->node, evt->link, evt->depth, evt->attemptedBUID); @@ -176,7 +176,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) } case HT_EVENT_NCOH_AUTO_DEPTH: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; printk(log_level, ": node %d link %d depth: %d", evt->node, evt->link, evt->depth); @@ -189,7 +189,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_HW_EVENTS: case HT_EVENT_HW_SYNCHFLOOD: case HT_EVENT_HW_HTCRC: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); break; default: printk(log_level, "HT_EVENT_UNKNOWN");

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coreboot-gerrit December 2015