coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

New patch to review for coreboot: arch/arm64: add DMA_COHERENT region macros to memlayout
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12584 -gerrit commit 6abde733d29ea137f8557c5a22647bbf71e7060f Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Tue Jun 16 12:18:50 2015 +0800 arch/arm64: add DMA_COHERENT region macros to memlayout BRANCH=none BUG=none TEST=build pass Change-Id: Ia997ce97ad42234ab020af7bd007d57d7191ee86 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 604ac738e33fdfbaf093989ea13162c8506b9360 Original-Change-Id: I636a1a38d0f5af97926d4446f3edb91a359cce4c Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292551 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/include/arch/memlayout.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h index 0bd0835..ac09934 100644 --- a/src/arch/arm64/include/arch/memlayout.h +++ b/src/arch/arm64/include/arch/memlayout.h @@ -22,6 +22,11 @@ REGION(ttb, addr, size, 4K) \ _ = ASSERT(size % 4K == 0, "TTB size must be divisible by 4K!"); +#define DMA_COHERENT(addr, size) \ + REGION(dma_coherent, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DMA buffer should be multiple of smallest page size (4K)!"); + /* ARM64 stacks need 16-byte alignment. */ #define STACK(addr, size) \ REGION(stack, addr, size, 16) \

1 0

New patch to review for coreboot: libpayload: get cbfs offset & size for default media from lib_sysinfo
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12583 -gerrit commit 37b7850da4d7742f3716494d57b48cce58b7f787 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Nov 19 09:10:41 2015 -0800 libpayload: get cbfs offset & size for default media from lib_sysinfo This change revives the path which was made inert by CL:308520. When media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer to a default media. Thus, get_cbfs_range does not set cbfs offset & size from lib_sysinfo. BUG=chrome-os-partner:47772 BRANCH=tot TEST=Tested on Jerry and Glados Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89 Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0 Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313205 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/libcbfs/cbfs_core.c | 43 ++++++++++++++------------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 14a2001..ddf0da5 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -107,11 +107,8 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, return 0; } - /* - * If sysinfo doesn't have offset or size, we read them from - * a master header. - */ - DEBUG("CBFS offset & size not found in sysinfo\n"); + /* read offset and size from cbfs master header */ + DEBUG("Read CBFS offset & size from master header\n"); header = cbfs_get_header(media); if (header == CBFS_HEADER_INVALID_ADDRESS) return -1; @@ -143,6 +140,11 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) struct cbfs_file file, *file_ptr; struct cbfs_media default_media; + if (get_cbfs_range(&offset, &cbfs_end, media)) { + ERROR("Failed to find cbfs range\n"); + return NULL; + } + if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { @@ -151,11 +153,6 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) } } - if (get_cbfs_range(&offset, &cbfs_end, media)) { - ERROR("Failed to find cbfs range\n"); - return NULL; - } - DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end); DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); @@ -212,26 +209,24 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz) { - struct cbfs_media default_media; - - if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return NULL; - } - } - + /* + * get file (possibly compressed) data. we pass through 'media' to + * cbfs_get_file (don't call init_default_cbfs_media) here so that + * cbfs_get_file can see whether the call is for CBFS_DEFAULT_MEDIA + * or not. Therefore, we don't (can't) unmap the file but it's caused + * by a pre-existing inherent problem with cbfs_get_file (and all + * callers are suffering from it). + */ struct cbfs_file *file = cbfs_get_file(media, name); - if (sz) - *sz = 0; - if (file == NULL) { ERROR("Could not find file '%s'.\n", name); return NULL; } + if (sz) + *sz = 0; + if (ntohl(file->type) != type) { ERROR("File '%s' is of type %x, but we requested %x.\n", name, ntohl(file->type), type); @@ -264,11 +259,9 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, if (sz) *sz = final_size; - media->unmap(media, file); return dst; err: - media->unmap(media, file); free(dst); return NULL; }

1 0

New patch to review for coreboot: pcengines/apu1: Supply _HID object for ACPI GPIO devices
by Martin Roth 01 Dec '15

01 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12582 -gerrit commit 14508d380f6a8ac673f0977cd7c6ccb2d698beeb Author: Martin Roth <martinroth(a)google.com> Date: Tue Dec 1 10:46:33 2015 -0700 pcengines/apu1: Supply _HID object for ACPI GPIO devices The _HID was present for the top level BTNS and LEDS Devices, but was missing in the individual devices. The alternative would be to supply the GPIO being used as an _ADR object, but since it looks like the driver already has another method of handling that, it isn't required. Fixes these IASL warnings: dsdt.aml 1522: Device (BTN1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1567: Device (LED1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1576: Device (LED2) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1587: Device (LED3) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/pcengines/apu1/Kconfig | 4 ---- src/mainboard/pcengines/apu1/acpi/buttons.asl | 1 + src/mainboard/pcengines/apu1/acpi/leds.asl | 3 +++ 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 0754596..2328776 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -110,8 +110,4 @@ config PINMUX_UART_D endchoice -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/acpi/buttons.asl b/src/mainboard/pcengines/apu1/acpi/buttons.asl index 17b2d9a..a2120a9 100644 --- a/src/mainboard/pcengines/apu1/acpi/buttons.asl +++ b/src/mainboard/pcengines/apu1/acpi/buttons.asl @@ -37,6 +37,7 @@ Scope (\_SB.PCI0.SBUS) Device (BTN1) { + Name (_HID, "PRP0001") Name (_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { diff --git a/src/mainboard/pcengines/apu1/acpi/leds.asl b/src/mainboard/pcengines/apu1/acpi/leds.asl index 91b4d20..1e447f1 100644 --- a/src/mainboard/pcengines/apu1/acpi/leds.asl +++ b/src/mainboard/pcengines/apu1/acpi/leds.asl @@ -35,6 +35,7 @@ Scope (\_SB.PCI0.SBUS) Device (LED1) { + Name (_HID, "PRP0001") Name (_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { @@ -51,6 +52,7 @@ Scope (\_SB.PCI0.SBUS) Device (LED2) { + Name (_HID, "PRP0001") Name (_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { @@ -63,6 +65,7 @@ Scope (\_SB.PCI0.SBUS) Device (LED3) { + Name (_HID, "PRP0001") Name (_DSD, Package () { ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () {

1 0

New patch to review for coreboot: build system: replace files on UPDATE_IMAGE
by Patrick Georgi 01 Dec '15

01 Dec '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12581 -gerrit commit 57bafa174d5984a5cd7124de1f77f1c9307c0635 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Dec 1 18:34:42 2015 +0100 build system: replace files on UPDATE_IMAGE So far the build system only added files starting with CBFS_PREFIX/ in the UPDATE_IMAGE configuration, but there are a number of files that exist in the global namespace (eg. config, revision, but also cmos_layout.bin). Now, existing files are removed if necessary. Change-Id: I977ff85fe18115c84268103be72e91ca854e62a4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 9d754ad..8209863 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -626,10 +626,9 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # Add all cbfs files to image of the form: CONFIG_CBFS_PREFIX/<filename> prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(if $(filter $(CONFIG_CBFS_PREFIX)/%,\ - $(call extract_nth,2,$(file))), \ + $(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null ; \ $(if $(call extract_nth,6,$(file)),$(cbfs-add-cmd) -a $(call extract_nth,6,$(file)) &&,\ - $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))) + $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) .PHONY: $(obj)/coreboot.pre1 $(obj)/coreboot.pre1: $$(prebuilt-files) $(CBFSTOOL)

1 0

Patch set updated for coreboot: pci_device: Fix IRQ swizzling for pci2pci bridges
by Michael Tasche 01 Dec '15

01 Dec '15

Michael Tasche (michael.tasche(a)esd.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12579 -gerrit commit d384001bdde82ef1b3398d4b27c8eb1df16e33fb Author: Michael Tasche <michael.tasche(a)esd.eu> Date: Tue Dec 1 13:54:23 2015 +0100 pci_device: Fix IRQ swizzling for pci2pci bridges On ATOM E38xx we have 4 PCIe lanes seen as one multifunction device with function 0-3. The swizzling was correct for lane 0(function 0) only. Change-Id: I669b7f5244a7f8cc23df5e9020f26510e778c64d Signed-off-by: Michael Tasche <michael.tasche(a)esd.eu> --- src/device/pci_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..3f799a8 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1340,7 +1340,7 @@ static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) child_devfn = child->path.pci.devfn; /* Swizzle the INT_PIN for any bridges not on root bus */ - swizzled_pin = (PCI_SLOT(child_devfn) + swizzled_pin) % 4; + swizzled_pin = (PCI_SLOT(child_devfn) + PCI_FUNC(parent_devfn) + swizzled_pin) % 4; printk(BIOS_SPEW, "\tWith INT_PIN swizzled to %s\n" "\tAttached to bridge device %01X:%02Xh.%02Xh\n", pin_to_str(swizzled_pin + 1), parent_bus,

1 0

Patch set updated for coreboot: mainboard/biostar/am1ml: Add support for W25Q32 flash chip
by Sergej Ivanov 01 Dec '15

01 Dec '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12580 -gerrit commit 9ea8a9216303f8c13c806ab062f28f3018cf1e80 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Tue Dec 1 18:53:54 2015 +0300 mainboard/biostar/am1ml: Add support for W25Q32 flash chip This patch adds support for W25Q32 flash chip. Without it board hangs during spi configure if this chip is used. Patch force AGESA to use generic mode for spi without chip-specific optimizations. This disables quad-spi access and other features, that AGESA enables if it detects supported chip. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/mainboard/biostar/am1ml/BiosCallOuts.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index c87f465..318d9ba 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -118,6 +118,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.SataEnable = 1; FchParams_reset->FchReset.IdeEnable = 0; + FchParams_reset->Mode = 6; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

1 0

New patch to review for coreboot: mainboard/biostar/am1ml: Add support for W25Q32 flash chip
by Sergej Ivanov 01 Dec '15

01 Dec '15

Sergej Ivanov (getinaks(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12580 -gerrit commit 0200d35c7d48944a34589de6b0adb23b43bc74e7 Author: Sergej Ivanov <getinaks(a)gmail.com> Date: Tue Dec 1 18:53:54 2015 +0300 mainboard/biostar/am1ml: Add support for W25Q32 flash chip This patch adds support for W25Q32 flash chip. Without it board hangs during spi configure if this chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks(a)gmail.com> --- src/mainboard/biostar/am1ml/BiosCallOuts.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c index c87f465..318d9ba 100644 --- a/src/mainboard/biostar/am1ml/BiosCallOuts.c +++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c @@ -118,6 +118,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); FchParams_reset->FchReset.SataEnable = 1; FchParams_reset->FchReset.IdeEnable = 0; + FchParams_reset->Mode = 6; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

1 0

Patch merged into coreboot/master: southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 1a38374535df694a1a63d1f198d9828249019390 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Oct 25 18:58:24 2015 -0500 southbridge/amd/sb700: Fix boot hang when AHCI mode disabled Existence of requested PCI device was not checked when enabling IDE mode on the SP5100. Fix incorrect PCI device ID and check for device existence before attempting setup. Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12572 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12572 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 links
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit 273384638b4f4fbe8e500025d8941bd2e54b5f8a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Sep 13 15:54:32 2015 -0500 cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 links Decision Feedback Equalization (DFE) is a form of dynamic link training used to lower the overall error rate within the coherent fabric. Enable it on all capable HT links. Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12072 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See https://review.coreboot.org/12072 for details. -gerrit

1 0

Patch merged into coreboot/master: cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup
by gerrit＠coreboot.org 01 Dec '15

01 Dec '15

the following patch was just integrated into master: commit f8549e88e243721ac1b26373a774612b66ac8ef2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 22:26:55 2015 -0500 cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup The existing code did not properly detect various link attributes on Family 10h/15h processors. With the addition of new HT3- and IOMMU-specific code, proper detection has become critical to avoid system deadlocks. Fix and streamline link attribute detection. Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12071 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2015