Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12612
-gerrit
commit 6a33e8e2c45506a29aa2e71868bd529dd28df5ed Author: Itamar itamar.gold@mediatek.com Date: Fri Jul 31 17:10:46 2015 +0800
google/oak: Add support for verstage
Add support for vertage and add watchdog driver for hard reset.
BRANCH=none BUG=none TEST=build pass and can boot to kernel with vboot2 enabled
Change-Id: I578a69a1e43aad8c90c3914efd09d556920f728e Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656 Original-Signed-off-by: Yidi Lin yidi.lin@mediatek.com Original-Reviewed-on: https://chromium-review.googlesource.com/292662 Original-Reviewed-by: Julius Werner jwerner@chromium.org --- src/arch/arm64/Makefile.inc | 2 + src/mainboard/google/oak/Kconfig | 14 +++++++ src/mainboard/google/oak/Makefile.inc | 3 ++ src/soc/mediatek/mt8173/Kconfig | 1 + src/soc/mediatek/mt8173/Makefile.inc | 12 ++++++ src/soc/mediatek/mt8173/bootblock.c | 4 ++ src/soc/mediatek/mt8173/include/soc/wdt.h | 58 ++++++++++++++++++++++++++ src/soc/mediatek/mt8173/wdt.c | 68 +++++++++++++++++++++++++++++++ 8 files changed, 162 insertions(+)
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 1cbc9a4..b527f3a 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -76,6 +76,8 @@ verstage-y += ../../lib/memset.c verstage-y += ../../lib/memcpy.c verstage-y += ../../lib/memmove.c
+verstage-y += transition.c transition_asm.S + endif # CONFIG_ARCH_VERSTAGE_ARM64
################################################################################ diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index e45fb4c..640fe24 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -29,7 +29,9 @@ config BOARD_SPECIFIC_OPTIONS select EC_SOFTWARE_SYNC select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS select VIRTUAL_DEV_SWITCH + select VBOOT2_MOCK_SECDATA
config MAINBOARD_DIR string @@ -47,4 +49,16 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0
+config DRIVER_TPM_I2C_BUS + hex + default 0x2 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x3 + endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc index dca67db..dd6abf0 100644 --- a/src/mainboard/google/oak/Makefile.inc +++ b/src/mainboard/google/oak/Makefile.inc @@ -22,6 +22,9 @@ bootblock-y += memlayout.ld bootblock-y += chromeos.c bootblock-y += boardid.c
+verstage-y += chromeos.c +verstage-y += memlayout.ld + romstage-y += chromeos.c romstage-y += romstage.c romstage-y += memlayout.ld diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 6f23eba..f781aef 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8173 select GENERIC_UDELAY select HAS_PRECBMEM_TIMESTAMP_REGION select GENERIC_GPIO_LIB + select HAVE_HARD_RESET
if SOC_MEDIATEK_MT8173
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 563caf4..53dc9ff 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -30,6 +30,17 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif
bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c +bootblock-y += wdt.c + +################################################################################ + +verstage-y += spi.c + +verstage-$(CONFIG_DRIVERS_UART) += uart.c + +verstage-y += timer.c +verstage-y += wdt.c +verstage-y += cbfs.c
################################################################################
@@ -50,6 +61,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += gpio.c +ramstage-y += wdt.c
################################################################################
diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index ef09cae..b284dd0 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -20,6 +20,7 @@ #include <bootblock_common.h> #include <soc/mt6391.h> #include <soc/pll.h> +#include <soc/wdt.h>
void bootblock_soc_init(void) { @@ -30,4 +31,7 @@ void bootblock_soc_init(void)
/* post init pll */ mt_pll_post_init(); + + /* init watch dog, will disable AP watch dog */ + mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/wdt.h b/src/soc/mediatek/mt8173/include/soc/wdt.h new file mode 100644 index 0000000..b7b7ba4 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/wdt.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOC_MEDIATEK_MT8173_WDT_H +#define SOC_MEDIATEK_MT8173_WDT_H + +#include <stdint.h> + +struct mt8173_wdt_regs { + u32 wdt_mode; + u32 wdt_length; + u32 wdt_restart; + u32 wdt_status; + u32 wdt_interval; + u32 wdt_swrst; + u32 wdt_swsysrst; + u32 reserved[9]; + u32 wdt_debug_ctrl; +}; + +/* WDT_MODE */ +enum { + MTK_WDT_MODE_KEY = 0x22000000, + MTK_WDT_MODE_DUAL_MODE = 1 << 6, + MTK_WDT_MODE_IRQ = 1 << 3, + MTK_WDT_MODE_EXTEN = 1 << 2, + MTK_WDT_MODE_EXT_POL = 1 << 1, + MTK_WDT_MODE_ENABLE = 1 << 0 +}; + +/* WDT_RESET */ +enum { + MTK_WDT_SWRST_KEY = 0x1209, + MTK_WDT_STA_SPM_RST = 1 << 1, + MTK_WDT_STA_SW_RST = 1 << 30, + MTK_WDT_STA_HW_RST = 1 << 31 +}; + +int mtk_wdt_init(void); + +#endif /* SOC_MEDIATEK_MT8173_WDT_H */ + diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c new file mode 100644 index 0000000..2d725b1 --- /dev/null +++ b/src/soc/mediatek/mt8173/wdt.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <reset.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE; + +int mtk_wdt_init(void) +{ + uint32_t wdt_sta; + + /* Write Mode register will clear status register */ + wdt_sta = read32(&mt8173_wdt->wdt_status); + + printk(BIOS_INFO, "WDT: Last reset was "); + if (wdt_sta & MTK_WDT_STA_HW_RST) + printk(BIOS_INFO, "hardware watchdog\n"); + else if (wdt_sta & MTK_WDT_STA_SW_RST) + printk(BIOS_INFO, "normal software reboot\n"); + else if (wdt_sta & MTK_WDT_STA_SPM_RST) + printk(BIOS_INFO, "SPM reboot\n"); + else if (!wdt_sta) + printk(BIOS_INFO, "cold boot\n"); + else + printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta); + + /* Config watchdog reboot mode: + * Clearing bits: + * DUAL_MODE & IRQ: trigger reset instead of irq then reset. + * EXT_POL: select watchdog output signal as active low. + * ENABLE: disable watchdog on initialization. + * Setting bit EXTEN to enable watchdog output. + */ + clrsetbits_le32(&mt8173_wdt->wdt_mode, + MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | + MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, + MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + + return wdt_sta; +} + +void hard_reset(void) +{ + write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + while (1) + ; +}