coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: northbridge/amd/amdmct: Fix hang on boot due to invalid array access
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit e36fb7434c173e0d2f016a4e3e7af3ced5973726 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 12 19:43:06 2015 -0500 northbridge/amd/amdmct: Fix hang on boot due to invalid array access Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11989 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11989 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdfam10: Add ability to set maximum P-state limit
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 010d62311ec4be4a61dc9ee394da39d908f1f7a8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 00:35:05 2015 -0500 northbridge/amd/amdfam10: Add ability to set maximum P-state limit Under specific circumstances, for instance in low power or fanless machines, it may be useful to cap the maximum P-state of the CPU. Allow the maximum CPU P-state to be set via an NVRAM option. Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11985 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11985 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Add chromeos.c to verstage
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit b87f2a55a2601859566eefb0a76c82982e31fed0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 6 08:16:31 2015 -0800 google/chell: Add chromeos.c to verstage When enabling CONFIG_SEPARATE_VERSTAGE the functions in chromeos.c need to be put into verstage. BUG=chrome-os-partner:46289 BRANCH=none TEST=enable SEPARATE_VERSTAGE and build for chell Change-Id: Ic58a6e383806a7a64b9af760e194fddf15c645f1 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 403f0707074802371237beecf1941034c1612f10 Original-Change-Id: Ib1154869974337b53a64efa5892a83ecd81973b8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/310928 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12393 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12393 for details. -gerrit

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Patch merged into coreboot/master: google/veyron_emile: Add new board of veyron
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit e4d438e8dcf691e8ef65f32415e9176b11c85fa2 Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Thu Oct 22 10:33:13 2015 +0800 google/veyron_emile: Add new board of veyron This is a copy of mickey and renamed. CQ-DEPEND=CL:306967 BUG=chrome-os-partner:46658 TEST=build coreboot BRANCH=veyron Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325 Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307620 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/12394 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12394 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: Enable wake from touch pad.
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 278f20e88d565a0de5bd4beefc2a3dcfd209a89b Author: Archana Patni <archana.patni(a)intel.com> Date: Thu Nov 5 18:38:03 2015 +0530 intel/kunimitsu: Enable wake from touch pad. This patch enables GPP_B5 as ACPI_SCI for wake. It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW. BUG=chrome-os-partner:43491 BRANCH=none TEST=Build for kunimitsu. Tested wake from touchpad on a reworked kunimitsu board. Change-Id: I4347be8f7a4552c6b583f0797fab64045aa9792e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8c21f3b5df21d96937975dc20ee5e2f83fb3d75e Original-Change-Id: I76e69bdba81ec22ae67c7cff3a807cea8c54a5b3 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311007 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12395 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12395 for details. -gerrit

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Patch merged into coreboot/master: google/veyron_emile: adjust to the spec of emile
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 0dc117aa5d0375f0ef94824ceab399c8fe94b136 Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Thu Oct 22 10:45:23 2015 +0800 google/veyron_emile: adjust to the spec of emile o. Make some gpio changes base on Emile spec. o. Init sdmmc function. o. Revert cpu freq reducing in recovery mode since Emile have more effective thermal than Mickey. o. Revert the changes of lpddr3-samsung-2GB config. BUG=chrome-os-partner:46658 TEST=build and boot on Emile BRANCH=veyron Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999 Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307651 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/12396 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12396 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Disable Deep S3
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit c1f864e2572c7815cdb847af31b5005a4daf0f2e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 6 07:38:04 2015 -0800 google/chell: Disable Deep S3 In order to wake from trackpad and wifi we cannot enable Deep S3. BUG=chrome-os-partner:46289 BRANCH=none TEST=wake from trackpad on chell Change-Id: Ieb2210d5d15b5f5d744a686c743df11e5d72558f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cbc74e13b754249869144df84ab2bb9b7e77119a Original-Change-Id: I84265197fb964e0594a4672a40fd3e2362e29ae1 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311306 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12392 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Add SPD for new memory type
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit a85f3ae852fcca022fe409fb96bd293ab7a8b9f9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 5 17:08:25 2015 -0800 google/chell: Add SPD for new memory type This adds the SPD for SK-Hynix H9CCNNNCLTMLAR memory to be used in the EVT build. BUG=chrome-os-partner:47346 BRANCH=none TEST=emerge-chell coreboot Change-Id: I45d0840e43ed81d8286b005f0a99b014b7f0cf28 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 1e917440141c586cb370147f9c5b782d6e77ea10 Original-Change-Id: I02f1349f38d83f4a09887adf81384b5a8f475dd0 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311214 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12391 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12391 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: mainboards: Add MAINBOARD_FAMILY kconfig entry
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 0ca1b2f5475ac1efb3e95d560ba4a6dee415787c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 5 16:54:04 2015 -0800 intel/skylake: mainboards: Add MAINBOARD_FAMILY kconfig entry The family variable was not being set yet for skylake, add this to the current boards. BUG=chromium:551715 BRANCH=none TEST=emerge-glados coreboot Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311213 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12390 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12390 for details. -gerrit

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Patch merged into coreboot/master: google/chell: Fix USB port assignment again
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit b13845191ff96dea4e88c220167fa7f3c1576d69 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 5 07:12:33 2015 -0800 google/chell: Fix USB port assignment again The net names are offset by 1. My board is not stable enough to really test all of these yet... BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311113 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12389 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12389 for details. -gerrit

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coreboot-gerrit November 2015