coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: southbridge/amd/sb700: Recover if AHCI disk detection fails
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11999 -gerrit commit b16f0c9f1a985809b916e9b6a015102d0047a0ae Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 22 02:21:29 2015 -0500 southbridge/amd/sb700: Recover if AHCI disk detection fails Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 83 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 75 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 63c07d8..a59708f 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -27,12 +27,15 @@ static int sata_drive_detect(int portnum, uint16_t iobar) { u8 byte, byte2; + u8 byte_prev, byte2_prev; int i = 0; + byte_prev = byte2_prev = 0; outb(0xa0 + 0x10 * (portnum % 2), iobar + 0x6); while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), (byte != (0xa0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { - printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); + if ((byte != byte_prev) || (byte2 != byte2_prev)) + printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); if (byte != (0xa0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the @@ -41,11 +44,22 @@ static int sata_drive_detect(int portnum, uint16_t iobar) printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); return 1; - } else - printk(BIOS_SPEW, "drive detection not yet completed, " - "waiting...\n"); + } else { + if (i == 0) + printk(BIOS_SPEW, "drive detection not yet completed, " + "waiting...\n"); + } mdelay(10); i++; + byte_prev = byte; + byte2_prev = byte2; + + /* Detect stuck SATA controller and attempt reset */ + if (i > 1024) { + printk(BIOS_DEBUG, "drive detection not done after %i ms, " + "resetting HBA and retrying init\n", i * 10); + return 2; + } } printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); return 0; @@ -101,12 +115,13 @@ static void sata_init(struct device *dev) uint16_t sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; uint16_t ide_bar0, ide_bar1, ide_bar2, ide_bar3; uint16_t current_bar; - int i, j; + int i, j, ret; uint8_t nvram; uint8_t sata_ahci_mode; uint8_t sata_alpm_enable; uint8_t port_count; uint8_t max_port_count; + uint8_t hba_reset_count; sata_ahci_mode = 0; if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) @@ -120,14 +135,23 @@ static void sata_init(struct device *dev) /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + hba_reset_count = 0; + +retry_init: byte = pci_read_config8(sm_dev, 0xad); /* Disable SATA SMBUS */ - byte |= (1 << 0); - /* Enable SATA and power saving */ byte |= (1 << 1); + /* Enable SATA and power saving */ + byte |= (1 << 0); byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte); + /* Take the PHY logic out of reset */ + word = pci_read_config16(dev, 0x84); + word |= 0x1 << 2; + word &= ~0x1f8; + pci_write_config16(dev, 0x84, word); + /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; @@ -320,6 +344,26 @@ static void sata_init(struct device *dev) if (port_count > max_port_count) port_count = max_port_count; + /* Send COMRESET to all ports */ + for (i = 0; i < port_count; i++) { + /* Read in Port-N Serial ATA Control Register */ + byte = read8(sata_bar5 + 0x12C + 0x80 * i); + + /* Set Reset Bit */ + byte |= 0x1; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + + /* Clear Reset Bit */ + byte &= ~0x01; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + } + /* RPR7.7 SATA drive detection. */ /* Use BAR5+0x128,BAR0 for Primary Slave */ /* Use BAR5+0x1A8,BAR0 for Primary Slave */ @@ -365,8 +409,31 @@ static void sata_init(struct device *dev) current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; else current_bar = ide_bar0; - if (!sata_drive_detect(i, current_bar)) + ret = sata_drive_detect(i, current_bar); + if (ret == 0) { break; + } else if (ret == 2) { + /* Reset PHY logic */ + word = pci_read_config16(dev, 0x84); + word &= ~(0x1 << 2); + word |= 0x1f8; + pci_write_config16(dev, 0x84, word); + + /* Disable SATA controller */ + byte = pci_read_config8(sm_dev, 0xad); + byte &= ~(0x1); + pci_write_config8(sm_dev, 0xad, byte); + + mdelay(100); + + /* Retry initialization */ + hba_reset_count++; + if (hba_reset_count < 16) + goto retry_init; + else + printk(BIOS_WARNING, "HBA reset count exceeded, " + "continuing but AHCI drives may not function\n"); + } } if (sata_ahci_mode) printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n",

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Patch set updated for coreboot: src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startup
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11998 -gerrit commit 96100622ae5789ec431743056b400b389703b068 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Jun 21 16:27:03 2015 -0500 src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startup In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts), with the probability of a failure increasing with the number of disks connected to the controller. Resetting the SATA controller appears to show the true state of the underlying hardware, allowing the drive detection code to attempt link renegotiation as needed. Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 47 ++++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index ae44446..63c07d8 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -131,6 +131,8 @@ static void sata_init(struct device *dev) /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; + printk(BIOS_SPEW, "rev_id=%x\n", rev_id); + if (sata_ahci_mode) { /* Enable link latency enhancement on A14 and above */ if (rev_id >= 0x14) { @@ -241,6 +243,27 @@ static void sata_init(struct device *dev) write32(sata_bar5 + 0xfc, dword); } + if (sata_ahci_mode) { + /* FIXME + * SeaBIOS does not know how to spin + * up the drives and therefore hangs + * in AHCI init if this is enabled... + */ + /* Enable staggered spin-up */ + dword = read32(sata_bar5 + 0x00); +#if 0 + dword |= 0x1 << 27; +#else + dword &= ~(0x1 << 27); +#endif + write32(sata_bar5 + 0x00, dword); + + /* Reset the HBA to avoid stuck drives in SeaBIOS */ + dword = read32(sata_bar5 + 0x04); + dword |= 0x1; + write32(sata_bar5 + 0x04, dword); + } + /* Write protect Sub-Class Code */ byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0); @@ -367,21 +390,21 @@ static void sata_init(struct device *dev) } /* Below is CIM InitSataLateFar */ - /* Enable interrupts from the HBA */ - byte = read8(sata_bar5 + 0x4); - byte |= 1 << 1; - write8((sata_bar5 + 0x4), byte); - if (!sata_ahci_mode) { - /* Clear error status */ - write32((sata_bar5 + 0x130), 0xFFFFFFFF); - write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x230), 0xFFFFFFFF); - write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); - write32((sata_bar5 + 0x330), 0xFFFFFFFF); - write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); + /* Enable interrupts from the HBA */ + byte = read8(sata_bar5 + 0x4); + byte |= 1 << 1; + write8((sata_bar5 + 0x4), byte); } + /* Clear error status */ + write32((sata_bar5 + 0x130), 0xFFFFFFFF); + write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x230), 0xFFFFFFFF); + write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x330), 0xFFFFFFFF); + write32((sata_bar5 + 0x3b0), 0xFFFFFFFF); + /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */

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Patch set updated for coreboot: southbridge/amd/sb700: Add option to disable SATA ALPM
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11993 -gerrit commit 4e6e8df6134e903737f3c0a8c6efb85ec85b619f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 18 11:48:02 2015 -0500 southbridge/amd/sb700: Add option to disable SATA ALPM The AMD Register Programming Reference states that the user should have the option to disable Active Link Power Management for two reasons. First, some drives may not function correctly with the ALPM implementation of the SP5100, and second there are some situations where low latency access is more important than the power savings created by using ALPM. Allow the user to disable ALPM if desired. Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index fdf32c7..c61fa01 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -104,6 +104,7 @@ static void sata_init(struct device *dev) int i, j; uint8_t nvram; uint8_t sata_ahci_mode; + uint8_t sata_alpm_enable; uint8_t port_count; uint8_t max_port_count; @@ -111,6 +112,10 @@ static void sata_init(struct device *dev) if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) sata_ahci_mode = !!nvram; + sata_alpm_enable = 0; + if (get_option(&nvram, "sata_alpm") == CB_SUCCESS) + sata_alpm_enable = !!nvram; + device_t sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -229,6 +234,13 @@ static void sata_init(struct device *dev) dword &= ~(0x1 << i); write32(sata_bar5 + 0x0c, dword); + /* Disable ALPM if ALPM support not requested */ + if (!sata_alpm_enable) { + dword = read32(sata_bar5 + 0xfc); + dword &= ~(0x1 << 11); /* Disable ALPM */ + write32(sata_bar5 + 0xfc, dword); + } + /* Write protect Sub-Class Code */ byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0);

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11988 -gerrit commit d44ff212616af0337efc03aa2fa6a533e4f30bf9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 12 13:32:52 2015 -0500 mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 74 +++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 63d85e8..8445eb3 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -292,13 +292,29 @@ DefinitionBlock ( Name (PR03, Package () { /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 44 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 45 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 46 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 47 }, + }) + + Name (PR04, Package () { + /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR03, Package () { + Name (AR04, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 48 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 49 }, @@ -306,7 +322,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 51 }, }) - Name (PR04, Package () { + Name (PR05, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 }, @@ -314,7 +330,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 }, }) - Name (AR04, Package () { + Name (AR05, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 47 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 44 }, @@ -322,7 +338,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 46 }, }) - Name (PR05, Package () { + Name (PR06, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, @@ -330,7 +346,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR05, Package () { + Name (AR06, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 32 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 33 }, @@ -338,7 +354,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 35 }, }) - Name (PR06, Package () { + Name (PR07, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, @@ -346,7 +362,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, }) - Name (AR06, Package () { + Name (AR07, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 36 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 37 }, @@ -354,7 +370,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 39 }, }) - Name (PR07, Package () { + Name (PR08, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, @@ -362,7 +378,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR07, Package () { + Name (AR08, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 40 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 41 }, @@ -613,6 +629,26 @@ DefinitionBlock ( } } + /* 1:00.0 PIKE */ + Device (PIKE) + { + Name (_ADR, 0x00040000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + /* 3:00.0 PCIe NIC A */ Device (NICA) { @@ -621,9 +657,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR03) + Return (AR04) } Else { - Return (PR03) + Return (PR04) } } Device (BDC1) @@ -640,9 +676,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR04) + Return (AR05) } Else { - Return (PR04) + Return (PR05) } } Device (BDC2) @@ -659,9 +695,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR05) + Return (AR06) } Else { - Return (PR05) + Return (PR06) } } Device (SLT1) @@ -679,9 +715,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR06) + Return (AR07) } Else { - Return (PR06) + Return (PR07) } } Device (SLT1) @@ -699,9 +735,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR07) + Return (AR08) } Else { - Return (PR07) + Return (PR08) } } Device (SLT1)

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS option
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12407 -gerrit commit 3704086b2599a825834786d127aac3ca90a44024 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 13:38:06 2015 -0600 mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS option Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index dc698d0..0b87c91 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable sata_ahci_mode = Enable +maximum_p_state_limit = 0xf ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index dfd5159..19c7e7d 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -41,7 +41,8 @@ entries 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode -468 1 r 0 allow_spd_nvram_cache_restore +468 4 h 0 maximum_p_state_limit +473 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum

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Patch set updated for coreboot: src/northbridge/amd/amdmct: Add option to override bad SPD checksum
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11987 -gerrit commit d3bd0baf96b061a7c8617d1639192845365740ad Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 11 16:14:15 2015 -0500 src/northbridge/amd/amdmct: Add option to override bad SPD checksum Certain DIMMs, for example DIMMs on which the EEPROM has been modified by the end user, may not contain a valid SPD checksum. While this is not a normal condition, it may be useful to allow a checksum override while memory timing parameters are being altered, e.g. in the course of overclocking or underclocking, or when recovering from a bad SPD write. This is an advanced level feature primarily useful for debugging and development. Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 +++-- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2841b18..4bfb08a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1456,7 +1456,7 @@ restartinit: } } if (NodesWmem == 0) { - printk(BIOS_DEBUG, "No Nodes?!\n"); + printk(BIOS_ALERT, "Unable to detect valid memory on any nodes. Halting!\n"); goto fatalexit; } @@ -3892,13 +3892,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, read_spd_bytes(pMCTstat, pDCTstat, i); crc_status = crcCheck(pDCTstat, i); } - if (crc_status) { /* CRC is OK */ + if ((crc_status) || (SPDCtrl == 2)) { /* CRC is OK */ byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ pDCTstat->DIMMValid |= 1 << i; } } else { + printk(BIOS_WARNING, "Node %d DIMM %d: SPD checksum invalid\n", pDCTstat->Node_ID, i); pDCTstat->DIMMSPDCSE = 1 << i; if (SPDCtrl == 0) { pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 45f8177..f49e973 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -146,6 +146,14 @@ static u16 mctGet_NVbits(u8 index) case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */ + //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */ + + if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) + val = nvram & 0x3; + + if (val > 2) + val = 2; + break; case NV_DQSTrainCTL: //val = 0; /*Skip dqs training */

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Patch set updated for coreboot: northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11986 -gerrit commit 61e0adf99431bbce9e2441fcaa54fef069fd6a10 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 10:46:17 2015 -0500 northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2d8ab34..2841b18 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -4134,7 +4134,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); - if (load_spd_hashes_from_nvram(pDCTstat) < 0) { + if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; } else { @@ -4149,6 +4149,13 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) + allow_config_restore = 0; +#else + allow_config_restore = 0; +#endif + if (!allow_config_restore) pDCTstat->spd_data.nvram_spd_match = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 196d96d..425f1ef 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -297,6 +297,7 @@ struct MCTStatStruc { u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ uint32_t TSCFreq; + uint16_t nvram_checksum; } __attribute__((packed)); /*============================================================================= @@ -792,6 +793,7 @@ struct amd_s3_persistent_node_data { struct amd_s3_persistent_data { struct amd_s3_persistent_node_data node[MAX_NODES_SUPPORTED]; + uint16_t nvram_checksum; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 0a508cb..6e92f3a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -139,6 +139,36 @@ void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) *spd_hash = *spd_hash ^ (*spd_hash << 37); } +uint16_t calculate_nvram_mct_hash(void) +{ + uint32_t nvram; + uint16_t ret; + + ret = 0; + if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) + ret |= nvram & 0xf; + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) + ret |= (nvram & 0x3) << 4; + if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) + ret |= (nvram & 0x1) << 6; + if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) + ret |= (nvram & 0x1) << 7; + if (get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) + ret |= (nvram & 0x1) << 8; + if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) + ret |= (nvram & 0x1) << 9; + if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) + ret |= (nvram & 0x1) << 10; + if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) + ret |= (nvram & 0x1) << 11; + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + ret |= (nvram & 0x1) << 12; + if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) + ret |= (nvram & 0x1) << 13; + + return ret; +} + static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) { ssize_t s3nv_offset; @@ -169,7 +199,7 @@ static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) } #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { struct amd_s3_persistent_data *persistent_data; @@ -180,6 +210,8 @@ int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); + pMCTstat->nvram_checksum = persistent_data->nvram_checksum; + return 0; } #endif @@ -233,6 +265,8 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + persistent_data->nvram_checksum = calculate_nvram_mct_hash(); + if (restored) { if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) *restored = 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 56e627e..8a72695 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -17,9 +17,10 @@ #include "mct_d.h" void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); +uint16_t calculate_nvram_mct_hash(void); #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat); +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); #endif #ifdef __RAMSTAGE__

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Patch merged into coreboot/master: Makefile.inc: Build test intelvbttool
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 28a45d4c1b9fb9d471612f66dd551e6dccc8d04e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Oct 18 11:47:45 2015 +0200 Makefile.inc: Build test intelvbttool Add intelvbttool to list of utilities to be build tested by the build servers. Change-Id: Id75724726778fd939fb7497f5b33a3d5d58124fd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/12085 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12085 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct: Fix crash on startup due to NULL pointer access
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 9b5480dd5e6b2f84b4c05e9ce91a35cee4f9cc64 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 14:40:56 2015 -0500 northbridge/amd/amdmct: Fix crash on startup due to NULL pointer access Change-Id: I47089f2ad886a6fda4e0cd4472efd975bb8e06c5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11995 Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11995 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Set SP5100 subtype
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit fe2ae6190680db7999ba41df682dcfc59aa60322 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 18 12:37:08 2015 -0500 mainboard/asus/kgpe-d16: Set SP5100 subtype Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11994 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11994 for details. -gerrit

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coreboot-gerrit November 2015