coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

New patch to review for coreboot: libpayload: queue: Add a helper macro for checking singleton queue
by Patrick Georgi 11 Nov '15

11 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12412 -gerrit commit f9260693d30f31f368738e74ad14cc9cc5c5ced4 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Nov 6 22:20:15 2015 -0800 libpayload: queue: Add a helper macro for checking singleton queue Check if the simple queue consists of only 1 element. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. Change-Id: Ib257a5e6b9042b42c549f8ad8b943e3b75fd8c9c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5435d6fec1c4fbb4c04ba5b8c15caff9ee4e50f0 Original-Change-Id: I7a8cb9c4e7e71956e85e65b3e7b8e0af4d354110 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311256 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/include/queue.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/payloads/libpayload/include/queue.h b/payloads/libpayload/include/queue.h index f8f09bf..2b64669 100644 --- a/payloads/libpayload/include/queue.h +++ b/payloads/libpayload/include/queue.h @@ -268,6 +268,9 @@ struct { \ #define SIMPLEQ_END(head) NULL #define SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head)) #define SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) +#define SIMPLEQ_TAIL_NEXT(head) ((head)->sqh_last) +#define SIMPLEQ_SINGLETON(head, field) \ + (&SIMPLEQ_NEXT(SIMPLEQ_FIRST(head), field) == SIMPLEQ_TAIL_NEXT(head)) #define SIMPLEQ_FOREACH(var, head, field) \ for((var) = SIMPLEQ_FIRST(head); \

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New patch to review for coreboot: intel/skylake: ensure the RTC time is set
by Patrick Georgi 11 Nov '15

11 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12411 -gerrit commit 0116ca31330506d8c4a3766b1798985075383587 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 6 15:24:20 2015 -0600 intel/skylake: ensure the RTC time is set In 2014 or so the RTC code was changed to assume the ALTCENTRY register (0x32) as always being utilized for creating an rtc_time. However, one needs to ensure it's set at least once otherwise the year field in rtc_time is not sane. In practice this doesn't matter unless somone wants to use the full year value. cmos_init() should do the same thing in the rtc fail case, but the machine I had never had that set correctly. BUG=chrome-os-partner:47388 BRANCH=None TEST=Booted glados w/ 0xff ALTCENTRY value. New value is 0x20. Change-Id: I028f801c5d717a0018ed00df82c25b466d64670c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d5be5bc697bef60a264ddc7f67755aa96088d36 Original-Change-Id: I6e12a30c9e08d8c1002e4cef0f143f0f88009e92 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311264 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/pmc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index fb09589..a2d88aa 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -139,6 +139,9 @@ static void pch_rtc_init(void) printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } + /* Ensure the date is set including century byte. */ + cmos_check_update_date(); + #if IS_ENABLED(CONFIG_CHROMEOS_VBNV_CMOS) pch_cmos_init_preserve(rtc_failed); #else

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New patch to review for coreboot: elog: fix improper assumption for year values
by Patrick Georgi 11 Nov '15

11 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12410 -gerrit commit c7e0e559fc94cfa7d62c5ddcee6e95bb5408e10e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 6 15:20:23 2015 -0600 elog: fix improper assumption for year values The elog format stores the year of the event in bcd format. Semi-recently rtc_get() started returning the full year, e.g. 2015. However, bin2bcd takes a uint8_t as a parameter. Converting a full year (2015 or 0x7df) to a uint8_t results in passing bad values (223 or 0xdf) to bin2bcd. In other words the input value of bin2bcd needs to be a number between 0 and 99. Therefore fix that mistake. BUG=chrome-os-partner:47388 BRANCH=None TEST=Events show up with correct year in eventlog now. Change-Id: I9209cb9175c0b4925337e2e5d4fea8316b30022a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 95a86013234dc999c988291f636e2db3803cc24a Original-Change-Id: I12734bc3a423ba9d739658b8edc402b8d445f22e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311263 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/elog/elog.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 97abf81..71eaad2 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -635,8 +635,7 @@ static void elog_fill_timestamp(struct event_header *event) event->hour = bin2bcd(time.hour); event->day = bin2bcd(time.mday); event->month = bin2bcd(time.mon); - event->year = bin2bcd(time.year) & 0xff; - + event->year = bin2bcd(time.year % 100); /* Basic sanity check of expected ranges */ if (event->month > 0x12 || event->day > 0x31 || event->hour > 0x23 ||

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS option
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit ab87c4db30acda329d010ac9e91d0bb8b9c6c1cc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 13:38:06 2015 -0600 mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS option Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12407 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12407 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Rename PDCurses-3.4 to PDCurses
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 4f85a1eb76d1e7109bcc60ba6f3262a5654ac61b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Nov 10 09:00:41 2015 -0800 libpayload: Rename PDCurses-3.4 to PDCurses Change-Id: If881ec130833c7e7e62caa3d31e350a531f5bc8e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/12398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12398 for details. -gerrit

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Patch merged into coreboot/master: PDCurses: Don't hard code version number
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 2ea24dabd658b8396e0abf79318a538ef0f3a5b8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Nov 10 08:56:37 2015 -0800 PDCurses: Don't hard code version number Don't hard code the PDCurses version number in every file added to the object list. Change-Id: Ic2e9230b7e3089c60dd7f442e3ea7baffb4aa400 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/12397 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12397 for details. -gerrit

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New patch to review for coreboot: mainboard/asus/kgpe-d16: Add sata_alpm CMOS option
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12409 -gerrit commit 8b7618c92cd7912bbb8e99c94366c40ac88ddf8f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 14:04:40 2015 -0600 mainboard/asus/kgpe-d16: Add sata_alpm CMOS option Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 3473bc9..9994dad 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -18,6 +18,7 @@ interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable sata_ahci_mode = Enable +sata_alpm = Disable maximum_p_state_limit = 0xf ieee1394_controller = Enable power_on_after_fail = On diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 0bc6db8..21765e3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -41,9 +41,10 @@ entries 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode -468 4 h 0 maximum_p_state_limit -472 2 e 13 dimm_spd_checksum -474 1 r 0 allow_spd_nvram_cache_restore +468 1 e 1 sata_alpm +469 4 h 0 maximum_p_state_limit +473 2 e 13 dimm_spd_checksum +475 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum

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New patch to review for coreboot: mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS option
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12408 -gerrit commit fa5642a04a201bda46bc2eecd8a6d36718651f71 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 14:07:10 2015 -0600 mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS option Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 0b87c91..3473bc9 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -8,6 +8,7 @@ nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 minimum_memory_voltage = 1.5V +dimm_spd_checksum = Enforce ECC_memory = Enable ECC_redirection = Enable ecc_scrub_rate = 1.28us diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 19c7e7d..0bc6db8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -42,7 +42,8 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 4 h 0 maximum_p_state_limit -473 1 r 0 allow_spd_nvram_cache_restore +472 2 e 13 dimm_spd_checksum +474 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum @@ -137,6 +138,9 @@ enumerations 12 1 1.35V 12 2 1.25V 12 3 1.15V +13 0 Enforce +13 1 Ignore +13 2 Override checksums

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Patch set updated for coreboot: southbridge/amd/sb700: Do drive detection even in AHCI mode
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11997 -gerrit commit c172111860ad27588e040d51af0db3d1f93cf0b4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 21:31:15 2015 -0500 southbridge/amd/sb700: Do drive detection even in AHCI mode SeaBIOS AHCI drive detection randomly fails for drives present on the secondary channel of each AHCI SATA BAR. Forcing native drive detection in AHCI mode resolves this issue. Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 99 +++++++++++++++++++++------------------- 1 file changed, 53 insertions(+), 46 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index c61fa01..ae44446 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -297,65 +297,72 @@ static void sata_init(struct device *dev) if (port_count > max_port_count) port_count = max_port_count; - if (!sata_ahci_mode) { - /* RPR7.7 SATA drive detection. */ - /* Use BAR5+0x128,BAR0 for Primary Slave */ - /* Use BAR5+0x1A8,BAR0 for Primary Slave */ - /* Use BAR5+0x228,BAR2 for Secondary Master */ - /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ - /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ - /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ - for (i = 0; i < port_count; i++) { + /* RPR7.7 SATA drive detection. */ + /* Use BAR5+0x128,BAR0 for Primary Slave */ + /* Use BAR5+0x1A8,BAR0 for Primary Slave */ + /* Use BAR5+0x228,BAR2 for Secondary Master */ + /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ + /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ + /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ + for (i = 0; i < port_count; i++) { + byte = read8(sata_bar5 + 0x128 + 0x80 * i); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); + byte &= 0xF; + if (byte == 0x1) { + /* If the drive status is 0x1 then we see it but we aren't talking to it. */ + /* Try to do something about it. */ + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); + + /* Read in Port-N Serial ATA Control Register */ + byte = read8(sata_bar5 + 0x12C + 0x80 * i); + + /* Set Reset Bit and 1.5g bit */ + byte |= 0x11; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + + /* Clear Reset Bit */ + byte &= ~0x01; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + + /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; - if (byte == 0x1) { - /* If the drive status is 0x1 then we see it but we aren't talking to it. */ - /* Try to do something about it. */ - printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); - - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); - - /* Set Reset Bit and 1.5g bit */ - byte |= 0x11; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); + } - /* Reread status */ - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; + if (byte == 0x3) { + for (j = 0; j < 10; j++) { + if (i < 4) + current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; + else + current_bar = ide_bar0; + if (!sata_drive_detect(i, current_bar)) + break; } - - if (byte == 0x3) { - for (j = 0; j < 10; j++) { - if (i < 4) - current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; - else - current_bar = ide_bar0; - if (!sata_drive_detect(i, current_bar)) - break; - } + if (sata_ahci_mode) + printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n", + i, + (j == 10) ? "not " : "", + (j == 10) ? j : j + 1); + else printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); - } else { + } else { + if (sata_ahci_mode) + printk(BIOS_DEBUG, "No AHCI SATA drive on Slot%i\n", i); + else printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); - } } }

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Patch set updated for coreboot: northbridge/amd/amdmct: Clear memory before enabling ECC
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11996 -gerrit commit 6d558d7c4a2849755aec1cbe1b5511583e0156cc Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 20:02:49 2015 -0500 northbridge/amd/amdmct: Clear memory before enabling ECC Change-Id: I992e7040520570893ba6a213138dd57bfa14733b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 45 ++++++++------------------ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 38 +++++++++++++++++++++- 2 files changed, 51 insertions(+), 32 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4bfb08a..b3f43fb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -47,8 +47,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); static u8 NodePresent_D(u8 Node); static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -1507,10 +1505,11 @@ restartinit: InterleaveChannels_D(pMCTstat, pDCTstatA); printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n"); - if (ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat,pDCTstatA); - } + ECCInit_D(pMCTstat, pDCTstatA); /* Setup ECC control and ECC check-bits*/ + + /* mctDoWarmResetMemClr_D(); */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); + MCTMemClr_D(pMCTstat,pDCTstatA); printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -2102,9 +2101,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ mctHookAfterAnyTraining(); - - /* mctDoWarmResetMemClr_D(); */ - MCTMemClr_D(pMCTstat, pDCTstatA); } static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, @@ -2392,26 +2388,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, } } -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Ensures that memory clear has completed on all node.*/ - u8 Node; - struct DCTStatStruc *pDCTstat; - - if (!mctGet_NVbits(NV_DQSTrainCTL)){ - /* callback to wrapper: mctDoWarmResetMemClr_D */ - } else { /* NV_DQSTrainCTL == 1 */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - } - } -} - static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -2432,9 +2408,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } while (!(val & (1 << Dr_MemClrStatus))); } - val = 0x0FE40FC0; /* BKDG recommended */ + if (is_fam15h()) + val = 0x0ce00f41; /* BKDG recommended */ + else + val = 0x0fe40fc0; /* BKDG recommended */ val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(dev, 0x11C, val); + Set_NB32(dev, 0x11c, val); } static u8 NodePresent_D(u8 Node) @@ -3097,6 +3076,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, u16 proposedFreq; u16 word; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + /* Get CPU Si Revision defined limit (NPT) */ if (is_fam15h()) proposedFreq = 933; @@ -3121,6 +3102,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, pDCTstat->PresetmaxFreq = word; } /* Check F3xE8[DdrMaxRate] for maximum DRAM data rate support */ + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 6ab33a3..8701bae 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,6 +84,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; + uint32_t dword; + uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; + uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; + mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -107,6 +111,25 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) nvbits = mctGet_NVbits(NV_DramBKScrub); OF_ScrubCTL |= nvbits; + /* Prevent lockups on DRAM errors during ECC init */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; + sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ + DCTMemClr_Init_D(pMCTstat, pDCTstat); + DCTMemClr_Sync_D(pMCTstat, pDCTstat); + } + } + AllECC = 1; MemClrECC = 0; for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -153,7 +176,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* Node has Dram */ if (MemClrECC) { - MCTMemClrSync_D(pMCTstat, pDCTstatA); + DCTMemClr_Sync_D(pMCTstat, pDCTstat); } if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { @@ -166,6 +189,19 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* if Node present */ } + /* Restore previous MCA error handling settings */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; + dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } + } + if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else

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coreboot-gerrit November 2015