coreboot-gerrit November 2015

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Patch merged into coreboot/master: fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbol
by gerrit＠coreboot.org 30 Nov '15

30 Nov '15

the following patch was just integrated into master: commit bd88fa0ef62339bfc3027423d230a6ffcd1419ae Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 17:46:45 2015 -0700 fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbol The symbol BAYTRAIL_SMM was never valid (there's no config statment initializing the symbol), but it was being selected and used in the code. Now that SMM is supported in fsp_baytrail, the code it was trying to switch can be removed, and just set up for SMM. Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12553 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Ben Gardner <gardner.ben(a)gmail.com> See https://review.coreboot.org/12553 for details. -gerrit

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Patch set updated for coreboot: arch/x86/bootblock_normal: Update to use fewer registers
by Martin Roth 30 Nov '15

30 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12574 -gerrit commit 7137b539d8c145d3488f87fcd4992e50673e8f6d Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 30 09:49:21 2015 -0700 arch/x86/bootblock_normal: Update to use fewer registers - Move initialization of entry to later in main. - Make boot_mode an unsigned char - no need to use int. - Remove unnecessary variable filenames. - Only get and try to boot fallback once. Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a Test: compiled. Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/arch/x86/bootblock_normal.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index d5f03b7..a6a877c 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -10,9 +10,9 @@ static const char *get_fallback(const char *stagelist) { static void main(unsigned long bist) { - unsigned long entry; - int boot_mode; - const char *default_filenames = "normal/romstage\0fallback/romstage"; + u8 boot_mode; + const char *default_filenames = + "normal/romstage\0fallback/romstage"; if (boot_cpu()) { bootblock_mainboard_init(); @@ -30,22 +30,22 @@ static void main(unsigned long bist) boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE)); } - char *filenames = (char *)walkcbfs("coreboot-stages"); - if (!filenames) { - filenames = default_filenames; - } - char *normal_candidate = filenames; + char *normal_candidate = (char *)walkcbfs("coreboot-stages"); - if (boot_mode) - entry = findstage(normal_candidate); - else - entry = findstage(get_fallback(normal_candidate)); + if (!normal_candidate) + normal_candidate = default_filenames; - if (entry) call(entry, bist); + unsigned long entry; + + if (boot_mode) { + entry = findstage(normal_candidate); + if (entry) + call(entry, bist); + } - /* run fallback if normal can't be found */ entry = findstage(get_fallback(normal_candidate)); - if (entry) call(entry, bist); + if (entry) + call(entry, bist); /* duh. we're stuck */ halt();

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Patch set updated for coreboot: device: Do not attempt to assign resources to large BARs
by Ben Frisch 30 Nov '15

30 Nov '15

Ben Frisch (bfrisch(a)xes-inc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12575 -gerrit commit 4cfb680d52d80f27f410290defa1f61bd1766afe Author: Benjamin Frisch <bfrisch(a)xes-inc.com> Date: Mon Nov 30 12:23:31 2015 -0600 device: Do not attempt to assign resources to large BARs Per the PCI Firmware Specification 3.1 and Firmware Allocation of PCI Device Resources in Windows document, firmware shall not allocate resources to devices that cannot fit in available 32-bit MMIO space. It is then assumed that 64-bit operating systems can rebalance resources as necessary (eg. adding 64-bit MMIO space in ACPI and possibly adding the pci=realloc kernel argument in in Linux). This implmentation is inspired by the error handling in the UEFI tianocore.org PCI Enumeration. If a BAR is found that cannot be satisfied, devices that are not on bus 0 are disabled and skipped in the following order to attempt to make room to satisfy the remaining BAR MMIO space requests: 1) Disabling the device with the largest 64-bit BARs (without OPROMs) 2) Disabling the device with the largest 32-bit BARs (without OPROMs) 3) Disabling the devices with the largest space request (with OPROMs) After the device is disabled, PCI enumeration is then repeated with the disabled device skipped. This process continues until PCI emeration completes successfully. TEST=Tested on internal coreboot port based on older upstream with device presenting 128 GB BAR with latest Linux kernel, additional testing help and feedback is appreciated. Change-Id: I0217d627ca77431075df5e24d49d6406c35893b7 Signed-off-by: Ben Frisch <bfrisch(a)xes-inc.com> --- src/device/Kconfig | 46 ++++++++++++++++ src/device/device.c | 124 ++++++++++++++++++++++++++++++++------------ src/device/device_util.c | 109 ++++++++++++++++++++++++++++++++++++++ src/device/pci_device.c | 64 ++++++++++++++++------- src/include/device/device.h | 4 ++ 5 files changed, 295 insertions(+), 52 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 0113545..b9a734d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -389,6 +389,52 @@ config SOFTWARE_I2C I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines. +choice SET_MAX_MEM_BAR_SIZE + prompt "Set Maximum memory BAR size to try to allocate " + optional + help + Select the maximum size PCI device memory BAR that coreboot will try + to allocate. If a BAR is found with a values above this size, coreboot + will disable the device and will not try to allocate any BARs. + + If unsure, leave this disabled, and coreboot will find and disable any + devices that are too large to be allocated by itself. The + disadvantage is a slight boot time increase if a device has to be + disabled. + +config MAX_BAR_SIZE_256MB + bool "256 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 256 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_512MB + bool "512 MB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 512 MB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +config MAX_BAR_SIZE_1GB + bool "1 GB" + help + Set the maximum size PCI device memory BAR that coreboot will try to + allocate to 1 GB. If a BAR is found with a values above this size, + coreboot will disable the device and will not try to allocate any + BARs. + +endchoice + +config MAX_MEM_BAR_SIZE_TO_ALLOCATE + hex + default 0x10000000 if MAX_BAR_SIZE_256MB + default 0x20000000 if MAX_BAR_SIZE_512MB + default 0x40000000 if MAX_BAR_SIZE_1GB + default 0 + endmenu menu "Display" diff --git a/src/device/device.c b/src/device/device.c index e23c9de..dc39dfc 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -690,7 +690,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) } } -static void avoid_fixed_resources(struct device *dev) +static u8 avoid_fixed_resources(struct device *dev) { struct constraints limits; struct resource *res; @@ -743,9 +743,60 @@ static void avoid_fixed_resources(struct device *dev) if (res->flags & IORESOURCE_MEM) res->base = resource_max(res); + if (res->base < lim->base) { + /* This usually happens at the domain level, usually + * caused by a device having a BAR which is too big. + * Error out so we can retry. + */ + printk(BIOS_WARNING, + "ERROR: Resource Base was lower than its limit!\n\t"); + printk(BIOS_WARNING, + "%s@%02lx: base value 0x%08llx, lower limit 0x%08llx\n", + dev_path(dev), res->index, res->base, lim->base); + return 1; + } + printk(BIOS_SPEW, "%s:@%s %02lx base %08llx limit %08llx\n", __func__, dev_path(dev), res->index, res->base, res->limit); } + + return 0; +} + +static u8 avoid_all_fixed_resources(struct device *root) +{ + struct device *child; + + /* For all domains. */ + for (child = root->link_list->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_DOMAIN) { + if (avoid_fixed_resources(child)) { + printk( + BIOS_SPEW, + "Error trying to avoid fixed resources."); + + /* Now find the device which is the largest + * and disable it. + */ + struct device *largest = find_pci_dev_max_mem(); + + printk(BIOS_SPEW, "\tDisabling Device %s\n", + dev_path(largest)); + if (largest) + largest->enabled = 0; + + /* Clear out all devices on all domains, ready + * for re-scanning. + */ + printk(BIOS_SPEW, + "\tClearing old resource computations.\n"); + clear_computed_resources(); + return 1; + } + } + } + + return 0; } device_t vga_pri = 0; @@ -1022,45 +1073,54 @@ void dev_configure(void) root = &dev_root; - /* - * Each domain should create resources which contain the entire address - * space for IO, MEM, and PREFMEM resources in the domain. The - * allocation of device resources will be done from this address space. - */ + do { + /* + * Each domain should create resources which contain the entire + * address space for IO, MEM, and PREFMEM resources in the + * domain. The allocation of device resources will be done from + * this address space. + */ - /* Read the resources for the entire tree. */ + /* Read the resources for the entire tree. */ - printk(BIOS_INFO, "Reading resources...\n"); - read_resources(root->link_list); - printk(BIOS_INFO, "Done reading resources.\n"); + printk(BIOS_INFO, "Reading resources...\n"); + read_resources(root->link_list); + printk(BIOS_INFO, "Done reading resources.\n"); - print_resource_tree(root, BIOS_SPEW, "After reading."); + print_resource_tree(root, BIOS_SPEW, "After reading."); - /* Compute resources for all domains. */ - for (child = root->link_list->children; child; child = child->sibling) { - if (!(child->path.type == DEVICE_PATH_DOMAIN)) - continue; - post_log_path(child); - for (res = child->resource_list; res; res = res->next) { - if (res->flags & IORESOURCE_FIXED) - continue; - if (res->flags & IORESOURCE_MEM) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_MEM); - continue; - } - if (res->flags & IORESOURCE_IO) { - compute_resources(child->link_list, - res, IORESOURCE_TYPE_MASK, IORESOURCE_IO); + /* Compute resources for all domains. */ + for (child = root->link_list->children; + child; + child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->flags & IORESOURCE_MEM) { + compute_resources( + child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_MEM); + continue; + } + if (res->flags & IORESOURCE_IO) { + compute_resources(child->link_list, + res, + IORESOURCE_TYPE_MASK, + IORESOURCE_IO); + continue; + } } } - } - /* For all domains. */ - for (child = root->link_list->children; child; child=child->sibling) - if (child->path.type == DEVICE_PATH_DOMAIN) - avoid_fixed_resources(child); + /* Attempt to avoid all fixed resources, if this process + * succeeds then we can carry on, otherwise we should re-try. + */ + } while (avoid_all_fixed_resources(root)); /* Store the computed resource allocations into device registers ... */ printk(BIOS_INFO, "Setting resources...\n"); diff --git a/src/device/device_util.c b/src/device/device_util.c index ac18538..25fd987 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -921,3 +921,112 @@ int dev_count_cpu(void) return count; } + +enum allocation_passes { + PASS_1_CHECK_64_BIT_BARS = 0, + PASS_2_CHECK_32_BIT_BARS = 1, + PASS_3_CHECK_DEVS_WITH_OPROMS = 2, + MAX_PASS = PASS_3_CHECK_DEVS_WITH_OPROMS +}; + +/** @brief finds the enabled, non root-bus, pci device using the most memory. + * + * @return pointer to the device + */ +struct device *find_pci_dev_max_mem(void) +{ + struct device *dev; + struct device *largest_dev = NULL; + struct resource *res; + uint64_t memory_used = 0; + uint64_t most_memory_used = 0; + uint8_t pass; + + for (pass = PASS_1_CHECK_64_BIT_BARS; pass <= MAX_PASS; pass++) { + + /* + * Loop through all pci devices that are not on bus 0, + * skipping them if they're disabled, checking to see + * which uses the most memory. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + /* Skip disabled, root bus, and non-pci devices */ + if ((!(dev->path.type == DEVICE_PATH_PCI)) || + (dev->bus->secondary == 0) || + (dev->enabled == 0)) + continue; + + /* Total the memory used by the device */ + memory_used = 0; + for (res = dev->resource_list; res; res = res->next) { + + /* don't check 32-bit bars on the first pass */ + if (pass == PASS_1_CHECK_64_BIT_BARS && + ((res->flags & IORESOURCE_PCI64) == 0)) + continue; + + /* skip devices with option roms until last */ + if ((pass < PASS_3_CHECK_DEVS_WITH_OPROMS) + && (res->index == PCI_ROM_ADDRESS)) { + memory_used = 0; + break; + } + + if (res->flags & IORESOURCE_MEM) + memory_used += res->size; + } + + /* Save the largest device found so far */ + if (memory_used > most_memory_used) { + most_memory_used = memory_used; + largest_dev = dev; + } + } + + /* break out of the pass loop when we find a device */ + if (largest_dev != NULL) + break; + } + + return largest_dev; +} + +/** @brief clear all non-pnp resources. + * + */ +void clear_computed_resources(void) +{ + struct device *dev; + + /* + * Loop through all non-pnp devices, clearing everything except index + * and the pointer to the next resource. This keeps them from having + * to be re-allocated. + */ + for (dev = &dev_root; dev; dev = dev->next) { + + //skip pnp devices - their resources are set early + if (dev->path.type == DEVICE_PATH_PNP) + continue; + + clear_device_resources(dev); + } +} + +/** @brief clear all resources for a specified device. Leave index and next. + * + */ +void clear_device_resources(struct device *dev) +{ + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) { + res->align = 0; + res->base = 0; + res->flags = 0; + res->gran = 0; + res->limit = 0; + res->size = 0; + } +} diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 5123229..dfc290b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -248,27 +248,49 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) resource->limit = 0xffff; } else { /* A Memory mapped base address. */ - attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; - resource->flags |= IORESOURCE_MEM; - if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) - resource->flags |= IORESOURCE_PREFETCH; - attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; - if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { - /* 32bit limit. */ - resource->limit = 0xffffffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { - /* 1MB limit. */ - resource->limit = 0x000fffffUL; - } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { - /* 64bit limit. */ - resource->limit = 0xffffffffffffffffULL; - resource->flags |= IORESOURCE_PCI64; + if (CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE && + (resource->size > CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE)) { + /* Disable devices that attempt to allocate a BAR beyond + the max configured size. */ + printk(BIOS_WARNING, + "Device at %s requested a 0x%llx byte BAR ", + dev_path(dev), + (unsigned long long)resource->size); + printk(BIOS_WARNING, + "for register 0x%02lx.\n", + index); + printk(BIOS_WARNING, + "The device exceeded largest allowed size of 0x%lx. ", + (unsigned long) + CONFIG_MAX_MEM_BAR_SIZE_TO_ALLOCATE); + printk(BIOS_WARNING, "Device disabled.\n"); + dev->enabled = 0; + clear_device_resources(dev); } else { - /* Invalid value. */ - printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); - printk(BIOS_ERR, " on dev %s at index %02lx\n", - dev_path(dev), index); - resource->flags = 0; + attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK; + resource->flags |= IORESOURCE_MEM; + if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) + resource->flags |= IORESOURCE_PREFETCH; + attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK; + if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) { + /* 32bit limit. */ + resource->limit = 0xffffffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) { + /* 1MB limit. */ + resource->limit = 0x000fffffUL; + } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) { + /* 64bit limit. */ + resource->limit = 0xffffffffffffffffULL; + resource->flags |= IORESOURCE_PCI64; + } else { + /* Invalid value. */ + printk(BIOS_ERR, + "Broken BAR with value %lx\n", + attr); + printk(BIOS_ERR, " on dev %s at index %02lx\n", + dev_path(dev), index); + resource->flags = 0; + } } } @@ -344,6 +366,8 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); + if (dev->enabled == 0) + return; index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 62460ae..c857dd2 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,10 @@ void fixed_mem_resource(device_t dev, unsigned long index, void scan_smbus(device_t bus); void scan_lpc_bus(device_t bus); +struct device *find_pci_dev_max_mem(void); +void clear_computed_resources(void); +void clear_device_resources(struct device *dev); + /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. */

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New patch to review for coreboot: build system: strip quotes from CONFIG_CBFS_PREFIX in a single location
by Patrick Georgi 30 Nov '15

30 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12578 -gerrit commit d5ee1944c33315e23e3bbe0d4ef83f98a86f0e11 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Nov 30 22:44:53 2015 +0100 build system: strip quotes from CONFIG_CBFS_PREFIX in a single location Instead of having to remember to strip the quotes everywhere so that string comparisons (of which there are a few) match up, do it right at the beginning. Fixes building the image with a .config where CONFIG_CBFS_PREFIX contains quotes. Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 16 ++++++++++------ src/arch/arm64/Makefile.inc | 4 ++-- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 4eebc71..e68ee6e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -16,6 +16,10 @@ GIT:=$(shell [ -d "$(top)/.git" ] && command -v git) ####################################################################### +# normalize Kconfig variables in a central place +CONFIG_CBFS_PREFIX:=$(call strip_quotes,$(CONFIG_CBFS_PREFIX)) + +####################################################################### # misleadingly named, this is the coreboot version export KERNELVERSION := $(strip $(if $(GIT),\ $(shell git describe --dirty --always || git describe),\ @@ -31,7 +35,7 @@ export MAINBOARDDIR ## Final build results, which CBFSTOOL uses to create the final ## rom image file, are placed under $(objcbfs). ## These typically have suffixes .debug .elf .bin and .map -export objcbfs := $(obj)/cbfs/$(call strip_quotes,$(CONFIG_CBFS_PREFIX)) +export objcbfs := $(obj)/cbfs/$(CONFIG_CBFS_PREFIX) ## Based on the active configuration, Makefile conditionally collects ## the required assembly includes and saves them in a file. @@ -189,10 +193,10 @@ endef # arg1: base file name # arg2: y or n for including in cbfs. defaults to y define asl_template -$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-file = $(obj)/$(1).aml -$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-type = raw -$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-compression = none -cbfs-files-$(if $(2),$(2),y) += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml +$(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml +$(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw +$(CONFIG_CBFS_PREFIX)/$(1).aml-compression = none +cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ @@ -622,7 +626,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # Add all cbfs files to image of the form: CONFIG_CBFS_PREFIX/<filename> prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(if $(filter $(call strip_quotes, $(CONFIG_CBFS_PREFIX))/%,\ + $(if $(filter $(CONFIG_CBFS_PREFIX)/%,\ $(call extract_nth,2,$(file))), \ $(if $(call extract_nth,6,$(file)),$(cbfs-add-cmd) -a $(call extract_nth,6,$(file)) &&,\ $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&))) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 1cbc9a4..b1e20dc 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -168,7 +168,7 @@ $(BL31): .PHONY: $(BL31) -BL31_CBFS := $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/bl31 +BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 $(BL31_CBFS)-file := $(BL31) $(BL31_CBFS)-type := stage $(BL31_CBFS)-compression := $(CBFS_COMPRESS_FLAG) @@ -177,7 +177,7 @@ cbfs-files-y += $(BL31_CBFS) ifeq ($(CONFIG_ARM64_USE_SECURE_OS),y) SECURE_OS_FILE := $(CONFIG_ARM64_SECURE_OS_FILE) -SECURE_OS_FILE_CBFS := $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/secure_os +SECURE_OS_FILE_CBFS := $(CONFIG_CBFS_PREFIX)/secure_os $(SECURE_OS_FILE_CBFS)-file := $(SECURE_OS_FILE) $(SECURE_OS_FILE_CBFS)-type := stage cbfs-files-y += $(SECURE_OS_FILE_CBFS)

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Patch set updated for coreboot: intel/fsp_rangeley: change non-existent config options to #defines
by Martin Roth 30 Nov '15

30 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12552 -gerrit commit 70d0f908e33a3716b010c85e7991991de95da4aa Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 15:58:12 2015 -0700 intel/fsp_rangeley: change non-existent config options to #defines Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/acpi/mainboard.asl | 3 +++ src/mainboard/intel/littleplains/dsdt.asl | 3 +++ src/mainboard/intel/mohonpeak/acpi/mainboard.asl | 3 +++ src/mainboard/intel/mohonpeak/dsdt.asl | 3 +++ src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 4 ++-- 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/littleplains/acpi/mainboard.asl b/src/mainboard/intel/littleplains/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/littleplains/acpi/mainboard.asl +++ b/src/mainboard/intel/littleplains/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index dbb8b15..ec56e26 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -23,6 +23,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl +++ b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index dbb8b15..ec56e26 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -23,6 +23,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 22edf50..696a81a 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -30,7 +30,7 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_PMIO) +#ifdef ACPI_INCLUDE_PMIO // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) @@ -77,7 +77,7 @@ Scope(\) } #endif -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_GPIO) +#ifdef ACPI_INCLUDE_GPIO // GPIO IO mapped registers (0x1f.0 reg 0x48.l) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve)

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Patch set updated for coreboot: intel/fsp_rangeley: change non-existent config options to #defines
by Martin Roth 30 Nov '15

30 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12552 -gerrit commit 7db211ce41c7ed114b9e3496c59f7378ac77bd29 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 15:58:12 2015 -0700 intel/fsp_rangeley: change non-existent config options to #defines The Kconfig symbols ONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/littleplains/acpi/mainboard.asl | 3 +++ src/mainboard/intel/littleplains/dsdt.asl | 3 +++ src/mainboard/intel/mohonpeak/acpi/mainboard.asl | 3 +++ src/mainboard/intel/mohonpeak/dsdt.asl | 3 +++ src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 4 ++-- 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/littleplains/acpi/mainboard.asl b/src/mainboard/intel/littleplains/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/littleplains/acpi/mainboard.asl +++ b/src/mainboard/intel/littleplains/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl index dbb8b15..ec56e26 100644 --- a/src/mainboard/intel/littleplains/dsdt.asl +++ b/src/mainboard/intel/littleplains/dsdt.asl @@ -23,6 +23,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl +++ b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index dbb8b15..ec56e26 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -23,6 +23,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 22edf50..696a81a 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -30,7 +30,7 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_PMIO) +#ifdef ACPI_INCLUDE_PMIO // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) @@ -77,7 +77,7 @@ Scope(\) } #endif -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_GPIO) +#ifdef ACPI_INCLUDE_GPIO // GPIO IO mapped registers (0x1f.0 reg 0x48.l) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve)

1 0

Patch set updated for coreboot: amd/pi/00630F01: Drop HT3_SUPPORT
by Martin Roth 30 Nov '15

30 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12556 -gerrit commit 6edcbfef2891718e3853d5b217014d8d9dcd002b Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 21:51:03 2015 -0700 amd/pi/00630F01: Drop HT3_SUPPORT The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented. This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT) Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/northbridge/amd/pi/00630F01/northbridge.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 9f55874..2809f2f 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -1039,13 +1039,7 @@ static void cpu_bus_scan(device_t dev) /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - int linknum; -#if IS_ENABLED(CONFIG_HT3_SUPPORT) - linknum = 8; -#else - linknum = 4; -#endif - add_more_links(cdb_dev, linknum); + add_more_links(cdb_dev, 4); } family = cpuid_eax(1);

1 0

Patch set updated for coreboot: lippert/frontronner-af & toucan-af: Fix IASL warnings
by Martin Roth 30 Nov '15

30 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12530 -gerrit commit 51fda75d7687b2c1898105740cec6123a70fdf72 Author: Martin Roth <martinroth(a)google.com> Date: Tue Nov 24 16:17:11 2015 -0700 lippert/frontronner-af & toucan-af: Fix IASL warnings Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. Fixes warnings for both platforms: dsdt.aml 1143: Method(_OSC,4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 1143: Method(_OSC,4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/lippert/frontrunner-af/Kconfig | 4 ---- src/mainboard/lippert/frontrunner-af/dsdt.asl | 16 ++++++++++++---- src/mainboard/lippert/toucan-af/Kconfig | 4 ---- src/mainboard/lippert/toucan-af/dsdt.asl | 16 ++++++++++++---- 4 files changed, 24 insertions(+), 16 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index ebf362d..1ec219e 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -76,8 +76,4 @@ config SB800_AHCI_ROM bool default n -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - endif # BOARD_LIPPERT_FRONTRUNNER_AF diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index a685b2c..86eccb2 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1158,14 +1158,22 @@ DefinitionBlock ( Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Operating System Capabilities Method */ - Method(_OSC,4) - { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + Method (_OSC, 4) + { + /* Check for PCI/PCI-X/PCIe GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } - } + Else + { + /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } /* End _OSC */ Method(_BBN, 0) { /* Bus number = 0 */ Return(0) diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 9e29a85..590909b 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -78,8 +78,4 @@ config SB800_AHCI_ROM bool default n -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - endif # BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 89c5c33..9c537fa 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1158,14 +1158,22 @@ DefinitionBlock ( Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ /* Operating System Capabilities Method */ - Method(_OSC,4) - { /* Check for proper PCI/PCIe UUID */ - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + Method (_OSC, 4) + { + /* Check for PCI/PCI-X/PCIe GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { /* Let OS control everything */ Return (Arg3) } - } + Else + { + /* Unrecognized UUID, so set bit 2 of Arg3 to 1 */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } /* End _OSC */ Method(_BBN, 0) { /* Bus number = 0 */ Return(0)

1 0

Patch set updated for coreboot: southbridge/amd/sr5650: Add MCFG ACPI table support
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12050 -gerrit commit 4085b1fa4fe2ad4e226f736f8ecc9f3fb2a3d955 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 15:20:42 2015 -0500 southbridge/amd/sr5650: Add MCFG ACPI table support Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--- src/southbridge/amd/rs780/rs780.c | 12 ++++ src/southbridge/amd/sb700/lpc.c | 6 -- src/southbridge/amd/sb800/lpc.c | 7 +- src/southbridge/amd/sr5650/Kconfig | 9 +++ src/southbridge/amd/sr5650/ht.c | 107 ++++++++++++++++++++++++++++- src/southbridge/amd/sr5650/sr5650.c | 18 +++++ 7 files changed, 156 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c8bf8fa..b376171 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -737,16 +737,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_MMCONF_SUPPORT - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); -#endif + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT) && !IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); + } if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c82a629..6eb4295 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -349,6 +350,17 @@ void rs780_enable(device_t dev) } } +#if !IS_ENABLED(CONFIG_AMD_SB_CIMX) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* FIXME + * Leave table blank until proper contents + * are determined. + */ + return current; +} +#endif + struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("ATI RS780") .enable_dev = rs780_enable, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a71fe1f..78933fa 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -30,12 +30,6 @@ #include <cpu/amd/powernow.h> #include "sb700.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 756a0c4..18d4471 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,6 @@ #include <arch/acpi.h> #include "sb800.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig index 29017c6..f2d12ff 100644 --- a/src/southbridge/amd/sr5650/Kconfig +++ b/src/southbridge/amd/sr5650/Kconfig @@ -15,3 +15,12 @@ config SOUTHBRIDGE_AMD_SR5650 bool + +if SOUTHBRIDGE_AMD_SR5650 +config EXT_CONF_SUPPORT + bool "Enable PCI-E MMCONFIG support" + default n + help + Select to enable PCI-E MMCONFIG support on the SR5650. + +endif diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 6119985..e74d36b 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -20,7 +20,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/ioapic.h> +#include <lib.h> #include "sr5650.h" +#include "cmn.h" /* Table 6-6 Recommended Interrupt Routing Configuration */ typedef struct _apic_device_info { @@ -154,11 +156,29 @@ static void pcie_init(struct device *dev) static void sr5690_read_resource(struct device *dev) { + struct resource *res; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + } + pci_dev_read_resources(dev); /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + res = new_resource(dev, 0x1c); /* PCIe MCFG space */ + res->base = EXT_CONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_ASSIGNED | IORESOURCE_RESERVE | IORESOURCE_BRIDGE; + } compact_resources(dev); } @@ -166,7 +186,88 @@ static void sr5690_read_resource(struct device *dev) /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ static void sr5690_set_resources(struct device *dev) { - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + uint32_t reg; + device_t amd_ht_cfg_dev; + device_t amd_addr_map_dev; + resource_t res_base; + resource_t res_end; + uint32_t base; + uint32_t limit; + struct resource *res; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + + res = probe_resource(dev, 0x1c); + if (res) { + /* Find requisite AMD CPU devices */ + amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + if (!amd_ht_cfg_dev || !amd_addr_map_dev) { + printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); + } + else { + /* Set up MMCONFIG bus range */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ + pci_write_config32(dev, 0x1c, res->base); + + /* Enable MMCONFIG decoding. */ + set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + + /* Set up nonposted resource in MMIO space */ + res_base = res->base; /* Get the base address */ + res_end = resource_end(res); /* Get the limit (rounded up) */ + printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); + + /* Locate an unused MMIO resource */ + for (reg = 0xb8; reg >= 0x80; reg -= 8) { + base = pci_read_config32(amd_addr_map_dev, reg); + limit = pci_read_config32(amd_addr_map_dev, reg + 4); + if (!(base & 0x3)) + break; /* Unused resource found */ + } + + /* If an unused MMIO resource was available, set up the mapping */ + if (!(base & 0x3)) { + uint32_t sblk; + + /* Remember this resource has been stored. */ + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " <mmconfig>"); + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; + + /* Calculate the MMIO mapping base */ + base &= 0x000000f0; + base |= ((res_base >> 8) & 0xffffff00); + base |= 3; + + /* Calculate the MMIO mapping limit */ + limit &= 0x00000048; + limit |= ((res_end >> 8) & 0xffffff00); + limit |= (sblk << 4); + limit |= (1 << 7); + + /* Configure and enable MMIO mapping */ + printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); + pci_write_config32(amd_addr_map_dev, reg + 4, limit); + pci_write_config32(amd_addr_map_dev, reg, base); + } + else { + printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); + } + } + } + } + pci_dev_set_resources(dev); } diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 07b4a02..54f0071 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -796,6 +796,24 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, i free(root_level); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Report MMCONF base */ + res = probe_resource(dev, 0x1c); + if (res) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); + } + + return current; +} + static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) { uint8_t *p;

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Enable GART by default
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12067 -gerrit commit 886baaa22a51e9ff18142f4aeee6d1bb1252d93b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 19:27:40 2015 -0500 mainboard/asus/kgpe-d16: Enable GART by default Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index b5e9f07..a05b9c3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -23,7 +23,7 @@ maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable ieee1394_controller = Enable -gart = Disable +gart = Enable experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback

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coreboot-gerrit November 2015