coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: northbridge/amd/amdht: Reduce excessive romstage array size
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12573 -gerrit commit 45c7e6d187e5a5ea3dd53dbd429e900b64bd46f1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Nov 16 11:48:38 2015 -0600 northbridge/amd/amdht: Reduce excessive romstage array size Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/ht_wrapper.c | 48 +++++++++++++++++----------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 18c0ac4..129b02d 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -91,25 +91,25 @@ static const char * event_class_string_decodes[] = { }; static const char * event_string_decodes[] = { - [HT_EVENT_COH_EVENTS] = "HT_EVENT_COH_EVENTS", - [HT_EVENT_COH_NO_TOPOLOGY] = "HT_EVENT_COH_NO_TOPOLOGY", - [HT_EVENT_COH_LINK_EXCEED] = "HT_EVENT_COH_LINK_EXCEED", - [HT_EVENT_COH_FAMILY_FEUD] = "HT_EVENT_COH_FAMILY_FEUD", - [HT_EVENT_COH_NODE_DISCOVERED] = "HT_EVENT_COH_NODE_DISCOVERED", - [HT_EVENT_COH_MPCAP_MISMATCH] = "HT_EVENT_COH_MPCAP_MISMATCH", - [HT_EVENT_NCOH_EVENTS] = "HT_EVENT_NCOH_EVENTS", - [HT_EVENT_NCOH_BUID_EXCEED] = "HT_EVENT_NCOH_BUID_EXCEED", - [HT_EVENT_NCOH_LINK_EXCEED] = "HT_EVENT_NCOH_LINK_EXCEED", - [HT_EVENT_NCOH_BUS_MAX_EXCEED] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", - [HT_EVENT_NCOH_CFG_MAP_EXCEED] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", - [HT_EVENT_NCOH_DEVICE_FAILED] = "HT_EVENT_NCOH_DEVICE_FAILED", - [HT_EVENT_NCOH_AUTO_DEPTH] = "HT_EVENT_NCOH_AUTO_DEPTH", - [HT_EVENT_OPT_EVENTS] = "HT_EVENT_OPT_EVENTS", - [HT_EVENT_OPT_REQUIRED_CAP_RETRY] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", - [HT_EVENT_OPT_REQUIRED_CAP_GEN3] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", - [HT_EVENT_HW_EVENTS] = "HT_EVENT_HW_EVENTS", - [HT_EVENT_HW_SYNCHFLOOD] = "HT_EVENT_HW_SYNCHFLOOD", - [HT_EVENT_HW_HTCRC] = "HT_EVENT_HW_HTCRC" + [(HT_EVENT_COH_EVENTS & 0xfff)] = "HT_EVENT_COH_EVENTS", + [(HT_EVENT_COH_NO_TOPOLOGY & 0xfff)] = "HT_EVENT_COH_NO_TOPOLOGY", + [(HT_EVENT_COH_LINK_EXCEED & 0xfff)] = "HT_EVENT_COH_LINK_EXCEED", + [(HT_EVENT_COH_FAMILY_FEUD & 0xfff)] = "HT_EVENT_COH_FAMILY_FEUD", + [(HT_EVENT_COH_NODE_DISCOVERED & 0xfff)] = "HT_EVENT_COH_NODE_DISCOVERED", + [(HT_EVENT_COH_MPCAP_MISMATCH & 0xfff)] = "HT_EVENT_COH_MPCAP_MISMATCH", + [(HT_EVENT_NCOH_EVENTS & 0xfff)] = "HT_EVENT_NCOH_EVENTS", + [(HT_EVENT_NCOH_BUID_EXCEED & 0xfff)] = "HT_EVENT_NCOH_BUID_EXCEED", + [(HT_EVENT_NCOH_LINK_EXCEED & 0xfff)] = "HT_EVENT_NCOH_LINK_EXCEED", + [(HT_EVENT_NCOH_BUS_MAX_EXCEED & 0xfff)] = "HT_EVENT_NCOH_BUS_MAX_EXCEED", + [(HT_EVENT_NCOH_CFG_MAP_EXCEED & 0xfff)] = "HT_EVENT_NCOH_CFG_MAP_EXCEED", + [(HT_EVENT_NCOH_DEVICE_FAILED & 0xfff)] = "HT_EVENT_NCOH_DEVICE_FAILED", + [(HT_EVENT_NCOH_AUTO_DEPTH & 0xfff)] = "HT_EVENT_NCOH_AUTO_DEPTH", + [(HT_EVENT_OPT_EVENTS & 0xfff)] = "HT_EVENT_OPT_EVENTS", + [(HT_EVENT_OPT_REQUIRED_CAP_RETRY & 0xfff)] = "HT_EVENT_OPT_REQUIRED_CAP_RETRY", + [(HT_EVENT_OPT_REQUIRED_CAP_GEN3 & 0xfff)] = "HT_EVENT_OPT_REQUIRED_CAP_GEN3", + [(HT_EVENT_HW_EVENTS & 0xfff)] = "HT_EVENT_HW_EVENTS", + [(HT_EVENT_HW_SYNCHFLOOD & 0xfff)] = "HT_EVENT_HW_SYNCHFLOOD", + [(HT_EVENT_HW_HTCRC & 0xfff)] = "HT_EVENT_HW_HTCRC" }; /** @@ -146,7 +146,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: case HT_EVENT_COH_FAMILY_FEUD: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); break; case HT_EVENT_COH_NODE_DISCOVERED: { @@ -163,11 +163,11 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_NCOH_LINK_EXCEED: case HT_EVENT_NCOH_BUS_MAX_EXCEED: case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); break; case HT_EVENT_NCOH_DEVICE_FAILED: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); sHtEventNcohDeviceFailed *evt = (sHtEventNcohDeviceFailed*)pEventData0; printk(log_level, ": node %d link %d depth: %d attemptedBUID: %d", evt->node, evt->link, evt->depth, evt->attemptedBUID); @@ -176,7 +176,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) } case HT_EVENT_NCOH_AUTO_DEPTH: { - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); sHtEventNcohAutoDepth *evt = (sHtEventNcohAutoDepth*)pEventData0; printk(log_level, ": node %d link %d depth: %d", evt->node, evt->link, evt->depth); @@ -189,7 +189,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) case HT_EVENT_HW_EVENTS: case HT_EVENT_HW_SYNCHFLOOD: case HT_EVENT_HW_HTCRC: - printk(log_level, event_string_decodes[event]); + printk(log_level, event_string_decodes[event & 0xfff]); break; default: printk(log_level, "HT_EVENT_UNKNOWN");

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Patch set updated for coreboot: southbridge/amd/sb700: Fix boot hang when AHCI mode disabled
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12572 -gerrit commit 3f7e3014b5a78d6ec47b3f021f13c0b50a1ee523 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Oct 25 18:58:24 2015 -0500 southbridge/amd/sb700: Fix boot hang when AHCI mode disabled Existence of requested PCI device was not checked when enabling IDE mode on the SP5100. Fix incorrect PCI device ID and check for device existence before attempting setup. Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index f7e9120..06c6c77 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -520,26 +520,28 @@ static void sb700_devices_por_init(void) if (!sata_ahci_mode){ #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* SP5100 default SATA mode is RAID5 MODE */ - dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); + dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0); - /* Set SATA Operation Mode, Set to IDE mode */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 0); - pci_write_config8(dev, 0x40, byte); + if (dev != PCI_DEV_INVALID) { + /* Set SATA Operation Mode, Set to IDE mode */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 0); + pci_write_config8(dev, 0x40, byte); - dword = 0x01018f00; - pci_write_config32(dev, 0x8, dword); + dword = 0x01018f00; + pci_write_config32(dev, 0x8, dword); - /* set SATA Device ID writable */ - dword = pci_read_config32(dev, 0x40); - dword &= ~(1 << 24); - pci_write_config32(dev, 0x40, dword); + /* set SATA Device ID writable */ + dword = pci_read_config32(dev, 0x40); + dword &= ~(1 << 24); + pci_write_config32(dev, 0x40, dword); - /* set Device ID consistent with IDE emulation mode configuration */ - pci_write_config32(dev, 0x0, 0x43901002); + /* set Device ID consistent with IDE emulation mode configuration */ + pci_write_config32(dev, 0x0, 0x43901002); - /* rpr v2.13 4.17 Reset CPU on Sync Flood */ - abcfg_reg(0x10050, 1 << 2, 1 << 2); + /* rpr v2.13 4.17 Reset CPU on Sync Flood */ + abcfg_reg(0x10050, 1 << 2, 1 << 2); + } #endif }

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12069 -gerrit commit 3e8ec008a31bd6303cdcaff76b9ab1514cdbb60e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 18:07:03 2015 -0500 cpu/amd/fam10h-15h: Force iolink detect to either 1 or 0 Minor change to be more explicit about the binary state of the iolink detect variable. Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 635f357..22e0cb4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1244,7 +1244,7 @@ static void cpuSetAMDPCI(u8 node) for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); - iolink = (AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); + iolink = !!(AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); if (!iolink && ganged) { if (probe_filter_enabled) { @@ -1360,7 +1360,7 @@ static void cpuSetAMDPCI(u8 node) for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); - iolink = (AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); + iolink = !!(AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); /* Set defaults */ isoc_rsp_tok_1 = 0;

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Patch set updated for coreboot: nb/amd/amdfam10: Fix incorrect channel buffer count configuration
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12068 -gerrit commit 3492997a5db594562c3fe838627dbc6231e244d2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 03:39:15 2015 -0500 nb/amd/amdfam10: Fix incorrect channel buffer count configuration The secondary bus number set code incorrectly overwrote the link buffer settings in F0x[F4,D4,B4,94]. Constrain the secondary bus number set to the appropriate bits of the registers. Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 85cee13..c8bf8fa 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -184,17 +184,14 @@ static void ht_route_link(struct bus *link, scan_state mode) * not correctly configured */ busses = pci_read_config32(link->dev, link->cap + 0x14); - busses &= 0xff000000; + busses &= ~(0xff << 8); busses |= parent->secondary & 0xff; - if (mode == HT_ROUTE_CLOSE) { - busses |= 0xfeff << 8; - } else if (mode == HT_ROUTE_SCAN) { + if (mode == HT_ROUTE_CLOSE) + busses |= 0xff << 8; + else if (mode == HT_ROUTE_SCAN) busses |= ((u32) link->secondary & 0xff) << 8; - busses |= 0xfc << 16; - } else if (mode == HT_ROUTE_FINAL) { + else if (mode == HT_ROUTE_FINAL) busses |= ((u32) link->secondary & 0xff) << 8; - busses |= ((u32) link->subordinate & 0xff) << 16; - } pci_write_config32(link->dev, link->cap + 0x14, busses); if (mode == HT_ROUTE_FINAL) {

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12071 -gerrit commit 28f8dedf4ffee3b22cf079871a57b60a4907c3be Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 22:26:55 2015 -0500 cpu/amd/fam10h-15h: Fix link type detection and XCS buffer count setup The existing code did not properly detect various link attributes on Family 10h/15h processors. With the addition of new HT3- and IOMMU-specific code, proper detection has become critical to avoid system deadlocks. Fix and streamline link attribute detection. Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 33 +++++++++++++++------------ 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 3619a9c..2edb75e 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -375,7 +375,7 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { uint8_t link0isGen3 = 0; uint8_t offset; if (AMD_CpuFindCapability(node, 0, &offset)) { - link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); + link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3 ); } /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package S1g3 in link Gen3 mode, but I don't know how to tell diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 22e0cb4..bf1862b 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -842,7 +842,7 @@ static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) * * Returns the link characteristic mask. */ -static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) +static u32 AMD_checkLinkType(u8 node, u8 regoff) { uint32_t val; uint32_t val2; @@ -873,7 +873,7 @@ static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) linktype |= HTPHY_LINKTYPE_HT1; /* Check ganged */ - val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); + val = pci_read_config32(NODE_PCI(node, 0), (((regoff - 0x80) / 0x20) << 2) + 0x170); if (val & 1) linktype |= HTPHY_LINKTYPE_GANGED; @@ -1116,7 +1116,7 @@ static void cpuSetAMDPCI(u8 node) */ for (j = 0; j < 4; j++) { if (AMD_CpuFindCapability(node, j, &offset)) { - if (AMD_checkLinkType(node, j, offset) + if (AMD_checkLinkType(node, offset) & fam10_htphy_default[i].linktype) { AMD_SetHtPhyRegister(node, j, i); @@ -1214,6 +1214,7 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); uint8_t link; + uint8_t link_real; uint8_t ganged; uint8_t iolink; uint8_t probe_filter_enabled = !!dual_node; @@ -1243,8 +1244,9 @@ static void cpuSetAMDPCI(u8 node) for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { - ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); - iolink = !!(AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); + link_real = (offset - 0x80) / 0x20; + ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link_real << 2) + 0x170) & 0x1); + iolink = !!(AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_NONCOHERENT); if (!iolink && ganged) { if (probe_filter_enabled) { @@ -1304,7 +1306,7 @@ static void cpuSetAMDPCI(u8 node) np_req_cmd = 12; } - dword = pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x94); + dword = pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x94); dword &= ~(0x3 << 27); /* IsocRspData = isoc_rsp_data */ dword |= ((isoc_rsp_data & 0x3) << 27); dword &= ~(0x3 << 25); /* IsocNpReqData = isoc_np_req_data */ @@ -1315,9 +1317,9 @@ static void cpuSetAMDPCI(u8 node) dword |= ((isoc_preq & 0x7) << 19); dword &= ~(0x7 << 16); /* IsocNpReqCmd = isoc_np_req_cmd */ dword |= ((isoc_np_req_cmd & 0x7) << 16); - pci_write_config32(NODE_PCI(node, 0), (link * 0x20) + 0x94, dword); + pci_write_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x94, dword); - dword = pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x90); + dword = pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x90); dword &= ~(0x1 << 31); /* LockBc = 0x1 */ dword |= ((0x1 & 0x1) << 31); dword &= ~(0x7 << 25); /* FreeData = free_data */ @@ -1336,7 +1338,7 @@ static void cpuSetAMDPCI(u8 node) dword |= ((preq & 0x7) << 5); dword &= ~(0x1f << 0); /* NpReqCmd = np_req_cmd */ dword |= ((np_req_cmd & 0x1f) << 0); - pci_write_config32(NODE_PCI(node, 0), (link * 0x20) + 0x90, dword); + pci_write_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x90, dword); } } @@ -1359,8 +1361,9 @@ static void cpuSetAMDPCI(u8 node) for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { - ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); - iolink = !!(AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); + link_real = (offset - 0x80) / 0x20; + ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link_real << 2) + 0x170) & 0x1); + iolink = !!(AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_NONCOHERENT); /* Set defaults */ isoc_rsp_tok_1 = 0; @@ -1588,7 +1591,7 @@ static void cpuSetAMDPCI(u8 node) } } - dword = pci_read_config32(NODE_PCI(node, 3), (link << 2) + 0x148); + dword = pci_read_config32(NODE_PCI(node, 3), (link_real << 2) + 0x148); dword &= ~(0x3 << 30); /* FreeTok[3:2] = free_tokens[3:2] */ dword |= (((free_tokens >> 2) & 0x3) << 30); dword &= ~(0x1 << 28); /* IsocRspTok1 = isoc_rsp_tok_1 */ @@ -1621,7 +1624,7 @@ static void cpuSetAMDPCI(u8 node) dword |= (((preq_tok_0) & 0x3) << 2); dword &= ~(0x3 << 0); /* ReqTok0 = req_tok_0 */ dword |= (((req_tok_0) & 0x3) << 0); - pci_write_config32(NODE_PCI(node, 3), (link << 2) + 0x148, dword); + pci_write_config32(NODE_PCI(node, 3), (link_real << 2) + 0x148, dword); } } @@ -1667,6 +1670,7 @@ static void cpuSetAMDPCI(u8 node) } uint8_t link; + uint8_t link_real; uint8_t isochronous; uint8_t isochronous_link_present; @@ -1675,7 +1679,8 @@ static void cpuSetAMDPCI(u8 node) if (revision & AMD_FAM15_ALL) { for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { - isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; + link_real = (offset - 0x80) / 0x20; + isochronous = (pci_read_config32(NODE_PCI(node, 0), (link_real * 0x20) + 0x84) >> 12) & 0x1; if (isochronous) isochronous_link_present = 1;

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Patch set updated for coreboot: nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12070 -gerrit commit 0735efdfab69229c82ab73923a3d9776b778e9b1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Sep 7 18:07:43 2015 -0500 nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs The existing code re-used the Family 10h XCS buffer setup on Family 15h CPUs, which set incorrect values leading to random system lockups. Use the Family 15h XCS buffer setup shown in the BKDG. Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/h3ncmn.c | 94 +++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 7937c6e..cbe90e0 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1389,6 +1390,75 @@ static uint32_t fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) /***************************************************************************//** * + * static u16 + * fam15NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) + * + * Description: + * Return a mask that eliminates HT frequencies that cannot be used due to a slow + * northbridge frequency. + * + * Parameters: + * @param[in] node = Result could (later) be for a specific node + * @param[in] *nb = this northbridge + * @return = Frequency mask + * + ******************************************************************************/ +static uint32_t fam15NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +{ + u8 nbCOF; + uint32_t supported; + + nbCOF = getMinNbCOF(); + /* + * nbCOF is minimum northbridge speed in hundreds of MHz. + * HT can not go faster than the minimum speed of the northbridge. + */ + if ((nbCOF >= 6) && (nbCOF < 10)) + { + /* Generation 1 HT link frequency */ + /* Convert frequency to bit and all less significant bits, + * by setting next power of 2 and subtracting 1. + */ + supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; + } + else if ((nbCOF >= 10) && (nbCOF <= 32)) + { + /* Generation 3 HT link frequency + * Assume error retry is enabled on all Gen 3 links + */ + nbCOF *= 2; + if (nbCOF > 32) + nbCOF = 32; + + /* Convert frequency to bit and all less significant bits, + * by setting next power of 2 and subtracting 1. + */ + supported = ((uint32_t)1 << ((nbCOF >> 1) + 2)) - 1; + } + else if (nbCOF > 32) + { + supported = HT_FREQUENCY_LIMIT_3200M; + } + /* unlikely cases, but include as a defensive measure, also avoid trick above */ + else if (nbCOF == 4) + { + supported = HT_FREQUENCY_LIMIT_400M; + } + else if (nbCOF == 2) + { + supported = HT_FREQUENCY_LIMIT_200M; + } + else + { + STOP_HERE; + supported = HT_FREQUENCY_LIMIT_200M; + } + + return (fixEarlySampleFreqCapability(supported)); +} + +/***************************************************************************//** + * * static void * gatherLinkData(sMainData *pDat, cNorthBridge *nb) * @@ -2266,6 +2336,26 @@ static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) } } +/***************************************************************************//** + * + * static void + * fam15BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) + * + * Description: + * Buffer tunings are inherently northbridge specific. Check for specific configs + * which require adjustments and apply any standard workarounds to this node. + * + * Parameters: + * @param[in] node = the node to tune + * @param[in] *pDat = global state + * @param[in] nb = this northbridge + * + ******************************************************************************/ +static void fam15BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) +{ + /* Buffer count setup on Family 15h is currently handled in cpuSetAMDPCI */ +} + /* * North Bridge 'constructor'. * @@ -2324,11 +2414,11 @@ void newNorthBridge(u8 node, cNorthBridge *nb) ht3SetCFGAddrMap, convertBitsToWidth, convertWidthToBits, - fam10NorthBridgeFreqMask, + fam15NorthBridgeFreqMask, gatherLinkData, setLinkData, ht3WriteTrafficDistribution, - fam10BufferOptimizations, + fam15BufferOptimizations, 0x00000001, 0x00000200, 18,

1 0

Patch set updated for coreboot: cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 links
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12072 -gerrit commit e28d0749c70688b85a4e95c7526f527e52913767 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Sep 13 15:54:32 2015 -0500 cpu/amd/fam10h-15h: Enable DFE on Family 15h HT3 links Decision Feedback Equalization (DFE) is a form of dynamic link training used to lower the overall error rate within the coherent fabric. Enable it on all capable HT links. Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 28df747..57c0518 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -840,4 +840,12 @@ static const struct { { 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, [20:16] RttIndex = 04h */ + + { 0xc4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d, + [7] DfeEn = 0x1 */ + + { 0xd4, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, + 0x00013480, 0x0003fc80 }, /* [17:10] DCV = 0x4d, + [7] DfeEn = 0x1 */ };

1 0

Patch set updated for coreboot: nb/amd/mct_ddr3: Add Family 15h tristate enable codes
by Timothy Pearson 30 Nov '15

30 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12060 -gerrit commit cbc92a5d07d7b7b4e4e3971f7944373ad946581a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 27 23:37:38 2015 -0500 nb/amd/mct_ddr3: Add Family 15h tristate enable codes The Family 15h DRAM initialization did not set up the various tristate enable codes in the MCT. Add Family 15h tristate enable setup. This fixes multiple DIMMs on a single channel. Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 336 ++++++++++++++++++++----- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 26 +- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 4 + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 8 +- 6 files changed, 310 insertions(+), 74 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 74d5a8d..cb83fe1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1366,6 +1366,224 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc return slow_access; } +static uint8_t fam15h_odt_tristate_enable_code(struct DCTStatStruc *pDCTstat, uint8_t dct) +{ + uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); + + uint8_t package_type; + uint8_t odt_tristate_code = 0; + + package_type = mctGet_NVbits(NV_PACK_TYPE); + + /* Obtain number of DIMMs on channel */ + uint8_t dimm_count = pDCTstat->MAdimms[dct]; + uint8_t rank_count_dimm0; + uint8_t rank_count_dimm1; + + if (package_type == PT_GR) { + /* Socket G34 */ + if (pDCTstat->Status & (1 << SB_Registered)) { + /* RDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 104 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm0 == 1) + odt_tristate_code = 0xe; + else + odt_tristate_code = 0xa; + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm1 == 1) + odt_tristate_code = 0xd; + else + odt_tristate_code = 0x5; + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) + odt_tristate_code = 0xc; + else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 >= 2)) + odt_tristate_code = 0x4; + else if ((rank_count_dimm0 >= 2) && (rank_count_dimm1 == 1)) + odt_tristate_code = 0x8; + else + odt_tristate_code = 0x0; + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + + /* TODO + * Implement LRDIMM support + * See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 105 + */ + } else { + /* UDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 103 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm0 == 1) + odt_tristate_code = 0xe; + else + odt_tristate_code = 0xa; + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm0 == 1) + odt_tristate_code = 0xd; + else + odt_tristate_code = 0x5; + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) + odt_tristate_code = 0xc; + else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2)) + odt_tristate_code = 0x4; + else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1)) + odt_tristate_code = 0x8; + else + odt_tristate_code = 0x0; + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } + } else { + /* TODO + * Other socket support unimplemented + */ + } + + return odt_tristate_code; +} + +static uint8_t fam15h_cs_tristate_enable_code(struct DCTStatStruc *pDCTstat, uint8_t dct) +{ + uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); + + uint8_t package_type; + uint8_t cs_tristate_code = 0; + + package_type = mctGet_NVbits(NV_PACK_TYPE); + + /* Obtain number of DIMMs on channel */ + uint8_t dimm_count = pDCTstat->MAdimms[dct]; + uint8_t rank_count_dimm0; + uint8_t rank_count_dimm1; + + if (package_type == PT_GR) { + /* Socket G34 */ + if (pDCTstat->Status & (1 << SB_Registered)) { + /* RDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 104 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm0 < 4) + cs_tristate_code = 0xfc; + else + cs_tristate_code = 0xcc; + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm1 < 4) + cs_tristate_code = 0xf3; + else + cs_tristate_code = 0x33; + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + cs_tristate_code = 0xf0; + else if ((rank_count_dimm0 < 4) && (rank_count_dimm1 == 4)) + cs_tristate_code = 0x30; + else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 < 4)) + cs_tristate_code = 0xc0; + else + cs_tristate_code = 0x0; + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + + /* TODO + * Implement LRDIMM support + * See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 105 + */ + } else { + /* UDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 103 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm0 == 1) + cs_tristate_code = 0xfe; + else + cs_tristate_code = 0xfc; + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if (rank_count_dimm0 == 1) + cs_tristate_code = 0xfb; + else + cs_tristate_code = 0xf3; + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) + cs_tristate_code = 0xfa; + else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2)) + cs_tristate_code = 0xf2; + else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1)) + cs_tristate_code = 0xf8; + else + cs_tristate_code = 0xf0; + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } + } else { + /* TODO + * Other socket support unimplemented + */ + } + + return cs_tristate_code; +} + static void set_2t_configuration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { @@ -2315,20 +2533,16 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, if (memclk_index <= 0x6) { delay = 0x5; delay2 = 0x3; - } - else if (memclk_index == 0xa) { + } else if (memclk_index == 0xa) { delay = 0x6; delay2 = 0x3; - } - else if (memclk_index == 0xe) { + } else if (memclk_index == 0xe) { delay = 0x7; delay2 = 0x4; - } - else if (memclk_index == 0x12) { + } else if (memclk_index == 0x12) { delay = 0x8; delay2 = 0x4; - } - else if (memclk_index == 0x16) { + } else if (memclk_index == 0x16) { delay = 0xa; delay2 = 0x5; } @@ -3346,8 +3560,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, tCK16x = 40; else tCK16x = 48; - } - else { + } else { if (byte == 7) tCK16x = 20; else if (byte == 6) @@ -4674,13 +4887,13 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, else pDCTstat->RegMan1Present |= 1 << i; } - /* Get Control word values for RC3. We dont need it. */ + /* Get control word value for RC3 */ byte = pDCTstat->spd_data.spd_bytes[i][70]; - pDCTstat->CtrlWrd3 |= (byte >> 4) << (i << 2); /* C3 = SPD byte 70 [7:4] */ - /* Get Control word values for RC4, and RC5 */ + pDCTstat->CtrlWrd3 |= ((byte >> 4) & 0xf) << (i << 2); /* RC3 = SPD byte 70 [7:4] */ + /* Get control word values for RC4 and RC5 */ byte = pDCTstat->spd_data.spd_bytes[i][71]; - pDCTstat->CtrlWrd4 |= (byte & 0xFF) << (i << 2); /* RC4 = SPD byte 71 [3:0] */ - pDCTstat->CtrlWrd5 |= (byte >> 4) << (i << 2); /* RC5 = SPD byte 71 [7:4] */ + pDCTstat->CtrlWrd4 |= (byte & 0xf) << (i << 2); /* RC4 = SPD byte 71 [3:0] */ + pDCTstat->CtrlWrd5 |= ((byte >> 4) & 0xf) << (i << 2); /* RC5 = SPD byte 71 [7:4] */ } } } @@ -5866,23 +6079,27 @@ static void SetCSTriState(struct MCTStatStruc *pMCTstat, u32 val; u32 dev = pDCTstat->dev_dct; u32 index_reg = 0x98; - u32 index; u16 word; - /* Tri-state unused chipselects when motherboard - termination is available */ + if (is_fam15h()) { + word = fam15h_cs_tristate_enable_code(pDCTstat, dct); + } else { + /* Tri-state unused chipselects when motherboard + termination is available */ - /* FIXME: skip for Ax */ + /* FIXME: skip for Ax */ - word = pDCTstat->CSPresent; - if (pDCTstat->Status & (1 << SB_Registered)) { - word |= (word & 0x55) << 1; + word = pDCTstat->CSPresent; + if (pDCTstat->Status & (1 << SB_Registered)) { + word |= (word & 0x55) << 1; + } + word = (~word) & 0xff; } - word = (~word) & 0xFF; - index = 0x0c; - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); + + val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); + val &= ~0xff; val |= word; - Set_NB32_index_wait_DCT(dev, dct, index_reg, index, val); + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, val); } static void SetCKETriState(struct MCTStatStruc *pMCTstat, @@ -5891,7 +6108,6 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat, u32 val; u32 dev; u32 index_reg = 0x98; - u32 index; u16 word; /* Tri-state unused CKEs when motherboard termination is available */ @@ -5901,15 +6117,13 @@ static void SetCKETriState(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; word = pDCTstat->CSPresent; - index = 0x0c; - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); + val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); + val &= ~(0x3 << 12); if ((word & 0x55) == 0) val |= 1 << 12; - - if ((word & 0xAA) == 0) + if ((word & 0xaa) == 0) val |= 1 << 13; - - Set_NB32_index_wait_DCT(dev, dct, index_reg, index, val); + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, val); } static void SetODTTriState(struct MCTStatStruc *pMCTstat, @@ -5919,42 +6133,44 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat, u32 dev; u32 index_reg = 0x98; u8 cs; - u32 index; u8 odt; u8 max_dimms; - /* FIXME: skip for Ax */ - dev = pDCTstat->dev_dct; - /* Tri-state unused ODTs when motherboard termination is available */ - max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS); - odt = 0x0F; /* ODT tri-state setting */ - - if (pDCTstat->Status & (1 <<SB_Registered)) { - for (cs = 0; cs < 8; cs += 2) { - if (pDCTstat->CSPresent & (1 << cs)) { - odt &= ~(1 << (cs / 2)); - if (mctGet_NVbits(NV_4RANKType) != 0) { /* quad-rank capable platform */ - if (pDCTstat->CSPresent & (1 << (cs + 1))) - odt &= ~(4 << (cs / 2)); + if (is_fam15h()) { + odt = fam15h_odt_tristate_enable_code(pDCTstat, dct); + } else { + /* FIXME: skip for Ax */ + + /* Tri-state unused ODTs when motherboard termination is available */ + max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS); + odt = 0x0f; /* ODT tri-state setting */ + + if (pDCTstat->Status & (1 <<SB_Registered)) { + for (cs = 0; cs < 8; cs += 2) { + if (pDCTstat->CSPresent & (1 << cs)) { + odt &= ~(1 << (cs / 2)); + if (mctGet_NVbits(NV_4RANKType) != 0) { /* quad-rank capable platform */ + if (pDCTstat->CSPresent & (1 << (cs + 1))) + odt &= ~(4 << (cs / 2)); + } } } + } else { /* AM3 package */ + val = ~(pDCTstat->CSPresent); + odt = val & 9; /* swap bits 1 and 2 */ + if (val & (1 << 1)) + odt |= 1 << 2; + if (val & (1 << 2)) + odt |= 1 << 1; } - } else { /* AM3 package */ - val = ~(pDCTstat->CSPresent); - odt = val & 9; /* swap bits 1 and 2 */ - if (val & (1 << 1)) - odt |= 1 << 2; - if (val & (1 << 2)) - odt |= 1 << 1; } - index = 0x0C; - val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index); - val |= ((odt & 0xFF) << 8); /* set bits 11:8 ODTTriState[3:0] */ - Set_NB32_index_wait_DCT(dev, dct, index_reg, index, val); - + val = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c); + val &= ~(0xf << 8); /* ODTTri = odt */ + val |= (odt & 0xf) << 8; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0000000c, val); } /* Family 15h */ @@ -6524,7 +6740,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, dword |= (read_odt_delay & 0xf); Set_NB32_DCT(dev, dct, 0x240, dword); - printk(BIOS_SPEW, "Programmed ODT pattern %08x %08x %08x %08x\n", odt_pattern_0, odt_pattern_1, odt_pattern_2, odt_pattern_3); + printk(BIOS_SPEW, "Programmed DCT %d ODT pattern %08x %08x %08x %08x\n", dct, odt_pattern_0, odt_pattern_1, odt_pattern_2, odt_pattern_3); } else if (pDCTstat->LogicalCPUID & AMD_DR_Dx) { if (pDCTstat->Speed == 3) dword = 0x00000800; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index b72b9da..5f72ff3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -578,7 +578,7 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t NbPstateThreshold; uint8_t NbPstateHi; -/* New for LB Support */ + /* New for LB Support */ u8 NodePresent; u32 dev_host; u32 dev_map; @@ -588,9 +588,9 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_nbctl; u8 TargetFreq; u8 TargetCASL; - u8 CtrlWrd3; - u8 CtrlWrd4; - u8 CtrlWrd5; + uint32_t CtrlWrd3; + uint32_t CtrlWrd4; + uint32_t CtrlWrd5; u8 DqsRdWrPos_Saved; u8 DqsRcvEnGrossMax; u8 DqsRcvEnGrossMin; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index abb84ae..4cc87de 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1017,7 +1017,7 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, pDCTstat->CH_MaxRdLat[dct] = n - 1; #if DQS_TRAIN_DEBUG > 0 - printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]); + printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]); #endif } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index a63fe2e..4455391 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -static uint8_t fam15h_rdimm_rc2_control_code(struct DCTStatStruc *pDCTstat, uint8_t dct) +static uint8_t fam15h_rdimm_rc2_ibt_code(struct DCTStatStruc *pDCTstat, uint8_t dct) { uint8_t MaxDimmsInstallable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); @@ -157,7 +157,7 @@ static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat, val = 0xc; /* if single rank, set DBA1 and DBA0 */ } else if (CtrlWordNum == 2) { if (is_fam15h()) { - val = fam15h_rdimm_rc2_control_code(pDCTstat, dct); + val = (fam15h_rdimm_rc2_ibt_code(pDCTstat, dct) & 0x1) << 2; } else { if (package_type == PT_GR) { /* Socket G34 */ @@ -174,10 +174,14 @@ static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat, } else if (CtrlWordNum == 5) { val = (pDCTstat->CtrlWrd5 >> (DimmNum << 2)) & 0xff; } else if (CtrlWordNum == 8) { - if (package_type == PT_GR) { - /* Socket G34 */ - if (MaxDimmsInstallable == 2) { - val = 0x0; + if (is_fam15h()) { + val = (fam15h_rdimm_rc2_ibt_code(pDCTstat, dct) & 0xe) >> 1; + } else { + if (package_type == PT_GR) { + /* Socket G34 */ + if (MaxDimmsInstallable == 2) { + val = 0x0; + } } } } else if (CtrlWordNum == 9) { @@ -229,7 +233,11 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, mct_Wait(1200); - for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) { + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; + if (pDCTstat->GangedMode & 1) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + + for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel += 2) { if (pDCTstat->CSPresent & (1 << MrsChipSel)) { val = Get_NB32_DCT(dev, dct, 0xa8); val &= ~(0xff << 8); @@ -272,6 +280,10 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, u32 val; uint16_t mem_freq; + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; + if (pDCTstat->GangedMode & 1) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + pDCTstat->DIMMAutoSpeed = pDCTstat->TargetFreq; mem_freq = memclk_to_freq(pDCTstat->TargetFreq); for (MrsChipSel=0; MrsChipSel < 8; MrsChipSel++, MrsChipSel++) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index c1bb89e..143290f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -841,6 +841,10 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, */ } + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; + if (pDCTstat->GangedMode & 1) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + /* The following steps are performed once for unbuffered DIMMs and once for each * chip select on registered DIMMs: */ for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel++) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 5deaca5..f5bf9e3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -921,7 +921,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, * OUT * ---------------------------------------------------------------------------- */ -void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, u8 dimm) +void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm) { sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; @@ -929,6 +929,10 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui u8 WrLvOdt1=0; if (is_fam15h()) { + /* On Family15h processors, the value for the specific CS being targetted + * is taken from F2x238 / F2x23C as appropriate, then loaded into F2x9C_x0000_0008 + */ + /* Convert DIMM number to CS */ uint32_t dword; uint8_t cs; @@ -963,7 +967,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui set_DCT_ADDR_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT, DRAM_ADD_DCT_PHY_CONTROL_REG, 8, 11, (u32)WrLvOdt1); - printk(BIOS_SPEW, "Programmed DCT %d write levelling ODT pattern %08x\n", dct, WrLvOdt1); + printk(BIOS_SPEW, "Programmed DCT %d write levelling ODT pattern %08x from DIMM %d data\n", dct, WrLvOdt1, dimm); }

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Patch merged into coreboot/master: build system: add dependencies for SeaBIOS output
by gerrit＠coreboot.org 30 Nov '15

30 Nov '15

the following patch was just integrated into master: commit 4013469c507847d48e891c16b92f4556a2f6b76f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Nov 30 20:00:33 2015 +0100 build system: add dependencies for SeaBIOS output Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/12577 Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12577 for details. -gerrit

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New patch to review for coreboot: build system: add dependencies for SeaBIOS output
by Patrick Georgi 30 Nov '15

30 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12577 -gerrit commit 44228787f8d2c83cc2bfecd0b165736671674ff9 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Nov 30 20:00:33 2015 +0100 build system: add dependencies for SeaBIOS output Change-Id: I7b9f1574f6d487c0a6e5c9095c25ee973a96fa89 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/external/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index eedee05..26bb52e 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -56,6 +56,9 @@ seabios: CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) +payloads/external/SeaBIOS/seabios/out/vgabios.bin: seabios +payloads/external/SeaBIOS/seabios/out/bios.bin.elf: seabios + filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ HOSTCC="$(HOSTCC)" \

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coreboot-gerrit November 2015