coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: northbridge/amd/amdfam10: Add ability to set maximum P-state limit
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11985 -gerrit commit 994c2962087c1b42697b0c7cef61bc1fb8fb1587 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 00:35:05 2015 -0500 northbridge/amd/amdfam10: Add ability to set maximum P-state limit Under specific circumstances, for instance in low power or fanless machines, it may be useful to cap the maximum P-state of the CPU. Allow the maximum CPU P-state to be set via an NVRAM option. Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 24c422d..847b599 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -120,16 +120,32 @@ static void mcf3_set_resources(device_t dev) static void misc_control_init(struct device *dev) { - u32 cmd; + uint32_t dword; + uint8_t nvram; + uint8_t boost_limit; + uint8_t current_boost; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ - cmd = pci_read_config32(dev, 0x44); - cmd |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, cmd ); + dword = pci_read_config32(dev, 0x44); + dword |= (1<<6) | (1<<25); + pci_write_config32(dev, 0x44, dword); + + boost_limit = 0xf; + if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS) + boost_limit = nvram & 0xf; + + /* Set P-state maximum value */ + dword = pci_read_config32(dev, 0xdc); + current_boost = (dword >> 8) & 0x7; + if (boost_limit > current_boost) + boost_limit = current_boost; + dword &= ~(0x7 << 8); + dword |= (boost_limit & 0x7) << 8; + pci_write_config32(dev, 0xdc, dword); printk(BIOS_DEBUG, "done.\n"); }

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Patch set updated for coreboot: src/northbridge/amd/amdmct: Add option to override bad SPD checksum
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11987 -gerrit commit bbbcb33fda86e0147a536bb0ecd5bbfa48d962c1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 11 16:14:15 2015 -0500 src/northbridge/amd/amdmct: Add option to override bad SPD checksum Certain DIMMs, for example DIMMs on which the EEPROM has been modified by the end user, may not contain a valid SPD checksum. While this is not a normal condition, it may be useful to allow a checksum override while memory timing parameters are being altered, e.g. in the course of overclocking or underclocking, or when recovering from a bad SPD write. This is an advanced level feature primarily useful for debugging and development. Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 6 +++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 +++-- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 0b87c91..3473bc9 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -8,6 +8,7 @@ nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 minimum_memory_voltage = 1.5V +dimm_spd_checksum = Enforce ECC_memory = Enable ECC_redirection = Enable ecc_scrub_rate = 1.28us diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 19c7e7d..0bc6db8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -42,7 +42,8 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 4 h 0 maximum_p_state_limit -473 1 r 0 allow_spd_nvram_cache_restore +472 2 e 13 dimm_spd_checksum +474 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum @@ -137,6 +138,9 @@ enumerations 12 1 1.35V 12 2 1.25V 12 3 1.15V +13 0 Enforce +13 1 Ignore +13 2 Override checksums diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2841b18..4bfb08a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1456,7 +1456,7 @@ restartinit: } } if (NodesWmem == 0) { - printk(BIOS_DEBUG, "No Nodes?!\n"); + printk(BIOS_ALERT, "Unable to detect valid memory on any nodes. Halting!\n"); goto fatalexit; } @@ -3892,13 +3892,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, read_spd_bytes(pMCTstat, pDCTstat, i); crc_status = crcCheck(pDCTstat, i); } - if (crc_status) { /* CRC is OK */ + if ((crc_status) || (SPDCtrl == 2)) { /* CRC is OK */ byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ pDCTstat->DIMMValid |= 1 << i; } } else { + printk(BIOS_WARNING, "Node %d DIMM %d: SPD checksum invalid\n", pDCTstat->Node_ID, i); pDCTstat->DIMMSPDCSE = 1 << i; if (SPDCtrl == 0) { pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index a030f71..95d57fc 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -146,6 +146,14 @@ static u16 mctGet_NVbits(u8 index) case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */ + //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */ + + if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) + val = nvram & 0x3; + + if (val > 2) + val = 2; + break; case NV_DQSTrainCTL: //val = 0; /*Skip dqs training */

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Patch set updated for coreboot: northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11986 -gerrit commit fca10fe6dec95fe02708ae6234f695424e1ccb65 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 10:46:17 2015 -0500 northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2d8ab34..2841b18 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -4134,7 +4134,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); - if (load_spd_hashes_from_nvram(pDCTstat) < 0) { + if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; } else { @@ -4149,6 +4149,13 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) + allow_config_restore = 0; +#else + allow_config_restore = 0; +#endif + if (!allow_config_restore) pDCTstat->spd_data.nvram_spd_match = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 196d96d..425f1ef 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -297,6 +297,7 @@ struct MCTStatStruc { u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ uint32_t TSCFreq; + uint16_t nvram_checksum; } __attribute__((packed)); /*============================================================================= @@ -792,6 +793,7 @@ struct amd_s3_persistent_node_data { struct amd_s3_persistent_data { struct amd_s3_persistent_node_data node[MAX_NODES_SUPPORTED]; + uint16_t nvram_checksum; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 0a508cb..6e92f3a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -139,6 +139,36 @@ void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) *spd_hash = *spd_hash ^ (*spd_hash << 37); } +uint16_t calculate_nvram_mct_hash(void) +{ + uint32_t nvram; + uint16_t ret; + + ret = 0; + if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) + ret |= nvram & 0xf; + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) + ret |= (nvram & 0x3) << 4; + if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) + ret |= (nvram & 0x1) << 6; + if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) + ret |= (nvram & 0x1) << 7; + if (get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) + ret |= (nvram & 0x1) << 8; + if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) + ret |= (nvram & 0x1) << 9; + if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) + ret |= (nvram & 0x1) << 10; + if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) + ret |= (nvram & 0x1) << 11; + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + ret |= (nvram & 0x1) << 12; + if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) + ret |= (nvram & 0x1) << 13; + + return ret; +} + static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) { ssize_t s3nv_offset; @@ -169,7 +199,7 @@ static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) } #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { struct amd_s3_persistent_data *persistent_data; @@ -180,6 +210,8 @@ int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); + pMCTstat->nvram_checksum = persistent_data->nvram_checksum; + return 0; } #endif @@ -233,6 +265,8 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + persistent_data->nvram_checksum = calculate_nvram_mct_hash(); + if (restored) { if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) *restored = 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 56e627e..8a72695 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -17,9 +17,10 @@ #include "mct_d.h" void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); +uint16_t calculate_nvram_mct_hash(void); #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat); +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); #endif #ifdef __RAMSTAGE__

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit c7e4c27c3b6cecfcfd36dfc8c077357118215523 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 18:26:52 2015 -0600 mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12400 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12400 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 45de61de8bb5ef15a900415a482449cfde019549 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 8 19:54:56 2015 -0500 northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11980 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See http://review.coreboot.org/11980 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd: Add CC6 support
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 83abd81c8acb3a53dfc125e248d9e5fd58f3e0f7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 8 19:35:06 2015 -0500 cpu/amd: Add CC6 support This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11979 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/11979 for details. -gerrit

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Patch merged into coreboot/master: via/cx700: Fix hidden compile error and make sure it won't hide again
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit dd4390b6e055ef862084a5fc45b756d6fe09151d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Oct 31 16:12:51 2015 +0100 via/cx700: Fix hidden compile error and make sure it won't hide again A wrong function name made an #ifdef'd code path not compile. Fix that, and also use IS_ENABLED() to make sure that such issues won't come up again there. Change-Id: Iccb98842dde498cce32cd86a770e22a506ad4cc2 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/12296 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12296 for details. -gerrit

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Patch merged into coreboot/master: asus/k8v-x: Add more subsystem IDs to device tree
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit b31017b3ac13913cca1793b5fc50b041713ff186 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:36:31 2015 +0200 asus/k8v-x: Add more subsystem IDs to device tree This is an attempt at better compatibility with driver matching etc. Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Reviewed-on: http://review.coreboot.org/12351 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12351 for details. -gerrit

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Patch merged into coreboot/master: asus/k8v-x: Add PIRQ tables to init PCI IRQ config
by gerrit＠coreboot.org 11 Nov '15

11 Nov '15

the following patch was just integrated into master: commit 406834717ace674fd1dfb8e48a7e5fcdccee79e3 Author: Urja Rannikko <urjaman(a)gmail.com> Date: Thu Nov 5 18:43:52 2015 +0200 asus/k8v-x: Add PIRQ tables to init PCI IRQ config Pulled getpir from the attic and used data provided by it to create the table a bit more programmatically and added the AGP slot so the video card is given an IRQ Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Reviewed-on: http://review.coreboot.org/12350 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12350 for details. -gerrit

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Patch set updated for coreboot: northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11980 -gerrit commit 39ed71e734191a9c4563283c1cff872a94e6f4e5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 8 19:54:56 2015 -0500 northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 +++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 21 +++++++++++++++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1d48070..2d8ab34 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1368,6 +1368,7 @@ restartinit: printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); if (restore_mct_information_from_nvram(0) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); + pMCTstat->GStatus |= 1 << GSB_ConfigRestored; #endif printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); @@ -2095,6 +2096,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, if (is_fam15h()) exit_training_mode_fam15(pMCTstat, pDCTstatA); + + pMCTstat->GStatus |= 1 << GSB_ConfigRestored; } /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 1ac7bbf..196d96d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -312,6 +312,7 @@ struct MCTStatStruc { #define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ #define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */ /* NOTE: This is a local bit used by memory code */ +#define GSB_ConfigRestored 18 /* Training configuration was restored from NVRAM */ /*=============================================================================== Local DCT Status structure (a structure for each DCT) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 8ed7e3c..0a508cb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -209,7 +209,7 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d return pci_read_config32(dev, reg); } -static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) +static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored) { uint8_t node; uint8_t dimm; @@ -232,6 +232,13 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (node = 0; node < MAX_NODES_SUPPORTED; node++) for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + + if (restored) { + if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) + *restored = 1; + else + *restored = 0; + } } void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) @@ -1030,6 +1037,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste int8_t save_mct_information_to_nvram(void) { uint8_t nvram; + uint8_t restored = 0; if (acpi_is_wakeup_s3()) return 0; @@ -1051,7 +1059,16 @@ int8_t save_mct_information_to_nvram(void) copy_mct_data_to_save_variable(persistent_data); /* Save RAM SPD data at the same time */ - copy_cbmem_spd_data_to_save_variable(persistent_data); + copy_cbmem_spd_data_to_save_variable(persistent_data, &restored); + + if (restored) { + /* Allow training bypass if DIMM configuration is unchanged on next boot */ + nvram = 1; + set_option("allow_spd_nvram_cache_restore", &nvram); + + printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n"); + return 0; + } /* Obtain CBFS file offset */ s3nv_offset = get_s3nv_file_offset();

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coreboot-gerrit November 2015