coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch set updated for coreboot: southbridge/amd/sb700: Add option to disable SATA ALPM
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11993 -gerrit commit f6d89833d4576011a1098bfb8dfd8a13cc6d12fb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 18 11:48:02 2015 -0500 southbridge/amd/sb700: Add option to disable SATA ALPM The AMD Register Programming Reference states that the user should have the option to disable Active Link Power Management for two reasons. First, some drives may not function correctly with the ALPM implementation of the SP5100, and second there are some situations where low latency access is more important than the power savings created by using ALPM. Allow the user to disable ALPM if desired. Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- src/southbridge/amd/sb700/sata.c | 12 ++++++++++++ 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 3473bc9..9994dad 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -18,6 +18,7 @@ interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable sata_ahci_mode = Enable +sata_alpm = Disable maximum_p_state_limit = 0xf ieee1394_controller = Enable power_on_after_fail = On diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 0bc6db8..21765e3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -41,9 +41,10 @@ entries 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode -468 4 h 0 maximum_p_state_limit -472 2 e 13 dimm_spd_checksum -474 1 r 0 allow_spd_nvram_cache_restore +468 1 e 1 sata_alpm +469 4 h 0 maximum_p_state_limit +473 2 e 13 dimm_spd_checksum +475 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index fdf32c7..c61fa01 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -104,6 +104,7 @@ static void sata_init(struct device *dev) int i, j; uint8_t nvram; uint8_t sata_ahci_mode; + uint8_t sata_alpm_enable; uint8_t port_count; uint8_t max_port_count; @@ -111,6 +112,10 @@ static void sata_init(struct device *dev) if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) sata_ahci_mode = !!nvram; + sata_alpm_enable = 0; + if (get_option(&nvram, "sata_alpm") == CB_SUCCESS) + sata_alpm_enable = !!nvram; + device_t sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -229,6 +234,13 @@ static void sata_init(struct device *dev) dword &= ~(0x1 << i); write32(sata_bar5 + 0x0c, dword); + /* Disable ALPM if ALPM support not requested */ + if (!sata_alpm_enable) { + dword = read32(sata_bar5 + 0xfc); + dword &= ~(0x1 << 11); /* Disable ALPM */ + write32(sata_bar5 + 0xfc, dword); + } + /* Write protect Sub-Class Code */ byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0);

1 0

Patch set updated for coreboot: northbridge/amd/amdmct: Fix crash on startup due to NULL pointer access
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11995 -gerrit commit 7a03dfe6f5dea171baf98b98a12f28edce7cc129 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 14:40:56 2015 -0500 northbridge/amd/amdmct: Fix crash on startup due to NULL pointer access Change-Id: I47089f2ad886a6fda4e0cd4472efd975bb8e06c5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 9196863..f49e973 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -349,11 +349,10 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) } for (i = 0; i < 2; i++) { - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i]; highest_rank_count[i] = 0x0; for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - if (pDCTData->DimmRanks[dimm] > highest_rank_count[i]) - highest_rank_count[i] = pDCTData->DimmRanks[dimm]; + if (pDCTstat->DimmRanks[dimm] > highest_rank_count[i]) + highest_rank_count[i] = pDCTstat->DimmRanks[dimm]; } } #endif

1 0

Patch set updated for coreboot: cpu/amd: Add CC6 support
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11979 -gerrit commit 8a103ae54afa0b672718c32517a435a9a27ffb93 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 8 19:35:06 2015 -0500 cpu/amd: Add CC6 support This patch adds CC6 power save support to the AMD Family 15h support code. As CC6 is a complex power saving state that relies heavily on CPU, northbridge, and southbridge cooperation, this patch alters significant amounts of code throughout the tree simultaneously. Allowing the CPU to enter CC6 allows the second level of turbo boost to be reached, and also provides significant power savings when the system is idle due to the complete core shutdown. Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/acpigen.c | 26 +++- src/arch/x86/include/arch/acpigen.h | 3 + src/cpu/amd/family_10h-family_15h/fidvid.c | 170 +++++++++++----------- src/cpu/amd/family_10h-family_15h/init_cpus.c | 81 +++++++++++ src/cpu/amd/family_10h-family_15h/powernow_acpi.c | 135 +++++++++++++++-- src/include/cpu/amd/powernow.h | 2 + src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 5 +- src/northbridge/amd/amdfam10/link_control.c | 81 ++++++++++- src/northbridge/amd/amdfam10/northbridge.c | 58 ++++---- src/northbridge/amd/amdht/AsPsDefs.h | 3 +- src/northbridge/amd/amdmct/amddefs.h | 66 +++++---- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 57 +++++--- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 8 + src/southbridge/amd/sb700/early_setup.c | 19 ++- src/southbridge/amd/sb700/fadt.c | 5 + src/southbridge/amd/sb700/sb700.h | 7 +- src/southbridge/amd/sb700/sm.c | 5 +- src/southbridge/amd/sb800/fadt.c | 5 + src/southbridge/amd/sb800/sb800.h | 8 +- 20 files changed, 544 insertions(+), 201 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index cac2f8c..c1a09f2 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> * * This program is free software; you can redistribute it and/or modify @@ -17,11 +18,11 @@ #define ACPIGEN_LENSTACK_SIZE 10 /* - * If you need to change this, change acpigen_write_f and + * If you need to change this, change acpigen_write_len_f and * acpigen_pop_len */ -#define ACPIGEN_MAXLEN 0xfff +#define ACPIGEN_MAXLEN 0xfffff #include <string.h> #include <arch/acpigen.h> @@ -39,6 +40,7 @@ void acpigen_write_len_f(void) len_stack[ltop++] = gencurrent; acpigen_emit_byte(0); acpigen_emit_byte(0); + acpigen_emit_byte(0); } void acpigen_pop_len(void) @@ -48,9 +50,10 @@ void acpigen_pop_len(void) char *p = len_stack[--ltop]; len = gencurrent - p; ASSERT(len <= ACPIGEN_MAXLEN) - /* generate store length for 0xfff max */ - p[0] = (0x40 | (len & 0xf)); + /* generate store length for 0xfffff max */ + p[0] = (0x80 | (len & 0xf)); p[1] = (len >> 4 & 0xff); + p[2] = (len >> 12 & 0xff); } @@ -479,6 +482,21 @@ void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) acpigen_pop_len(); } +void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index) +{ + acpigen_write_name("_CSD"); + acpigen_write_package(1); + acpigen_write_package(6); + acpigen_write_byte(6); // 6 values + acpigen_write_byte(0); // revision 0 + acpigen_write_dword(domain); + acpigen_write_dword(coordtype); + acpigen_write_dword(numprocs); + acpigen_write_dword(index); + acpigen_pop_len(); + acpigen_pop_len(); +} + void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 038ec3a..1ad021a 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,6 +52,8 @@ typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_CST_package_entry(acpi_cstate_t *cstate); void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); +typedef enum { CSD_HW_ALL=0xfe } CSD_coord; +void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index); void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 5eb7980..3af18bd 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -165,87 +165,87 @@ static void applyBoostFIDOffset(device_t dev, uint32_t nodeid) { } static void enableNbPState1( device_t dev ) { - uint64_t cpuRev = mctGetLogicalCPUID(0xFF); - if (cpuRev & AMD_FAM10_C3) { - u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); - if ( nbPState){ - u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; - u32 i; - for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_EN_MASK ) { - msr.hi |= NB_DID_M_ON; - msr.lo &= NB_VID_MASK_OFF; - msr.lo |= ( nbVid1 << NB_VID_POS); - wrmsr(PS_REG_BASE + i, msr); - } - } - } - } + uint64_t cpuRev = mctGetLogicalCPUID(0xFF); + if (cpuRev & AMD_FAM10_C3) { + u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); + if ( nbPState){ + u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; + u32 i; + for (i = nbPState; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; + msr.lo |= ( nbVid1 << NB_VID_POS); + wrmsr(PS_REG_BASE + i, msr); + } + } + } + } } -static u8 setPStateMaxVal( device_t dev ) { - u8 i,maxpstate=0; - for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_IDD_VALUE_MASK) { - msr.hi |= PS_EN_MASK ; - wrmsr(PS_REG_BASE + i, msr); - } - if (msr.hi & PS_EN_MASK) { - maxpstate = i; - } - } - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u32 reg = pci_read_config32(dev, CPTC2); - reg &= PS_MAX_VAL_MASK; - reg |= (maxpstate << PS_MAX_VAL_POS); - pci_write_config32(dev, CPTC2,reg); - return maxpstate; +static u8 setPStateMaxVal(device_t dev) { + u8 i, maxpstate=0; + for (i = 0; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_IDD_VALUE_MASK) { + msr.hi |= PS_EN_MASK ; + wrmsr(PS_REG_BASE + i, msr); + } + if (msr.hi & PS_EN_MASK) { + maxpstate = i; + } + } + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u32 reg = pci_read_config32(dev, CPTC2); + reg &= PS_MAX_VAL_MASK; + reg |= (maxpstate << PS_MAX_VAL_POS); + pci_write_config32(dev, CPTC2,reg); + return maxpstate; } static void dualPlaneOnly( device_t dev ) { - // BKDG 2.4.2.7 - - uint64_t cpuRev = mctGetLogicalCPUID(0xFF); - if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) - && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E - if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) - && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){ - if (cpuid_edx(0x80000007) & CPB_MASK) { - // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(0xC0010065); - wrmsr(0xC0010065, rdmsr(0xC0010068) ); - wrmsr(0xC0010068,minPstate); - } else { - msr_t msr; - msr.lo=0; msr.hi=0; - wrmsr(0xC0010064, rdmsr(0xC0010068) ); - wrmsr(0xC0010068, msr ); - } - - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u8 maxpstate = setPStateMaxVal(dev); - - u32 reg = pci_read_config32(dev, HTC_REG); - reg &= HTC_PS_LMT_MASK; - reg |= (maxpstate << PS_LIMIT_POS); - pci_write_config32(dev, HTC_REG,reg); - - } - } + // BKDG 2.4.2.7 + + uint64_t cpuRev = mctGetLogicalCPUID(0xFF); + if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) + && (cpuRev & (AMD_DR_Cx | AMD_DR_Ex))) { + if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) + && (pci_read_config32(dev, 0xA0) & PVI_MODE)) { + if (cpuid_edx(0x80000007) & CPB_MASK) { + // revision E only, but E is apparently not supported yet, therefore untested + msr_t minPstate = rdmsr(0xC0010065); + wrmsr(0xC0010065, rdmsr(0xC0010068)); + wrmsr(0xC0010068, minPstate); + } else { + msr_t msr; + msr.lo=0; msr.hi=0; + wrmsr(0xC0010064, rdmsr(0xC0010068) ); + wrmsr(0xC0010068, msr); + } + + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u8 maxpstate = setPStateMaxVal(dev); + + u32 reg = pci_read_config32(dev, HTC_REG); + reg &= HTC_PS_LMT_MASK; + reg |= (maxpstate << PS_LIMIT_POS); + pci_write_config32(dev, HTC_REG,reg); + } + } } static int vidTo100uV(u8 vid) -{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV - // BKDG #31116 rev 3.48 2.4.1.6 - int voltage; - if (vid >= 0x7c) { - voltage = 0; - } else { - voltage = (15500 - (125*vid)); - } - return voltage; +{ + // returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV + // BKDG #31116 rev 3.48 2.4.1.6 + int voltage; + if (vid >= 0x7c) { + voltage = 0; + } else { + voltage = (15500 - (125*vid)); + } + return voltage; } static void setVSRamp(device_t dev) { @@ -344,7 +344,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) } /* Get AltVID */ - dtemp = pci_read_config32(dev, 0xDC); + dtemp = pci_read_config32(dev, 0xdc); bValue = (u8) (dtemp & BIT_MASK_7); /* Use the VID with the lowest voltage (higher VID) */ @@ -508,15 +508,15 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { values (min latency) */ u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; u8 nbSynPtrAdj; - if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) - || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { - nbSynPtrAdj = 5; + if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL) ) + || ((cpuRev & AMD_RB_C3) && (nbPstate != 0))) { + nbSynPtrAdj = 5; } else { - nbSynPtrAdj = 6; + nbSynPtrAdj = 6; } - u32 dword = pci_read_config32(dev, 0xDc); - dword &= ~ NB_SYN_PTR_ADJ_MASK; + u32 dword = pci_read_config32(dev, 0xdc); + dword &= ~NB_SYN_PTR_ADJ_MASK; dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); @@ -548,7 +548,7 @@ static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg } } else { // rev C or later // same doubt as cache scrubbing: ok to check current state ? - dword = pci_read_config32(dev, 0xDC); + dword = pci_read_config32(dev, 0xdc); u32 cacheFlushOnHalt = dword & (7 << 16); if (!cacheFlushOnHalt) { c1 = 0x80; @@ -619,11 +619,11 @@ static void prep_fid_change(void) printk(BIOS_DEBUG, " F3x80: %08x\n", dword); dword = pci_read_config32(dev, 0x84); printk(BIOS_DEBUG, " F3x84: %08x\n", dword); - dword = pci_read_config32(dev, 0xD4); + dword = pci_read_config32(dev, 0xd4); printk(BIOS_DEBUG, " F3xD4: %08x\n", dword); - dword = pci_read_config32(dev, 0xD8); + dword = pci_read_config32(dev, 0xd8); printk(BIOS_DEBUG, " F3xD8: %08x\n", dword); - dword = pci_read_config32(dev, 0xDC); + dword = pci_read_config32(dev, 0xdc); printk(BIOS_DEBUG, " F3xDC: %08x\n", dword); } } @@ -752,7 +752,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) * synchronization between cores and we don't think * PstatMaxVal is going to be 0 on cold reset anyway ? */ - if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { + if (!(pci_read_config32(dev, 0xdc) & (~PS_MAX_VAL_MASK))) { printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); }; diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 85eb931..c9dca76 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -26,6 +26,14 @@ #include <northbridge/amd/amdfam10/raminit_amdmct.c> #include <reset.h> +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) +#include <southbridge/amd/sb700/sb700.h> +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) +#include <southbridge/amd/sb800/sb800.h> +#endif + #if IS_ENABLED(CONFIG_SET_FIDVID) static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); @@ -870,6 +878,7 @@ void cpuSetAMDMSR(uint8_t node_id) u8 i; u32 platform; uint64_t revision; + uint8_t enable_c_states; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -932,6 +941,44 @@ void cpuSetAMDMSR(uint8_t node_id) wrmsr(FP_CFG, msr); } +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) + uint8_t nvram; + + if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { + /* Set up message triggered C1E */ + msr = rdmsr(0xc0010055); + msr.lo &= ~0xffff; /* IOMsgAddr = ACPI_PM_EVT_BLK */ + msr.lo |= ACPI_PM_EVT_BLK & 0xffff; + msr.lo |= (0x1 << 29); /* BmStsClrOnHltEn = 1 */ + if (revision & AMD_DR_GT_D0) { + msr.lo &= ~(0x1 << 28); /* C1eOnCmpHalt = 0 */ + msr.lo &= ~(0x1 << 27); /* SmiOnCmpHalt = 0 */ + } + wrmsr(0xc0010055, msr); + + msr = rdmsr(0xc0010015); + msr.lo |= (0x1 << 12); /* HltXSpCycEn = 1 */ + wrmsr(0xc0010015, msr); + } + + if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) { + enable_c_states = 0; + if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + enable_c_states = !!nvram; + + if (enable_c_states) { + /* Set up the C-state base address */ + msr_t c_state_addr_msr; + c_state_addr_msr = rdmsr(0xc0010073); + c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */ + wrmsr(0xc0010073, c_state_addr_msr); + } + } +#else + enable_c_states = 0; +#endif + printk(BIOS_DEBUG, " done\n"); } @@ -946,6 +993,7 @@ static void cpuSetAMDPCI(u8 node) u32 platform; u32 val; u8 offset; + uint32_t dword; uint64_t revision; printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node); @@ -1004,6 +1052,39 @@ static void cpuSetAMDPCI(u8 node) if (revision & (AMD_DR_B2 | AMD_DR_B3)) dctPhyDiag(); */ + if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { + /* Set up message triggered C1E */ + dword = pci_read_config32(NODE_PCI(node, 3), 0xd4); + dword &= ~(0x1 << 14); /* CacheFlushImmOnAllHalt = !is_fam15h() */ + dword |= (is_fam15h()?0:1) << 14; + pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0xdc); + dword |= 0x1 << 26; /* IgnCpuPrbEn = 1 */ + dword &= ~(0x7f << 19); /* CacheFlushOnHaltTmr = 0x28 */ + dword |= 0x28 << 19; + dword |= 0x7 << 16; /* CacheFlushOnHaltCtl = 0x7 */ + pci_write_config32(NODE_PCI(node, 3), 0xdc, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0xa0); + dword |= 0x1 << 10; /* IdleExitEn = 1 */ + pci_write_config32(NODE_PCI(node, 3), 0xa0, dword); + + if (revision & AMD_DR_GT_D0) { + dword = pci_read_config32(NODE_PCI(node, 3), 0x188); + dword |= 0x1 << 4; /* EnStpGntOnFlushMaskWakeup = 1 */ + pci_write_config32(NODE_PCI(node, 3), 0x188, dword); + } else { + dword = pci_read_config32(NODE_PCI(node, 4), 0x128); + dword &= ~(0x1 << 31); /* CstateMsgDis = 0 */ + pci_write_config32(NODE_PCI(node, 4), 0x128, dword); + } + + dword = pci_read_config32(NODE_PCI(node, 3), 0xd4); + dword |= 0x1 << 13; /* MTC1eEn = 1 */ + pci_write_config32(NODE_PCI(node, 3), 0xd4, dword); + } + printk(BIOS_DEBUG, " done\n"); } diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c index 0c53e86..a7cc9da 100644 --- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c +++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <stdint.h> +#include <option.h> #include <cpu/x86/msr.h> #include <arch/acpigen.h> #include <cpu/amd/powernow.h> @@ -30,21 +31,29 @@ #include <northbridge/amd/amdmct/mct/mct.h> #include <northbridge/amd/amdmct/amddefs.h> +static inline uint8_t is_fam15h(void) +{ + uint8_t fam15h = 0; + uint32_t family; + + family = cpuid_eax(0x80000001); + family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8); + + if (family >= 0x6f) + /* Family 15h or later */ + fam15h = 1; + + return fam15h; +} + static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_power, u32 *pstate_latency, u32 *pstate_control, u32 *pstate_status, int coreID, - u32 pcontrol_blk, u8 plen, u8 onlyBSP, uint8_t single_link) { int i; struct cpuid_result cpuid1; - if ((onlyBSP) && (coreID != 0)) { - plen = 0; - pcontrol_blk = 0; - } - - acpigen_write_processor(coreID, pcontrol_blk, plen); acpigen_write_empty_PCT(); acpigen_write_name("_PSS"); @@ -88,9 +97,62 @@ static void write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u32 *pstate_p if (cpu) acpigen_write_PSD_package(cpu->path.apic.apic_id, 1, SW_ANY); } +} - /* patch the whole Processor token length */ - acpigen_pop_len(); +static void write_cstates_for_core(int coreID) +{ + /* Generate C state entries */ + uint8_t cstate_count = 1; + acpi_cstate_t cstate; + + if (is_fam15h()) { + cstate.ctype = 2; + cstate.latency = 100; + cstate.power = 0; + cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; + cstate.resource.bit_width = 8; + cstate.resource.bit_offset = 0; + cstate.resource.addrl = rdmsr(0xc0010073).lo + 1; + cstate.resource.addrh = 0; + cstate.resource.resv = 1; + } else { + cstate.ctype = 2; + cstate.latency = 75; + cstate.power = 0; + cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO; + cstate.resource.bit_width = 8; + cstate.resource.bit_offset = 0; + cstate.resource.addrl = rdmsr(0xc0010073).lo; + cstate.resource.addrh = 0; + cstate.resource.resv = 1; + } + + acpigen_write_CST_package(&cstate, cstate_count); + + /* Find the local APIC ID for the specified core ID */ + if (is_fam15h()) { + struct device* cpu; + int cpu_index = 0; + for (cpu = all_devices; cpu; cpu = cpu->next) { + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) + continue; + if (!cpu->enabled) + continue; + if (cpu_index == coreID) + break; + cpu_index++; + } + + if (cpu) { + /* TODO + * Detect dual core status and skip CSD generation if dual core is disabled + */ + + /* Generate C state dependency entries */ + acpigen_write_CSD_package((cpu->path.apic.apic_id >> 1) & 0x7f, 2, CSD_HW_ALL, 0); + } + } } /* @@ -121,6 +183,15 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) u8 index; msr_t msr; + uint8_t nvram; + uint8_t enable_c_states; + + enable_c_states = 0; +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + enable_c_states = !!nvram; +#endif + /* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */ cpuid1 = cpuid(0x80000002); v = (u32 *) processor_brand; @@ -196,6 +267,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) return; } + if (fam15h) + /* Set P_LVL2 P_BLK entry */ + *(((uint8_t *)pcontrol_blk) + 0x04) = (rdmsr(0xc0010073).lo + 1) & 0xff; + uint8_t pviModeFlag; uint8_t Pstate_max; uint8_t cpufid; @@ -314,18 +389,56 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_latency[index]); } + /* Enter processor block scope */ char pscope[] = "\\_PR"; - acpigen_write_scope(pscope); + for (index = 0; index < total_core_count; index++) { /* Determine if this is a single-link processor */ node_index = 0x18 + (index / cores_per_node); dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80); single_link = !!(((dtemp & 0xff00) >> 8) == 0); + /* Enter processor core scope */ + uint8_t plen_cur = plen; + uint32_t pcontrol_blk_cur = pcontrol_blk; + if ((onlyBSP) && (index != 0)) { + plen_cur = 0; + pcontrol_blk_cur = 0; + } + acpigen_write_processor(index, pcontrol_blk_cur, plen_cur); + + /* Write P-state status and dependency objects */ write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power, Pstate_latency, Pstate_control, Pstate_status, - index, pcontrol_blk, plen, onlyBSP, single_link); + index, single_link); + + /* Write C-state status and dependency objects */ + if (fam15h && enable_c_states) + write_cstates_for_core(index); + + /* Exit processor core scope */ + acpigen_pop_len(); } + + /* Exit processor block scope */ acpigen_pop_len(); } + +void amd_powernow_update_fadt(acpi_fadt_t * fadt) +{ + if (is_fam15h()) { + fadt->p_lvl2_lat = 101; /* NOTE: While the BKDG states this should + * be set to 100, there is no way to meet + * the other FADT requirements. I suspect + * there is an error in the BKDG for ACPI + * 1.x support; disable all FADT-based C + * states > 2... */ + fadt->p_lvl3_lat = 1001; + fadt->flags |= 0x1 << 2; /* FLAGS.PROC_C1 = 1 */ + fadt->flags |= 0x1 << 3; /* FLAGS.P_LVL2_UP = 1 */ + } else { + fadt->cst_cnt = 0; + } + fadt->pstate_cnt = 0; +} diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h index 5f749d0..fc1e863 100644 --- a/src/include/cpu/amd/powernow.h +++ b/src/include/cpu/amd/powernow.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,5 +18,6 @@ #define POWERNOW_H void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP); +void amd_powernow_update_fadt(acpi_fadt_t * fadt); #endif diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index b42541a..c841aa9 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -14,6 +14,7 @@ ecc_scrub_rate = 1.28us interleave_chip_selects = Enable interleave_nodes = Disable interleave_memory_channels = Enable +cpu_c_states = Enable cpu_cc6_state = Enable ieee1394_controller = Enable power_on_after_fail = On diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index fb6ea73..40799d5 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -38,8 +38,9 @@ entries 458 4 e 11 hypertransport_speed_limit 462 2 e 12 minimum_memory_voltage 464 1 e 2 compute_unit_siblings -465 1 e 1 cpu_cc6_state -466 1 r 0 allow_spd_nvram_cache_restore +465 1 e 1 cpu_c_states +466 1 e 1 cpu_cc6_state +467 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index 1091ef4..7fa9f12 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -49,15 +49,94 @@ static inline uint8_t is_fam15h(void) static void nb_control_init(struct device *dev) { + uint8_t enable_c_states; + uint8_t enable_cc6; uint32_t dword; printk(BIOS_DEBUG, "NB: Function 4 Link Control.. "); + /* Configure L3 Power Control */ + dword = pci_read_config32(dev, 0x1c4); + dword |= (0x1 << 8); /* L3PwrSavEn = 1 */ + pci_write_config32(dev, 0x1c4, dword); + if (is_fam15h()) { + /* Configure L3 Control 2 */ + dword = pci_read_config32(dev, 0x1cc); + dword &= ~(0x7 << 6); /* ImplRdProjDelayThresh = 0x2 */ + dword |= (0x2 << 6); + pci_write_config32(dev, 0x1cc, dword); + + /* Configure TDP Accumulator Divisor Control */ + dword = pci_read_config32(dev, 0x104); + dword &= ~(0xfff << 2); /* TdpAccDivRate = 0xc8 */ + dword |= (0xc8 << 2); + dword &= ~0x3; /* TdpAccDivVal = 0x1 */ + dword |= 0x1; + pci_write_config32(dev, 0x104, dword); + + /* Configure Sample and Residency Timers */ + dword = pci_read_config32(dev, 0x110); + dword &= ~0xfff; /* CSampleTimer = 0x1 */ + dword |= 0x1; + pci_write_config32(dev, 0x110, dword); + + /* Configure APM TDP Control */ + dword = pci_read_config32(dev, 0x16c); + dword |= (0x1 << 4); /* ApmTdpLimitIntEn = 1 */ + pci_write_config32(dev, 0x16c, dword); + /* Enable APM */ dword = pci_read_config32(dev, 0x15c); dword |= (0x1 << 7); /* ApmMasterEn = 1 */ pci_write_config32(dev, 0x15c, dword); + + enable_c_states = 0; + enable_cc6 = 0; +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + uint8_t nvram; + + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + enable_c_states = !!nvram; + + if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) + enable_cc6 = !!nvram; +#endif + + if (enable_c_states) { + /* Configure C-state Control 1 */ + dword = pci_read_config32(dev, 0x118); + dword |= (0x1 << 24); /* PwrGateEnCstAct1 = 1 */ + dword &= ~(0x7 << 21); /* ClkDivisorCstAct1 = 0x0 */ + dword &= ~(0x3 << 18); /* CacheFlushTmrSelCstAct1 = 0x1 */ + dword |= (0x1 << 18); + dword |= (0x1 << 17); /* CacheFlushEnCstAct1 = 1 */ + dword |= (0x1 << 16); /* CpuPrbEnCstAct1 = 1 */ + dword &= ~(0x1 << 8); /* PwrGateEnCstAct0 = 0 */ + dword &= ~(0x7 << 5); /* ClkDivisorCstAct0 = 0x0 */ + dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x2 */ + dword |= (0x2 << 2); + dword |= (0x1 << 1); /* CacheFlushEnCstAct0 = 1 */ + dword |= 0x1; /* CpuPrbEnCstAct0 = 1 */ + pci_write_config32(dev, 0x118, dword); + + /* Configure C-state Control 2 */ + dword = pci_read_config32(dev, 0x11c); + dword &= ~(0x1 << 8); /* PwrGateEnCstAct2 = 0 */ + dword &= ~(0x7 << 5); /* ClkDivisorCstAct2 = 0x0 */ + dword &= ~(0x3 << 2); /* CacheFlushTmrSelCstAct0 = 0x0 */ + dword &= ~(0x1 << 1); /* CacheFlushEnCstAct0 = 0 */ + dword &= ~(0x1); /* CpuPrbEnCstAct0 = 0 */ + pci_write_config32(dev, 0x11c, dword); + + /* Configure C-state Policy Control 1 */ + dword = pci_read_config32(dev, 0x128); + dword &= ~(0x7f << 5); /* CacheFlushTmr = 0x28 */ + dword |= (0x28 << 5); + dword &= ~0x1; /* CoreCstateMode = !enable_cc6 */ + dword |= ((enable_cc6)?0:1); + pci_write_config32(dev, 0x128, dword); + } } printk(BIOS_DEBUG, "done.\n"); @@ -83,4 +162,4 @@ static const struct pci_driver mcf4_driver_fam15 __pci_driver = { .ops = &mcf4_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1604, -}; \ No newline at end of file +}; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 116789c..0c1971b 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -766,53 +766,49 @@ static void amdfam10_domain_read_resources(device_t dev) uint8_t num_nodes; /* Find highest DRAM range (DramLimitAddr) */ + num_nodes = 0; max_node = 0; max_range = -1; interleaved = 0; max_range_limit = 0; - for (range = 0; range < 8; range++) { - dword = f1_read_config32(0x40 + (range * 0x8)); - if (!(dword & 0x3)) - continue; - - if ((dword >> 8) & 0x7) - interleaved = 1; - - dword = f1_read_config32(0x44 + (range * 0x8)); - dword2 = f1_read_config32(0x144 + (range * 0x8)); - qword = ((((uint64_t)dword) >> 16) & 0xffff) << 24; - qword |= (((uint64_t)dword2) & 0xff) << 40; - - if (qword > max_range_limit) { - max_range = range; - max_range_limit = qword; - max_node = dword & 0x7; - } - } - - num_nodes = 0; device_t node_dev; for (node = 0; node < FX_DEVS; node++) { node_dev = get_node_pci(node, 0); /* Test for node presence */ - if ((node_dev) && (pci_read_config32(node_dev, PCI_VENDOR_ID) != 0xffffffff)) - num_nodes++; + if ((!node_dev) || (pci_read_config32(node_dev, PCI_VENDOR_ID) == 0xffffffff)) + continue; + + num_nodes++; + for (range = 0; range < 8; range++) { + dword = pci_read_config32(get_node_pci(node, 1), 0x40 + (range * 0x8)); + if (!(dword & 0x3)) + continue; + + if ((dword >> 8) & 0x7) + interleaved = 1; + + dword = pci_read_config32(get_node_pci(node, 1), 0x44 + (range * 0x8)); + dword2 = pci_read_config32(get_node_pci(node, 1), 0x144 + (range * 0x8)); + qword = 0xffffff; + qword |= ((((uint64_t)dword) >> 16) & 0xffff) << 24; + qword |= (((uint64_t)dword2) & 0xff) << 40; + + if (qword > max_range_limit) { + max_range = range; + max_range_limit = qword; + max_node = dword & 0x7; + } + } } - /* Calculate CC6 sotrage area size */ + /* Calculate CC6 storage area size */ if (interleaved) qword = (0x1000000 * num_nodes); else qword = 0x1000000; /* Reserve the CC6 save segment */ - reserved_ram_resource(dev, 8, max_range_limit >> 10, qword >> 10); - - /* Set up the C-state base address */ - msr_t c_state_addr_msr; - c_state_addr_msr = rdmsr(0xc0010073); - c_state_addr_msr.lo = 0xe0e0; /* CstateAddr = 0xe0e0 */ - wrmsr(0xc0010073, c_state_addr_msr); + reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10); } } } diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 559c67d..d4e6a29 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -250,7 +251,7 @@ #define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */ -#define NM_PS_REG 5 /* number of P-state MSR registers */ +#define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */ /* sFidVidInit.outFlags defines */ #define PWR_CK_OK 0 /* System board check OK */ diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 42ad32b..d2dfbcc 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -49,32 +49,34 @@ /* * Groups - Create as many as you wish, from the above public values */ -#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) -#define AMD_NPT_F3 (AMD_NPT_F3L) -#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) -#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) -#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) -#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) -#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) -#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) -#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) -#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) -#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) -#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) -#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) -#define AMD_DR_ALL (AMD_DR_Bx) -#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) -#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) -#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) -#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) -#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) -#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) -#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) -#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) -#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) -#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) +#define AMD_NPT_F2 (AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K) +#define AMD_NPT_F3 (AMD_NPT_F3L) +#define AMD_NPT_Fx (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3) +#define AMD_NPT_Gx (AMD_NPT_G0A | AMD_NPT_G1B) +#define AMD_NPT_ALL (AMD_NPT_Fx | AMD_NPT_Gx) +#define AMD_FINEDELAY (AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2) +#define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) +#define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) +#define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) +#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) +#define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) +#define AMD_DR_Ex (AMD_PH_E0) +#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) +#define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) +#define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) +#define AMD_DR_GT_Bx (AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx)) +#define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex) +#define AMD_DR_ALL (AMD_DR_Bx) +#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) +#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) +#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) +#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1) +#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) +#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) +#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) +#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) #define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3) -#define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0) +#define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0) /* * Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE @@ -87,9 +89,9 @@ #define AMD_PTYPE_MC 0x020 /* Multi Core (>2) */ #define AMD_PTYPE_UMA 0x040 /* UMA required */ - /* - * Groups - Create as many as you wish, from the above public values - */ +/* + * Groups - Create as many as you wish, from the above public values + */ #define AMD_PTYPE_ALL 0xFFFFFFFF /* A mask for all */ @@ -98,11 +100,11 @@ */ #define HTPHY_LINKTYPE_HT3 0x00000001 #define HTPHY_LINKTYPE_HT1 0x00000002 -#define HTPHY_LINKTYPE_COHERENT 0x00000004 +#define HTPHY_LINKTYPE_COHERENT 0x00000004 #define HTPHY_LINKTYPE_NONCOHERENT 0x00000008 #define HTPHY_LINKTYPE_CONNECTED (HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT) #define HTPHY_LINKTYPE_GANGED 0x00000010 -#define HTPHY_LINKTYPE_UNGANGED 0x00000020 +#define HTPHY_LINKTYPE_UNGANGED 0x00000020 #define HTPHY_LINKTYPE_ALL 0x7FFFFFFF @@ -110,7 +112,7 @@ * CPU HT PHY REGISTERS, FIELDS, AND MASKS */ #define HTPHY_OFFSET_MASK 0xE00001FF -#define HTPHY_WRITE_CMD 0x40000000 +#define HTPHY_WRITE_CMD 0x40000000 #define HTPHY_IS_COMPLETE_MASK 0x80000000 #define HTPHY_DIRECT_MAP 0x20000000 #define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF @@ -158,4 +160,4 @@ #define AMD_PKGTYPE_S1gX 2 #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 -#define AMD_PKGTYPE_C32 5 +#define AMD_PKGTYPE_C32 5 \ No newline at end of file diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 27fa7ae..1d48070 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1203,6 +1203,7 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, int8_t max_range; uint8_t max_node; uint64_t max_range_limit; + uint8_t byte; uint32_t dword; uint32_t dword2; uint64_t qword; @@ -1222,7 +1223,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8)); dword2 = Get_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8)); - qword = ((((uint64_t)dword) >> 16) & 0xffff) << 24; + qword = 0xffffff; + qword |= ((((uint64_t)dword) >> 16) & 0xffff) << 24; qword |= (((uint64_t)dword2) & 0xff) << 40; if (qword > max_range_limit) { @@ -1232,26 +1234,35 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, } } - if (pDCTstat->Node_ID == max_node) { - if (max_range >= 0) { - if (interleaved) - /* Move upper limit down by 16M * the number of nodes */ - max_range_limit -= (0x1000000 * num_nodes); - else - /* Move upper limit down by 16M */ - max_range_limit -= 0x1000000; - - /* Store modified range */ - dword = Get_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8)); - dword &= ~(0xffff << 16); /* DramLimit[39:24] = max_range_limit[39:24] */ - dword |= (max_range_limit >> 24) & 0xffff; - Set_NB32(pDCTstat->dev_map, 0x44 + (range * 0x8), dword); - - dword = Get_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8)); - dword &= ~(0xffff << 16); /* DramLimit[47:40] = max_range_limit[47:40] */ - dword |= (max_range_limit >> 40) & 0xff; - Set_NB32(pDCTstat->dev_map, 0x144 + (range * 0x8), dword); - } + if (max_range >= 0) { + if (interleaved) + /* Move upper limit down by 16M * the number of nodes */ + max_range_limit -= (0x1000000 * num_nodes); + else + /* Move upper limit down by 16M */ + max_range_limit -= 0x1000000; + + /* Disable the range */ + dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8)); + byte = dword & 0x3; + dword &= ~(0x3); + Set_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8), dword); + + /* Store modified range */ + dword = Get_NB32(pDCTstat->dev_map, 0x44 + (max_range * 0x8)); + dword &= ~(0xffff << 16); /* DramLimit[39:24] = max_range_limit[39:24] */ + dword |= ((max_range_limit >> 24) & 0xffff) << 16; + Set_NB32(pDCTstat->dev_map, 0x44 + (max_range * 0x8), dword); + + dword = Get_NB32(pDCTstat->dev_map, 0x144 + (max_range * 0x8)); + dword &= ~0xff; /* DramLimit[47:40] = max_range_limit[47:40] */ + dword |= (max_range_limit >> 40) & 0xff; + Set_NB32(pDCTstat->dev_map, 0x144 + (max_range * 0x8), dword); + + /* Reenable the range */ + dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8)); + dword |= byte; + Set_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8), dword); } /* Determine save state destination node */ @@ -1538,8 +1549,8 @@ restartinit: pDCTstat = pDCTstatA + Node; if (pDCTstat->NodePresent) { - lock_dram_config(pMCTstat, pDCTstat); set_cc6_save_enable(pMCTstat, pDCTstat, 1); + lock_dram_config(pMCTstat, pDCTstat); } } } @@ -5118,7 +5129,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat, /* get base/limit from Node0 */ reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */ val = Get_NB32(dev, reg); - Drambase = val >> ( 16 + 3); + Drambase = val >> (16 + 3); reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */ val = Get_NB32(dev, reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 0a51b1a..6ab33a3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -155,6 +155,14 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) if (MemClrECC) { MCTMemClrSync_D(pMCTstat, pDCTstatA); } + + if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { + /* Set up message triggered C1E */ + val = pci_read_config32(pDCTstat->dev_nbmisc, 0xd4); + val &= ~(0x1 << 15); /* StutterScrubEn = DRAM scrub enabled */ + val |= (mctGet_NVbits(NV_DramBKScrub)?1:0) << 15; + pci_write_config32(pDCTstat->dev_nbmisc, 0xd4, val); + } } /* if Node present */ } diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 57fda78..f109896 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -268,10 +268,6 @@ void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) byte &= ~(1<<6); pmio_write(0x8d, byte); - byte = pmio_read(0x61); - byte &= ~0x04; - pmio_write(0x61, byte); - byte = pmio_read(0x42); byte &= ~0x04; pmio_write(0x42, byte); @@ -583,6 +579,13 @@ static void sb700_devices_por_init(void) static void sb700_pmio_por_init(void) { u8 byte; + uint8_t enable_c_states; + + enable_c_states = 0; +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + if (get_option(&byte, "cpu_c_states") == CB_SUCCESS) + enable_c_states = !!byte; +#endif printk(BIOS_INFO, "sb700_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ @@ -644,6 +647,14 @@ static void sb700_pmio_por_init(void) byte |= 1 << 0; pmio_write(0xB2, byte); + /* Set up IOAPIC and BM_STS monitoring */ + byte = pmio_read(0x61); + if (enable_c_states) + byte |= 0x4; + else + byte &= ~0x04; + pmio_write(0x61, byte); + /* NOTE: Enabling automatic C1e state switch caused failures when initializing processors */ /* Enable precision HPET clock and automatic C state switch */ diff --git a/src/southbridge/amd/sb700/fadt.c b/src/southbridge/amd/sb700/fadt.c index 7a8a1a6..2417ceb 100644 --- a/src/southbridge/amd/sb700/fadt.c +++ b/src/southbridge/amd/sb700/fadt.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> +#include <cpu/amd/powernow.h> #include "sb700.h" void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) @@ -152,5 +154,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; + if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + amd_powernow_update_fadt(fadt); + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index a610267..f895811 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -32,10 +32,11 @@ #define ACPI_PM_EVT_BLK (SB700_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (SB700_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x0E) /* 1 byte */ -#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_PMA_CNT_BLK (SB700_ACPI_IO_BASE + 0x16) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB700_ACPI_IO_BASE + 0x20) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB700_ACPI_IO_BASE + 0x18) /* 8 bytes */ #define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */ extern void pm_iowrite(u8 reg, u8 value); extern u8 pm_ioread(u8 reg); diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index dc4b26f..04f4601 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -123,7 +123,10 @@ static void sm_init(device_t dev) pci_write_config8(dev, 0x41, byte); byte = pm_ioread(0x61); - byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ + if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + byte &= ~(1 << 1); /* Clear for non-K8 CPUs */ + else + byte |= 1 << 1; /* Set to enable NB/SB handshake during IOAPIC interrupt for AMD K8/K7 */ pm_iowrite(0x61, byte); /* disable SMI */ diff --git a/src/southbridge/amd/sb800/fadt.c b/src/southbridge/amd/sb800/fadt.c index 763fd13..ce64036 100644 --- a/src/southbridge/amd/sb800/fadt.c +++ b/src/southbridge/amd/sb800/fadt.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> +#include <cpu/amd/powernow.h> #include "sb800.h" void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) @@ -152,5 +154,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0; + if (IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)) + amd_powernow_update_fadt(fadt); + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h index a30a447..6a037cf 100644 --- a/src/southbridge/amd/sb800/sb800.h +++ b/src/southbridge/amd/sb800/sb800.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,10 +32,11 @@ #define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ #define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0F) /* 1 byte */ -#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x17) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x20) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x18) /* 8 bytes */ #define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */ +#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */ void pm_iowrite(u8 reg, u8 value); u8 pm_ioread(u8 reg);

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Set SP5100 subtype
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11994 -gerrit commit 49d374f5d1da9e18b210209ac3786eb910d7b28d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 18 12:37:08 2015 -0500 mainboard/asus/kgpe-d16: Set SP5100 subtype Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index c4528e5..c4f3962 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SR5650 select SOUTHBRIDGE_AMD_SB700 select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA + select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 select SUPERIO_NUVOTON_NCT5572D select PARALLEL_CPU_INIT select HAVE_HARD_RESET

1 0

Patch set updated for coreboot: northbridge/amd/amdmct: Fix hang on boot due to invalid array access
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11989 -gerrit commit 5ed2960597ce68d4ac988f3e5e44d35d1f5f5236 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 12 19:43:06 2015 -0500 northbridge/amd/amdmct: Fix hang on boot due to invalid array access Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 95d57fc..9196863 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -341,7 +341,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ uint8_t dimm; - for (i = 0; i < 15; i = i + 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; if (pDCTstat->DIMMValid & (1 << (i + 1))) @@ -351,7 +351,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) for (i = 0; i < 2; i++) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i]; highest_rank_count[i] = 0x0; - for (dimm = 0; dimm < 8; dimm++) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTData->DimmRanks[dimm] > highest_rank_count[i]) highest_rank_count[i] = pDCTData->DimmRanks[dimm]; }

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11988 -gerrit commit 9afbbad2a36e971f6fc053db7093e06d56fc4a93 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 12 13:32:52 2015 -0500 mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 74 +++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 63d85e8..8445eb3 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -292,13 +292,29 @@ DefinitionBlock ( Name (PR03, Package () { /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 44 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 45 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 46 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 47 }, + }) + + Name (PR04, Package () { + /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR03, Package () { + Name (AR04, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 48 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 49 }, @@ -306,7 +322,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 51 }, }) - Name (PR04, Package () { + Name (PR05, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 }, @@ -314,7 +330,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 }, }) - Name (AR04, Package () { + Name (AR05, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 47 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 44 }, @@ -322,7 +338,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 46 }, }) - Name (PR05, Package () { + Name (PR06, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, @@ -330,7 +346,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR05, Package () { + Name (AR06, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 32 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 33 }, @@ -338,7 +354,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 35 }, }) - Name (PR06, Package () { + Name (PR07, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, @@ -346,7 +362,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, }) - Name (AR06, Package () { + Name (AR07, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 36 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 37 }, @@ -354,7 +370,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 39 }, }) - Name (PR07, Package () { + Name (PR08, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, @@ -362,7 +378,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR07, Package () { + Name (AR08, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 40 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 41 }, @@ -613,6 +629,26 @@ DefinitionBlock ( } } + /* 1:00.0 PIKE */ + Device (PIKE) + { + Name (_ADR, 0x00040000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + /* 3:00.0 PCIe NIC A */ Device (NICA) { @@ -621,9 +657,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR03) + Return (AR04) } Else { - Return (PR03) + Return (PR04) } } Device (BDC1) @@ -640,9 +676,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR04) + Return (AR05) } Else { - Return (PR04) + Return (PR05) } } Device (BDC2) @@ -659,9 +695,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR05) + Return (AR06) } Else { - Return (PR05) + Return (PR06) } } Device (SLT1) @@ -679,9 +715,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR06) + Return (AR07) } Else { - Return (PR06) + Return (PR07) } } Device (SLT1) @@ -699,9 +735,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR07) + Return (AR08) } Else { - Return (PR07) + Return (PR08) } } Device (SLT1)

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12400 -gerrit commit a89a773577ba5f624d922371e98ab17035364ae5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 18:26:52 2015 -0600 mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index c841aa9..dc698d0 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -16,6 +16,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +sata_ahci_mode = Enable ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 40799d5..dfd5159 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -40,7 +40,8 @@ entries 464 1 e 2 compute_unit_siblings 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state -467 1 r 0 allow_spd_nvram_cache_restore +467 1 e 1 sata_ahci_mode +468 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Add ability to set maximum P-state limit
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11985 -gerrit commit fe7843f4add56700daff9f5d627091b512eae3e4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 00:35:05 2015 -0500 northbridge/amd/amdfam10: Add ability to set maximum P-state limit Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- src/northbridge/amd/amdfam10/misc_control.c | 24 ++++++++++++++++++++---- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index dc698d0..0b87c91 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable sata_ahci_mode = Enable +maximum_p_state_limit = 0xf ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index dfd5159..19c7e7d 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -41,7 +41,8 @@ entries 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode -468 1 r 0 allow_spd_nvram_cache_restore +468 4 h 0 maximum_p_state_limit +473 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 24c422d..847b599 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -120,16 +120,32 @@ static void mcf3_set_resources(device_t dev) static void misc_control_init(struct device *dev) { - u32 cmd; + uint32_t dword; + uint8_t nvram; + uint8_t boost_limit; + uint8_t current_boost; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ - cmd = pci_read_config32(dev, 0x44); - cmd |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, cmd ); + dword = pci_read_config32(dev, 0x44); + dword |= (1<<6) | (1<<25); + pci_write_config32(dev, 0x44, dword); + + boost_limit = 0xf; + if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS) + boost_limit = nvram & 0xf; + + /* Set P-state maximum value */ + dword = pci_read_config32(dev, 0xdc); + current_boost = (dword >> 8) & 0x7; + if (boost_limit > current_boost) + boost_limit = current_boost; + dword &= ~(0x7 << 8); + dword |= (boost_limit & 0x7) << 8; + pci_write_config32(dev, 0xdc, dword); printk(BIOS_DEBUG, "done.\n"); }

1 0

Patch set updated for coreboot: src/northbridge/amd/amdmct: Add option to override bad SPD checksum
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11987 -gerrit commit 058cf14316c87d81a3a7d033231e797b0f90ec12 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 11 16:14:15 2015 -0500 src/northbridge/amd/amdmct: Add option to override bad SPD checksum Certain DIMMs, for example DIMMs on which the EEPROM has been modified by the end user, may not contain a valid SPD checksum. While this is not a normal condition, it may be useful to allow a checksum override while memory timing parameters are being altered, e.g. in the course of overclocking or underclocking, or when recovering from a bad SPD write. This is an advanced level feature primarily useful for debugging and development. Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 6 +++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 +++-- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 0b87c91..3473bc9 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -8,6 +8,7 @@ nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 minimum_memory_voltage = 1.5V +dimm_spd_checksum = Enforce ECC_memory = Enable ECC_redirection = Enable ecc_scrub_rate = 1.28us diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 19c7e7d..0bc6db8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -42,7 +42,8 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 4 h 0 maximum_p_state_limit -473 1 r 0 allow_spd_nvram_cache_restore +472 2 e 13 dimm_spd_checksum +474 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum @@ -137,6 +138,9 @@ enumerations 12 1 1.35V 12 2 1.25V 12 3 1.15V +13 0 Enforce +13 1 Ignore +13 2 Override checksums diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2841b18..4bfb08a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1456,7 +1456,7 @@ restartinit: } } if (NodesWmem == 0) { - printk(BIOS_DEBUG, "No Nodes?!\n"); + printk(BIOS_ALERT, "Unable to detect valid memory on any nodes. Halting!\n"); goto fatalexit; } @@ -3892,13 +3892,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, read_spd_bytes(pMCTstat, pDCTstat, i); crc_status = crcCheck(pDCTstat, i); } - if (crc_status) { /* CRC is OK */ + if ((crc_status) || (SPDCtrl == 2)) { /* CRC is OK */ byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ pDCTstat->DIMMValid |= 1 << i; } } else { + printk(BIOS_WARNING, "Node %d DIMM %d: SPD checksum invalid\n", pDCTstat->Node_ID, i); pDCTstat->DIMMSPDCSE = 1 << i; if (SPDCtrl == 0) { pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index a030f71..95d57fc 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -146,6 +146,14 @@ static u16 mctGet_NVbits(u8 index) case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */ + //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */ + + if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) + val = nvram & 0x3; + + if (val > 2) + val = 2; + break; case NV_DQSTrainCTL: //val = 0; /*Skip dqs training */

1 0

Patch set updated for coreboot: northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11986 -gerrit commit 7f762f4cec11b75ad3aa92c163ff9a66f6143e71 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 10:46:17 2015 -0500 northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2d8ab34..2841b18 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -4134,7 +4134,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); - if (load_spd_hashes_from_nvram(pDCTstat) < 0) { + if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; } else { @@ -4149,6 +4149,13 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) + allow_config_restore = 0; +#else + allow_config_restore = 0; +#endif + if (!allow_config_restore) pDCTstat->spd_data.nvram_spd_match = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 196d96d..425f1ef 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -297,6 +297,7 @@ struct MCTStatStruc { u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ uint32_t TSCFreq; + uint16_t nvram_checksum; } __attribute__((packed)); /*============================================================================= @@ -792,6 +793,7 @@ struct amd_s3_persistent_node_data { struct amd_s3_persistent_data { struct amd_s3_persistent_node_data node[MAX_NODES_SUPPORTED]; + uint16_t nvram_checksum; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 0a508cb..6e92f3a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -139,6 +139,36 @@ void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) *spd_hash = *spd_hash ^ (*spd_hash << 37); } +uint16_t calculate_nvram_mct_hash(void) +{ + uint32_t nvram; + uint16_t ret; + + ret = 0; + if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) + ret |= nvram & 0xf; + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) + ret |= (nvram & 0x3) << 4; + if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) + ret |= (nvram & 0x1) << 6; + if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) + ret |= (nvram & 0x1) << 7; + if (get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) + ret |= (nvram & 0x1) << 8; + if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) + ret |= (nvram & 0x1) << 9; + if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) + ret |= (nvram & 0x1) << 10; + if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) + ret |= (nvram & 0x1) << 11; + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + ret |= (nvram & 0x1) << 12; + if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) + ret |= (nvram & 0x1) << 13; + + return ret; +} + static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) { ssize_t s3nv_offset; @@ -169,7 +199,7 @@ static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) } #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { struct amd_s3_persistent_data *persistent_data; @@ -180,6 +210,8 @@ int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); + pMCTstat->nvram_checksum = persistent_data->nvram_checksum; + return 0; } #endif @@ -233,6 +265,8 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + persistent_data->nvram_checksum = calculate_nvram_mct_hash(); + if (restored) { if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) *restored = 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 56e627e..8a72695 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -17,9 +17,10 @@ #include "mct_d.h" void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); +uint16_t calculate_nvram_mct_hash(void); #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat); +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); #endif #ifdef __RAMSTAGE__

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015