the following patch was just integrated into master:
commit 737c54d4d32dfe02b629ba7f4e86de4119c30d86
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Fri Nov 6 08:22:22 2015 +0100
fsp_baytrail: Add macros for legacy GPIO output set up
Up to now the GPIO set up macros for input sets up GPIOs to be
mapped to memory space while macros for outputs sets up GPIOs
to be mapped to legacy io space. This patch adds two additional
macros for legacy output definition and changes the old macros
to memory space mapping.
In addition, the intel/minnowmax mainboard is modified to use
the legacy macros for outputs to ensure this mainboard stays
unchanged in terms of functionality.
TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux.
Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: http://review.coreboot.org/12340
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/12340 for details.
-gerrit
the following patch was just integrated into master:
commit 74e03a4fdd597a027e41f826a8f1d9ec5b21c17f
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Fri Jun 5 21:14:23 2015 -0500
mainboard/asus/kgpe-d16: Enable CC6
Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/11978 for details.
-gerrit
the following patch was just integrated into master:
commit cfb93e70bf9a97bd7172b82b979d71295f312e88
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Fri Jun 5 21:13:30 2015 -0500
northbridge/amd/amdfam10: Enable CC6 DRAM save area setup
Change-Id: Ibeb35da3395dc77a21a2f92f0e1d0845be53d175
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11977
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/11977 for details.
-gerrit
the following patch was just integrated into master:
commit df1fb9c05f822b5a84c802617d3bad7d049dcd76
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Thu Jun 4 00:11:03 2015 -0500
amd/amdmct/mct_ddr3: Use training values from previous boot if possible
DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid. Use them
if the DIMM configuration has not changed since the last boot.
The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device. If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.
Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/11976 for details.
-gerrit
the following patch was just integrated into master:
commit 1b708656b2f347ab05bd89643322f86b7110a814
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 10 20:14:52 2015 -0600
southbridge/amd/sb700: Fix build failure from merging patches out of order
Change-Id: Ib6d1be64691cf5a1c0b7464284fbae4e583f383e
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12402
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/12402 for details.
-gerrit
the following patch was just integrated into master:
commit 86fc11d0c9b799f916d69ced72dc8a26a07591a2
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Oct 9 13:37:58 2015 -0700
arm/arm64: Generalize bootblock C entry point
When we first added ARM support to coreboot, it was clear that the
bootblock would need to do vastly different tasks than on x86, so we
moved its main logic under arch/. Now that we have several more
architectures, it turns out (as with so many things lately) that x86 is
really the odd one out, and all the others are trying to do pretty much
the same thing. This has already caused maintenance issues as the ARM32
bootblock developed and less-mature architectures were left behind with
old cruft.
This patch tries to address that problem by centralizing that logic
under lib/ for use by all architectures/SoCs that don't explicitly
opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option).
This works great out of the box for ARM32 and ARM64. It could probably
be easily applied to MIPS and RISCV as well, but I don't have any of
those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and
leave that for later cleanup.
BRANCH=None
BUG=None
TEST=Built Jerry and Falco, booted Oak.
Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/12076
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/12076 for details.
-gerrit