coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

Patch set updated for coreboot: northbridge/amd/amdmct: Fix hang on boot due to invalid array access
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11989 -gerrit commit d400f7d773a61ecc9301901343ffb2dd014eb7df Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 12 19:43:06 2015 -0500 northbridge/amd/amdmct: Fix hang on boot due to invalid array access Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 95d57fc..9196863 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -341,7 +341,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ uint8_t dimm; - for (i = 0; i < 15; i = i + 2) { + for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) { if (pDCTstat->DIMMValid & (1 << i)) ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i]; if (pDCTstat->DIMMValid & (1 << (i + 1))) @@ -351,7 +351,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) for (i = 0; i < 2; i++) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i]; highest_rank_count[i] = 0x0; - for (dimm = 0; dimm < 8; dimm++) { + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTData->DimmRanks[dimm] > highest_rank_count[i]) highest_rank_count[i] = pDCTData->DimmRanks[dimm]; }

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11988 -gerrit commit b638e7938c1883cae593b1ab2f27a6b7bc12b7fa Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 12 13:32:52 2015 -0500 mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 74 +++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 19 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 63d85e8..8445eb3 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -292,13 +292,29 @@ DefinitionBlock ( Name (PR03, Package () { /* PIC */ + Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0xFFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, + }) + + Name (AR03, Package () { + /* APIC */ + Package (0x04) { 0xFFFF, 0x00, 0x00, 44 }, + Package (0x04) { 0xFFFF, 0x01, 0x00, 45 }, + Package (0x04) { 0xFFFF, 0x02, 0x00, 46 }, + Package (0x04) { 0xFFFF, 0x03, 0x00, 47 }, + }) + + Name (PR04, Package () { + /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 }, Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR03, Package () { + Name (AR04, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 48 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 49 }, @@ -306,7 +322,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 51 }, }) - Name (PR04, Package () { + Name (PR05, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKH, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKE, 0x00 }, @@ -314,7 +330,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKG, 0x00 }, }) - Name (AR04, Package () { + Name (AR05, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 47 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 44 }, @@ -322,7 +338,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 46 }, }) - Name (PR05, Package () { + Name (PR06, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, @@ -330,7 +346,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR05, Package () { + Name (AR06, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 32 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 33 }, @@ -338,7 +354,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 35 }, }) - Name (PR06, Package () { + Name (PR07, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKE, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKF, 0x00 }, @@ -346,7 +362,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKH, 0x00 }, }) - Name (AR06, Package () { + Name (AR07, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 36 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 37 }, @@ -354,7 +370,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, 0x00, 39 }, }) - Name (PR07, Package () { + Name (PR08, Package () { /* PIC */ Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 }, @@ -362,7 +378,7 @@ DefinitionBlock ( Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 }, }) - Name (AR07, Package () { + Name (AR08, Package () { /* APIC */ Package (0x04) { 0xFFFF, 0x00, 0x00, 40 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 41 }, @@ -613,6 +629,26 @@ DefinitionBlock ( } } + /* 1:00.0 PIKE */ + Device (PIKE) + { + Name (_ADR, 0x00040000) // _ADR: Address + Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (PICM) { + Return (AR03) + } Else { + Return (PR03) + } + } + Device (SLT1) + { + Name (_ADR, 0xFFFF) // _ADR: Address + Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 + } + } + /* 3:00.0 PCIe NIC A */ Device (NICA) { @@ -621,9 +657,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR03) + Return (AR04) } Else { - Return (PR03) + Return (PR04) } } Device (BDC1) @@ -640,9 +676,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR04) + Return (AR05) } Else { - Return (PR04) + Return (PR05) } } Device (BDC2) @@ -659,9 +695,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR05) + Return (AR06) } Else { - Return (PR05) + Return (PR06) } } Device (SLT1) @@ -679,9 +715,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR06) + Return (AR07) } Else { - Return (PR06) + Return (PR07) } } Device (SLT1) @@ -699,9 +735,9 @@ DefinitionBlock ( Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (AR07) + Return (AR08) } Else { - Return (PR07) + Return (PR08) } } Device (SLT1)

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12400 -gerrit commit 632d0f1dc52b6c37a6078123a00128daa7618a13 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 18:26:52 2015 -0600 mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index c841aa9..dc698d0 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -16,6 +16,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +sata_ahci_mode = Enable ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 40799d5..dfd5159 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -40,7 +40,8 @@ entries 464 1 e 2 compute_unit_siblings 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state -467 1 r 0 allow_spd_nvram_cache_restore +467 1 e 1 sata_ahci_mode +468 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum

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Patch set updated for coreboot: northbridge/amd/amdfam10: Add ability to set maximum P-state limit
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11985 -gerrit commit 94215824d993698bd79982230adc7ca9853c3bf7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 00:35:05 2015 -0500 northbridge/amd/amdfam10: Add ability to set maximum P-state limit Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 3 ++- src/northbridge/amd/amdfam10/misc_control.c | 24 ++++++++++++++++++++---- 3 files changed, 23 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index dc698d0..0b87c91 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable sata_ahci_mode = Enable +maximum_p_state_limit = 0xf ieee1394_controller = Enable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index dfd5159..19c7e7d 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -41,7 +41,8 @@ entries 465 1 e 1 cpu_c_states 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode -468 1 r 0 allow_spd_nvram_cache_restore +468 4 h 0 maximum_p_state_limit +473 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 24c422d..847b599 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -120,16 +120,32 @@ static void mcf3_set_resources(device_t dev) static void misc_control_init(struct device *dev) { - u32 cmd; + uint32_t dword; + uint8_t nvram; + uint8_t boost_limit; + uint8_t current_boost; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ - cmd = pci_read_config32(dev, 0x44); - cmd |= (1<<6) | (1<<25); - pci_write_config32(dev, 0x44, cmd ); + dword = pci_read_config32(dev, 0x44); + dword |= (1<<6) | (1<<25); + pci_write_config32(dev, 0x44, dword); + + boost_limit = 0xf; + if (get_option(&nvram, "maximum_p_state_limit") == CB_SUCCESS) + boost_limit = nvram & 0xf; + + /* Set P-state maximum value */ + dword = pci_read_config32(dev, 0xdc); + current_boost = (dword >> 8) & 0x7; + if (boost_limit > current_boost) + boost_limit = current_boost; + dword &= ~(0x7 << 8); + dword |= (boost_limit & 0x7) << 8; + pci_write_config32(dev, 0xdc, dword); printk(BIOS_DEBUG, "done.\n"); }

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Patch set updated for coreboot: src/northbridge/amd/amdmct: Add option to override bad SPD checksum
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11987 -gerrit commit d7539f2b3d76c5c73a65c622b31fa4f75240e4fb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 11 16:14:15 2015 -0500 src/northbridge/amd/amdmct: Add option to override bad SPD checksum Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 6 +++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 5 +++-- src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 ++++++++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 0b87c91..3473bc9 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -8,6 +8,7 @@ nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 minimum_memory_voltage = 1.5V +dimm_spd_checksum = Enforce ECC_memory = Enable ECC_redirection = Enable ecc_scrub_rate = 1.28us diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 19c7e7d..0bc6db8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -42,7 +42,8 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 4 h 0 maximum_p_state_limit -473 1 r 0 allow_spd_nvram_cache_restore +472 2 e 13 dimm_spd_checksum +474 1 r 0 allow_spd_nvram_cache_restore 477 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum @@ -137,6 +138,9 @@ enumerations 12 1 1.35V 12 2 1.25V 12 3 1.15V +13 0 Enforce +13 1 Ignore +13 2 Override checksums diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2841b18..4bfb08a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1456,7 +1456,7 @@ restartinit: } } if (NodesWmem == 0) { - printk(BIOS_DEBUG, "No Nodes?!\n"); + printk(BIOS_ALERT, "Unable to detect valid memory on any nodes. Halting!\n"); goto fatalexit; } @@ -3892,13 +3892,14 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, read_spd_bytes(pMCTstat, pDCTstat, i); crc_status = crcCheck(pDCTstat, i); } - if (crc_status) { /* CRC is OK */ + if ((crc_status) || (SPDCtrl == 2)) { /* CRC is OK */ byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE]; if (byte == JED_DDR3SDRAM) { /*Dimm is 'Present'*/ pDCTstat->DIMMValid |= 1 << i; } } else { + printk(BIOS_WARNING, "Node %d DIMM %d: SPD checksum invalid\n", pDCTstat->Node_ID, i); pDCTstat->DIMMSPDCSE = 1 << i; if (SPDCtrl == 0) { pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index a030f71..95d57fc 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -146,6 +146,14 @@ static u16 mctGet_NVbits(u8 index) case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node intialization */ + //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */ + + if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) + val = nvram & 0x3; + + if (val > 2) + val = 2; + break; case NV_DQSTrainCTL: //val = 0; /*Skip dqs training */

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Patch set updated for coreboot: northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11986 -gerrit commit 4fb07ceaed6aaef1fc5931c644acd2024375d852 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 10 10:46:17 2015 -0500 northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 ++++++- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 ++ src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 36 ++++++++++++++++++++++++++- src/northbridge/amd/amdmct/mct_ddr3/s3utils.h | 3 ++- 4 files changed, 47 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 2d8ab34..2841b18 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -4134,7 +4134,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); - if (load_spd_hashes_from_nvram(pDCTstat) < 0) { + if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; } else { @@ -4149,6 +4149,13 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) + allow_config_restore = 0; +#else + allow_config_restore = 0; +#endif + if (!allow_config_restore) pDCTstat->spd_data.nvram_spd_match = 0; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 196d96d..425f1ef 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -297,6 +297,7 @@ struct MCTStatStruc { u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ uint32_t TSCFreq; + uint16_t nvram_checksum; } __attribute__((packed)); /*============================================================================= @@ -792,6 +793,7 @@ struct amd_s3_persistent_node_data { struct amd_s3_persistent_data { struct amd_s3_persistent_node_data node[MAX_NODES_SUPPORTED]; + uint16_t nvram_checksum; } __attribute__((packed)); /*=============================================================================== diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 0a508cb..6e92f3a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -139,6 +139,36 @@ void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash) *spd_hash = *spd_hash ^ (*spd_hash << 37); } +uint16_t calculate_nvram_mct_hash(void) +{ + uint32_t nvram; + uint16_t ret; + + ret = 0; + if (get_option(&nvram, "max_mem_clock") == CB_SUCCESS) + ret |= nvram & 0xf; + if (get_option(&nvram, "minimum_memory_voltage") == CB_SUCCESS) + ret |= (nvram & 0x3) << 4; + if (get_option(&nvram, "ECC_memory") == CB_SUCCESS) + ret |= (nvram & 0x1) << 6; + if (get_option(&nvram, "ECC_redirection") == CB_SUCCESS) + ret |= (nvram & 0x1) << 7; + if (get_option(&nvram, "ecc_scrub_rate") == CB_SUCCESS) + ret |= (nvram & 0x1) << 8; + if (get_option(&nvram, "interleave_chip_selects") == CB_SUCCESS) + ret |= (nvram & 0x1) << 9; + if (get_option(&nvram, "interleave_nodes") == CB_SUCCESS) + ret |= (nvram & 0x1) << 10; + if (get_option(&nvram, "interleave_memory_channels") == CB_SUCCESS) + ret |= (nvram & 0x1) << 11; + if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS) + ret |= (nvram & 0x1) << 12; + if (get_option(&nvram, "cpu_cc6_state") == CB_SUCCESS) + ret |= (nvram & 0x1) << 13; + + return ret; +} + static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) { ssize_t s3nv_offset; @@ -169,7 +199,7 @@ static struct amd_s3_persistent_data * map_s3nv_in_nvram(void) } #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { struct amd_s3_persistent_data *persistent_data; @@ -180,6 +210,8 @@ int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat) memcpy(pDCTstat->spd_data.nvram_spd_hash, persistent_data->node[pDCTstat->Node_ID].spd_hash, sizeof(pDCTstat->spd_data.nvram_spd_hash)); memcpy(pDCTstat->spd_data.nvram_memclk, persistent_data->node[pDCTstat->Node_ID].memclk, sizeof(pDCTstat->spd_data.nvram_memclk)); + pMCTstat->nvram_checksum = persistent_data->nvram_checksum; + return 0; } #endif @@ -233,6 +265,8 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* for (channel = 0; channel < 2; channel++) persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; + persistent_data->nvram_checksum = calculate_nvram_mct_hash(); + if (restored) { if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) *restored = 1; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h index 56e627e..8a72695 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.h @@ -17,9 +17,10 @@ #include "mct_d.h" void calculate_spd_hash(uint8_t *spd_data, uint64_t *spd_hash); +uint16_t calculate_nvram_mct_hash(void); #ifdef __PRE_RAM__ -int8_t load_spd_hashes_from_nvram(struct DCTStatStruc *pDCTstat); +int8_t load_spd_hashes_from_nvram(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); #endif #ifdef __RAMSTAGE__

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Set correct supported SATA port count
by gerrit＠coreboot.org 10 Nov '15

10 Nov '15

the following patch was just integrated into master: commit 95b97848cc96682e9574076001bfde23488b27b5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 19:20:42 2015 -0600 mainboard/asus/kgpe-d16: Set correct supported SATA port count Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12401 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12401 for details. -gerrit

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Patch merged into coreboot/master: southbridge/amd/sb700: Disable broken SATA MSI functionality
by gerrit＠coreboot.org 10 Nov '15

10 Nov '15

the following patch was just integrated into master: commit 22dfccf5b78ba87b015172200de0356648172210 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 9 19:12:35 2015 -0500 southbridge/amd/sb700: Disable broken SATA MSI functionality Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11983 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11983 for details. -gerrit

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Patch set updated for coreboot: southbridge/amd/sb700: Do drive detection even in AHCI mode
by Stefan Reinauer 10 Nov '15

10 Nov '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11997 -gerrit commit b636898bceed0d8c2bf78da79490de4a92dbdbeb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 21:31:15 2015 -0500 southbridge/amd/sb700: Do drive detection even in AHCI mode SeaBIOS AHCI drive detection randomly fails for drives present on the secondary channel of each AHCI SATA BAR. Forcing native drive detection in AHCI mode resolves this issue. Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 99 +++++++++++++++++++++------------------- 1 file changed, 53 insertions(+), 46 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index fdf32c7..8a2496e 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -285,65 +285,72 @@ static void sata_init(struct device *dev) if (port_count > max_port_count) port_count = max_port_count; - if (!sata_ahci_mode) { - /* RPR7.7 SATA drive detection. */ - /* Use BAR5+0x128,BAR0 for Primary Slave */ - /* Use BAR5+0x1A8,BAR0 for Primary Slave */ - /* Use BAR5+0x228,BAR2 for Secondary Master */ - /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ - /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ - /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ - for (i = 0; i < port_count; i++) { + /* RPR7.7 SATA drive detection. */ + /* Use BAR5+0x128,BAR0 for Primary Slave */ + /* Use BAR5+0x1A8,BAR0 for Primary Slave */ + /* Use BAR5+0x228,BAR2 for Secondary Master */ + /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ + /* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */ + /* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */ + for (i = 0; i < port_count; i++) { + byte = read8(sata_bar5 + 0x128 + 0x80 * i); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); + byte &= 0xF; + if (byte == 0x1) { + /* If the drive status is 0x1 then we see it but we aren't talking to it. */ + /* Try to do something about it. */ + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); + + /* Read in Port-N Serial ATA Control Register */ + byte = read8(sata_bar5 + 0x12C + 0x80 * i); + + /* Set Reset Bit and 1.5g bit */ + byte |= 0x11; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + + /* Clear Reset Bit */ + byte &= ~0x01; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + + /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; - if (byte == 0x1) { - /* If the drive status is 0x1 then we see it but we aren't talking to it. */ - /* Try to do something about it. */ - printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); - - /* Read in Port-N Serial ATA Control Register */ - byte = read8(sata_bar5 + 0x12C + 0x80 * i); - - /* Set Reset Bit and 1.5g bit */ - byte |= 0x11; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); - - /* Clear Reset Bit */ - byte &= ~0x01; - write8((sata_bar5 + 0x12C + 0x80 * i), byte); - - /* Wait 1ms */ - mdelay(1); + } - /* Reread status */ - byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); - byte &= 0xF; + if (byte == 0x3) { + for (j = 0; j < 10; j++) { + if (i < 4) + current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; + else + current_bar = ide_bar0; + if (!sata_drive_detect(i, current_bar)) + break; } - - if (byte == 0x3) { - for (j = 0; j < 10; j++) { - if (i < 4) - current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; - else - current_bar = ide_bar0; - if (!sata_drive_detect(i, current_bar)) - break; - } + if (sata_ahci_mode) + printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n", + i, + (j == 10) ? "not " : "", + (j == 10) ? j : j + 1); + else printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); - } else { + } else { + if (sata_ahci_mode) + printk(BIOS_DEBUG, "No AHCI SATA drive on Slot%i\n", i); + else printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); - } } }

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New patch to review for coreboot: mainboard/asus/kgpe-d16: Set correct supported SATA port count
by Timothy Pearson 10 Nov '15

10 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12401 -gerrit commit cc08f8158667903ea4f5c6c0f004fa7fb70d0649 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 10 19:20:42 2015 -0600 mainboard/asus/kgpe-d16: Set correct supported SATA port count Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 29061ca..c4528e5 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -80,6 +80,10 @@ config IRQ_SLOT_COUNT int default 13 +config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD + hex + default 0x3f + config ONBOARD_VGA_IS_PRIMARY bool default y

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coreboot-gerrit November 2015